Angel Pons | f23ae0b | 2020-04-02 23:48:12 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Arthur Heymans | dd4d895 | 2018-06-03 12:04:26 +0200 | [diff] [blame] | 2 | |
Martin Roth | c87ab01 | 2022-11-20 19:32:51 -0700 | [diff] [blame] | 3 | #include <cpu/intel/post_codes.h> |
Arthur Heymans | dd4d895 | 2018-06-03 12:04:26 +0200 | [diff] [blame] | 4 | #include <cpu/x86/mtrr.h> |
| 5 | #include <cpu/x86/cache.h> |
| 6 | #include <cpu/x86/post_code.h> |
| 7 | |
Arthur Heymans | dd4d895 | 2018-06-03 12:04:26 +0200 | [diff] [blame] | 8 | #define NoEvictMod_MSR 0x2e0 |
Arthur Heymans | 19e7273 | 2019-01-11 23:56:51 +0100 | [diff] [blame] | 9 | #define BBL_CR_CTL3_MSR 0x11e |
Arthur Heymans | dd4d895 | 2018-06-03 12:04:26 +0200 | [diff] [blame] | 10 | |
Kyösti Mälkki | 7522a8f | 2020-11-20 16:47:38 +0200 | [diff] [blame] | 11 | .section .init |
Kyösti Mälkki | c641f7e | 2018-12-28 16:54:54 +0200 | [diff] [blame] | 12 | .global bootblock_pre_c_entry |
| 13 | |
Patrick Rudolph | 49da0cf | 2020-09-24 18:57:43 +0200 | [diff] [blame] | 14 | #include <cpu/intel/car/cache_as_ram_symbols.inc> |
| 15 | |
Arthur Heymans | dd4d895 | 2018-06-03 12:04:26 +0200 | [diff] [blame] | 16 | .code32 |
| 17 | _cache_as_ram_setup: |
| 18 | |
Kyösti Mälkki | c641f7e | 2018-12-28 16:54:54 +0200 | [diff] [blame] | 19 | bootblock_pre_c_entry: |
Arthur Heymans | 8e646e7 | 2018-06-05 11:19:22 +0200 | [diff] [blame] | 20 | movl $cache_as_ram, %esp /* return address */ |
| 21 | jmp check_mtrr /* Check if CPU properly reset */ |
Arthur Heymans | 8e646e7 | 2018-06-05 11:19:22 +0200 | [diff] [blame] | 22 | |
Arthur Heymans | dd4d895 | 2018-06-03 12:04:26 +0200 | [diff] [blame] | 23 | cache_as_ram: |
lilacious | 40cb3fe | 2023-06-21 23:24:14 +0200 | [diff] [blame^] | 24 | post_code(POSTCODE_BOOTBLOCK_CAR) |
Arthur Heymans | dd4d895 | 2018-06-03 12:04:26 +0200 | [diff] [blame] | 25 | |
| 26 | /* Send INIT IPI to all excluding ourself. */ |
| 27 | movl $0x000C4500, %eax |
| 28 | movl $0xFEE00300, %esi |
| 29 | movl %eax, (%esi) |
| 30 | |
| 31 | /* All CPUs need to be in Wait for SIPI state */ |
| 32 | wait_for_sipi: |
| 33 | movl (%esi), %eax |
| 34 | bt $12, %eax |
| 35 | jc wait_for_sipi |
| 36 | |
Martin Roth | c87ab01 | 2022-11-20 19:32:51 -0700 | [diff] [blame] | 37 | post_code(POST_SOC_SET_DEF_MTRR_TYPE) |
Arthur Heymans | dd4d895 | 2018-06-03 12:04:26 +0200 | [diff] [blame] | 38 | /* Clean-up MTRR_DEF_TYPE_MSR. */ |
| 39 | movl $MTRR_DEF_TYPE_MSR, %ecx |
| 40 | xorl %eax, %eax |
| 41 | xorl %edx, %edx |
| 42 | wrmsr |
| 43 | |
Martin Roth | c87ab01 | 2022-11-20 19:32:51 -0700 | [diff] [blame] | 44 | post_code(POST_SOC_CLEAR_FIXED_MTRRS) |
Arthur Heymans | c2ccc97 | 2018-06-03 12:09:52 +0200 | [diff] [blame] | 45 | /* Clear/disable fixed MTRRs */ |
Arthur Heymans | 2834d98 | 2022-11-08 15:06:42 +0100 | [diff] [blame] | 46 | mov $fixed_mtrr_list, %ebx |
Arthur Heymans | c2ccc97 | 2018-06-03 12:09:52 +0200 | [diff] [blame] | 47 | xor %eax, %eax |
| 48 | xor %edx, %edx |
| 49 | |
| 50 | clear_fixed_mtrr: |
Arthur Heymans | 2834d98 | 2022-11-08 15:06:42 +0100 | [diff] [blame] | 51 | movzwl (%ebx), %ecx |
Arthur Heymans | dd4d895 | 2018-06-03 12:04:26 +0200 | [diff] [blame] | 52 | wrmsr |
Arthur Heymans | 2834d98 | 2022-11-08 15:06:42 +0100 | [diff] [blame] | 53 | add $2, %ebx |
| 54 | cmp $fixed_mtrr_list_end, %ebx |
| 55 | jl clear_fixed_mtrr |
Arthur Heymans | dd4d895 | 2018-06-03 12:04:26 +0200 | [diff] [blame] | 56 | |
| 57 | /* Zero out all variable range MTRRs. */ |
| 58 | movl $MTRR_CAP_MSR, %ecx |
| 59 | rdmsr |
| 60 | andl $0xff, %eax |
| 61 | shl $1, %eax |
| 62 | movl %eax, %edi |
| 63 | movl $0x200, %ecx |
| 64 | xorl %eax, %eax |
| 65 | xorl %edx, %edx |
| 66 | clear_var_mtrrs: |
| 67 | wrmsr |
| 68 | add $1, %ecx |
| 69 | dec %edi |
| 70 | jnz clear_var_mtrrs |
| 71 | |
Arthur Heymans | c2ccc97 | 2018-06-03 12:09:52 +0200 | [diff] [blame] | 72 | /* Determine CPU_ADDR_BITS and load PHYSMASK high word to %edx. */ |
| 73 | movl $0x80000008, %eax |
| 74 | cpuid |
| 75 | movb %al, %cl |
| 76 | sub $32, %cl |
| 77 | movl $1, %edx |
| 78 | shl %cl, %edx |
| 79 | subl $1, %edx |
| 80 | |
| 81 | /* Preload high word of address mask (in %edx) for Variable |
| 82 | * MTRRs 0 and 1. |
| 83 | */ |
| 84 | addrsize_set_high: |
| 85 | xorl %eax, %eax |
| 86 | movl $MTRR_PHYS_MASK(0), %ecx |
| 87 | wrmsr |
| 88 | movl $MTRR_PHYS_MASK(1), %ecx |
| 89 | wrmsr |
| 90 | |
Martin Roth | c87ab01 | 2022-11-20 19:32:51 -0700 | [diff] [blame] | 91 | post_code(POST_SOC_SET_MTRR_BASE) |
Arthur Heymans | dd4d895 | 2018-06-03 12:04:26 +0200 | [diff] [blame] | 92 | /* Set Cache-as-RAM base address. */ |
| 93 | movl $(MTRR_PHYS_BASE(0)), %ecx |
Patrick Rudolph | 49da0cf | 2020-09-24 18:57:43 +0200 | [diff] [blame] | 94 | movl car_mtrr_start, %eax |
Kyösti Mälkki | dc6bb6c | 2019-11-08 00:08:55 +0200 | [diff] [blame] | 95 | orl $MTRR_TYPE_WRBACK, %eax |
Arthur Heymans | dd4d895 | 2018-06-03 12:04:26 +0200 | [diff] [blame] | 96 | xorl %edx, %edx |
| 97 | wrmsr |
| 98 | |
Martin Roth | c87ab01 | 2022-11-20 19:32:51 -0700 | [diff] [blame] | 99 | post_code(POST_SOC_SET_MTRR_MASK) |
Arthur Heymans | dd4d895 | 2018-06-03 12:04:26 +0200 | [diff] [blame] | 100 | /* Set Cache-as-RAM mask. */ |
| 101 | movl $(MTRR_PHYS_MASK(0)), %ecx |
Arthur Heymans | c2ccc97 | 2018-06-03 12:09:52 +0200 | [diff] [blame] | 102 | rdmsr |
Patrick Rudolph | 49da0cf | 2020-09-24 18:57:43 +0200 | [diff] [blame] | 103 | mov car_mtrr_mask, %eax |
Kyösti Mälkki | dc6bb6c | 2019-11-08 00:08:55 +0200 | [diff] [blame] | 104 | orl $MTRR_PHYS_MASK_VALID, %eax |
Arthur Heymans | dd4d895 | 2018-06-03 12:04:26 +0200 | [diff] [blame] | 105 | wrmsr |
| 106 | |
Arthur Heymans | 48bf712 | 2019-01-05 17:18:11 +0100 | [diff] [blame] | 107 | /* Enable cache for our code in Flash because we do XIP here */ |
| 108 | movl $MTRR_PHYS_BASE(1), %ecx |
| 109 | xorl %edx, %edx |
Patrick Rudolph | 49da0cf | 2020-09-24 18:57:43 +0200 | [diff] [blame] | 110 | mov rom_mtrr_base, %eax |
Kyösti Mälkki | dc6bb6c | 2019-11-08 00:08:55 +0200 | [diff] [blame] | 111 | orl $MTRR_TYPE_WRPROT, %eax |
Arthur Heymans | 48bf712 | 2019-01-05 17:18:11 +0100 | [diff] [blame] | 112 | wrmsr |
| 113 | |
| 114 | movl $MTRR_PHYS_MASK(1), %ecx |
| 115 | rdmsr |
Patrick Rudolph | 49da0cf | 2020-09-24 18:57:43 +0200 | [diff] [blame] | 116 | mov rom_mtrr_mask, %eax |
Kyösti Mälkki | dc6bb6c | 2019-11-08 00:08:55 +0200 | [diff] [blame] | 117 | orl $MTRR_PHYS_MASK_VALID, %eax |
Arthur Heymans | 48bf712 | 2019-01-05 17:18:11 +0100 | [diff] [blame] | 118 | wrmsr |
| 119 | |
Martin Roth | c87ab01 | 2022-11-20 19:32:51 -0700 | [diff] [blame] | 120 | post_code(POST_SOC_ENABLE_MTRRS) |
Arthur Heymans | dd4d895 | 2018-06-03 12:04:26 +0200 | [diff] [blame] | 121 | |
| 122 | /* Enable MTRR. */ |
| 123 | movl $MTRR_DEF_TYPE_MSR, %ecx |
| 124 | rdmsr |
| 125 | orl $MTRR_DEF_TYPE_EN, %eax |
| 126 | wrmsr |
| 127 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 128 | #if CONFIG(CPU_HAS_L2_ENABLE_MSR) |
Arthur Heymans | 19e7273 | 2019-01-11 23:56:51 +0100 | [diff] [blame] | 129 | /* |
| 130 | * Enable the L2 cache. Currently this assumes that this |
| 131 | * only affect socketed CPU's for which this is always valid, |
| 132 | * hence the static preprocesser. |
| 133 | */ |
| 134 | movl $BBL_CR_CTL3_MSR, %ecx |
| 135 | rdmsr |
| 136 | orl $0x100, %eax |
| 137 | wrmsr |
| 138 | #endif |
| 139 | |
Arthur Heymans | dd4d895 | 2018-06-03 12:04:26 +0200 | [diff] [blame] | 140 | /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ |
| 141 | movl %cr0, %eax |
| 142 | andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax |
| 143 | invd |
| 144 | movl %eax, %cr0 |
| 145 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 146 | #if CONFIG(MICROCODE_UPDATE_PRE_RAM) |
Arthur Heymans | 48bf712 | 2019-01-05 17:18:11 +0100 | [diff] [blame] | 147 | update_microcode: |
| 148 | /* put the return address in %esp */ |
| 149 | movl $end_microcode_update, %esp |
| 150 | jmp update_bsp_microcode |
| 151 | end_microcode_update: |
| 152 | #endif |
| 153 | /* Disable caching to change MTRR's. */ |
| 154 | movl %cr0, %eax |
| 155 | orl $CR0_CacheDisable, %eax |
| 156 | movl %eax, %cr0 |
| 157 | |
| 158 | /* Clear the mask valid to disable the MTRR */ |
| 159 | movl $MTRR_PHYS_MASK(1), %ecx |
| 160 | rdmsr |
| 161 | andl $(~MTRR_PHYS_MASK_VALID), %eax |
| 162 | wrmsr |
| 163 | |
| 164 | /* Enable cache. */ |
| 165 | movl %cr0, %eax |
| 166 | andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax |
| 167 | invd |
| 168 | movl %eax, %cr0 |
| 169 | |
Arthur Heymans | dd4d895 | 2018-06-03 12:04:26 +0200 | [diff] [blame] | 170 | /* enable the 'no eviction' mode */ |
Arthur Heymans | a28befd | 2018-12-20 13:59:34 +0100 | [diff] [blame] | 171 | movl $NoEvictMod_MSR, %ecx |
Arthur Heymans | dd4d895 | 2018-06-03 12:04:26 +0200 | [diff] [blame] | 172 | rdmsr |
Arthur Heymans | a28befd | 2018-12-20 13:59:34 +0100 | [diff] [blame] | 173 | orl $1, %eax |
| 174 | andl $~2, %eax |
Arthur Heymans | dd4d895 | 2018-06-03 12:04:26 +0200 | [diff] [blame] | 175 | wrmsr |
| 176 | |
| 177 | /* Clear the cache memory region. This will also fill up the cache. */ |
Kyösti Mälkki | dc6bb6c | 2019-11-08 00:08:55 +0200 | [diff] [blame] | 178 | cld |
Arthur Heymans | dd4d895 | 2018-06-03 12:04:26 +0200 | [diff] [blame] | 179 | xorl %eax, %eax |
Kyösti Mälkki | dc6bb6c | 2019-11-08 00:08:55 +0200 | [diff] [blame] | 180 | movl $_car_mtrr_start, %edi |
| 181 | movl $_car_mtrr_size, %ecx |
| 182 | shr $2, %ecx |
Arthur Heymans | dd4d895 | 2018-06-03 12:04:26 +0200 | [diff] [blame] | 183 | rep stosl |
| 184 | |
| 185 | /* enable the 'no eviction run' state */ |
Arthur Heymans | a28befd | 2018-12-20 13:59:34 +0100 | [diff] [blame] | 186 | movl $NoEvictMod_MSR, %ecx |
Arthur Heymans | dd4d895 | 2018-06-03 12:04:26 +0200 | [diff] [blame] | 187 | rdmsr |
Arthur Heymans | a28befd | 2018-12-20 13:59:34 +0100 | [diff] [blame] | 188 | orl $3, %eax |
Arthur Heymans | dd4d895 | 2018-06-03 12:04:26 +0200 | [diff] [blame] | 189 | wrmsr |
| 190 | |
Martin Roth | c87ab01 | 2022-11-20 19:32:51 -0700 | [diff] [blame] | 191 | post_code(POST_SOC_DISABLE_CACHE) |
Arthur Heymans | dd4d895 | 2018-06-03 12:04:26 +0200 | [diff] [blame] | 192 | /* Enable Cache-as-RAM mode by disabling cache. */ |
| 193 | movl %cr0, %eax |
| 194 | orl $CR0_CacheDisable, %eax |
| 195 | movl %eax, %cr0 |
| 196 | |
Arthur Heymans | dd4d895 | 2018-06-03 12:04:26 +0200 | [diff] [blame] | 197 | movl $MTRR_PHYS_MASK(1), %ecx |
Arthur Heymans | c2ccc97 | 2018-06-03 12:09:52 +0200 | [diff] [blame] | 198 | rdmsr |
Arthur Heymans | 48bf712 | 2019-01-05 17:18:11 +0100 | [diff] [blame] | 199 | orl $MTRR_PHYS_MASK_VALID, %eax |
Arthur Heymans | dd4d895 | 2018-06-03 12:04:26 +0200 | [diff] [blame] | 200 | wrmsr |
| 201 | |
Martin Roth | c87ab01 | 2022-11-20 19:32:51 -0700 | [diff] [blame] | 202 | post_code(POST_SOC_ENABLE_CACHE) |
Arthur Heymans | dd4d895 | 2018-06-03 12:04:26 +0200 | [diff] [blame] | 203 | /* Enable cache. */ |
| 204 | movl %cr0, %eax |
| 205 | andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax |
| 206 | movl %eax, %cr0 |
| 207 | |
| 208 | /* Setup the stack. */ |
Arthur Heymans | df9cdcf | 2019-11-09 06:50:20 +0100 | [diff] [blame] | 209 | mov $_ecar_stack, %esp |
Arthur Heymans | dd4d895 | 2018-06-03 12:04:26 +0200 | [diff] [blame] | 210 | |
Kyösti Mälkki | c641f7e | 2018-12-28 16:54:54 +0200 | [diff] [blame] | 211 | /* Need to align stack to 16 bytes at call instruction. Account for |
| 212 | the pushes below. */ |
Arthur Heymans | 348b79f | 2018-06-03 17:14:19 +0200 | [diff] [blame] | 213 | andl $0xfffffff0, %esp |
Arthur Heymans | 348b79f | 2018-06-03 17:14:19 +0200 | [diff] [blame] | 214 | |
Patrick Rudolph | 49da0cf | 2020-09-24 18:57:43 +0200 | [diff] [blame] | 215 | #if ENV_X86_64 |
| 216 | |
| 217 | #include <cpu/x86/64bit/entry64.inc> |
| 218 | |
| 219 | movd %mm2, %rdi |
| 220 | shlq $32, %rdi |
| 221 | movd %mm1, %rsi |
| 222 | or %rsi, %rdi |
| 223 | movd %mm0, %rsi |
| 224 | |
| 225 | #else |
| 226 | subl $4, %esp |
Kyösti Mälkki | c641f7e | 2018-12-28 16:54:54 +0200 | [diff] [blame] | 227 | /* push TSC and BIST to stack */ |
| 228 | movd %mm0, %eax |
Elyes HAOUAS | 87930b3 | 2019-01-16 12:41:57 +0100 | [diff] [blame] | 229 | pushl %eax /* BIST */ |
Kyösti Mälkki | c641f7e | 2018-12-28 16:54:54 +0200 | [diff] [blame] | 230 | movd %mm2, %eax |
| 231 | pushl %eax /* tsc[63:32] */ |
| 232 | movd %mm1, %eax |
Elyes HAOUAS | 87930b3 | 2019-01-16 12:41:57 +0100 | [diff] [blame] | 233 | pushl %eax /* tsc[31:0] */ |
Patrick Rudolph | 49da0cf | 2020-09-24 18:57:43 +0200 | [diff] [blame] | 234 | #endif |
Arthur Heymans | dd4d895 | 2018-06-03 12:04:26 +0200 | [diff] [blame] | 235 | |
Kyösti Mälkki | c641f7e | 2018-12-28 16:54:54 +0200 | [diff] [blame] | 236 | before_c_entry: |
Martin Roth | c87ab01 | 2022-11-20 19:32:51 -0700 | [diff] [blame] | 237 | post_code(POST_BOOTBLOCK_BEFORE_C_ENTRY) |
Kyösti Mälkki | c641f7e | 2018-12-28 16:54:54 +0200 | [diff] [blame] | 238 | call bootblock_c_entry_bist |
Arthur Heymans | dd4d895 | 2018-06-03 12:04:26 +0200 | [diff] [blame] | 239 | |
| 240 | /* Should never see this postcode */ |
lilacious | 40cb3fe | 2023-06-21 23:24:14 +0200 | [diff] [blame^] | 241 | post_code(POSTCODE_DEAD_CODE) |
Arthur Heymans | dd4d895 | 2018-06-03 12:04:26 +0200 | [diff] [blame] | 242 | |
| 243 | |
| 244 | .Lhlt: |
| 245 | hlt |
| 246 | jmp .Lhlt |
| 247 | |
Arthur Heymans | c2ccc97 | 2018-06-03 12:09:52 +0200 | [diff] [blame] | 248 | fixed_mtrr_list: |
| 249 | .word MTRR_FIX_64K_00000 |
| 250 | .word MTRR_FIX_16K_80000 |
| 251 | .word MTRR_FIX_16K_A0000 |
| 252 | .word MTRR_FIX_4K_C0000 |
| 253 | .word MTRR_FIX_4K_C8000 |
| 254 | .word MTRR_FIX_4K_D0000 |
| 255 | .word MTRR_FIX_4K_D8000 |
| 256 | .word MTRR_FIX_4K_E0000 |
| 257 | .word MTRR_FIX_4K_E8000 |
| 258 | .word MTRR_FIX_4K_F0000 |
| 259 | .word MTRR_FIX_4K_F8000 |
Arthur Heymans | 2834d98 | 2022-11-08 15:06:42 +0100 | [diff] [blame] | 260 | fixed_mtrr_list_end: |
Arthur Heymans | dd4d895 | 2018-06-03 12:04:26 +0200 | [diff] [blame] | 261 | |
| 262 | _cache_as_ram_setup_end: |