| commit | dd4d8951368029634f53e44e1a222417b72036c0 | [log] [tgz] |
|---|---|---|
| author | Arthur Heymans <arthur@aheymans.xyz> | Sun Jun 03 12:04:26 2018 +0200 |
| committer | Arthur Heymans <arthur@aheymans.xyz> | Tue Jun 05 07:49:41 2018 +0000 |
| tree | 145e103037040f09438d5e41895ab0c6e51db4fe | |
| parent | 3a4edb6ea815fa24f02daeae9b80e6bde0871a9e [diff] |
cpu/intel/car/non-evict: Prepare for some POSTCAR_STAGE support Prepare a common cache as ram for CPU's featuring a Non eviction mode MSR. Change-Id: I7fa3853498856050855b3b97546f4d31f66d12f7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/26789 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>