Arthur Heymans | dd4d895 | 2018-06-03 12:04:26 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com> |
| 5 | * Copyright (C) 2007-2008 coresystems GmbH |
Arthur Heymans | c2ccc97 | 2018-06-03 12:09:52 +0200 | [diff] [blame] | 6 | * Copyright (C) 2012 Kyösti Mälkki <kyosti.malkki@gmail.com> |
Arthur Heymans | dd4d895 | 2018-06-03 12:04:26 +0200 | [diff] [blame] | 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; version 2 of the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | */ |
| 17 | |
| 18 | #include <cpu/x86/mtrr.h> |
| 19 | #include <cpu/x86/cache.h> |
| 20 | #include <cpu/x86/post_code.h> |
| 21 | |
| 22 | #define CACHE_AS_RAM_SIZE (CONFIG_DCACHE_RAM_SIZE \ |
| 23 | + CONFIG_DCACHE_RAM_MRC_VAR_SIZE) |
| 24 | #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE |
| 25 | |
Arthur Heymans | dd4d895 | 2018-06-03 12:04:26 +0200 | [diff] [blame] | 26 | #define NoEvictMod_MSR 0x2e0 |
Arthur Heymans | 19e7273 | 2019-01-11 23:56:51 +0100 | [diff] [blame] | 27 | #define BBL_CR_CTL3_MSR 0x11e |
Arthur Heymans | dd4d895 | 2018-06-03 12:04:26 +0200 | [diff] [blame] | 28 | |
Kyösti Mälkki | c641f7e | 2018-12-28 16:54:54 +0200 | [diff] [blame] | 29 | .global bootblock_pre_c_entry |
| 30 | |
Arthur Heymans | dd4d895 | 2018-06-03 12:04:26 +0200 | [diff] [blame] | 31 | .code32 |
| 32 | _cache_as_ram_setup: |
| 33 | |
Kyösti Mälkki | c641f7e | 2018-12-28 16:54:54 +0200 | [diff] [blame] | 34 | bootblock_pre_c_entry: |
Arthur Heymans | dd4d895 | 2018-06-03 12:04:26 +0200 | [diff] [blame] | 35 | |
| 36 | cache_as_ram: |
| 37 | post_code(0x20) |
| 38 | |
| 39 | /* Send INIT IPI to all excluding ourself. */ |
| 40 | movl $0x000C4500, %eax |
| 41 | movl $0xFEE00300, %esi |
| 42 | movl %eax, (%esi) |
| 43 | |
| 44 | /* All CPUs need to be in Wait for SIPI state */ |
| 45 | wait_for_sipi: |
| 46 | movl (%esi), %eax |
| 47 | bt $12, %eax |
| 48 | jc wait_for_sipi |
| 49 | |
| 50 | post_code(0x21) |
| 51 | /* Clean-up MTRR_DEF_TYPE_MSR. */ |
| 52 | movl $MTRR_DEF_TYPE_MSR, %ecx |
| 53 | xorl %eax, %eax |
| 54 | xorl %edx, %edx |
| 55 | wrmsr |
| 56 | |
| 57 | post_code(0x22) |
Arthur Heymans | c2ccc97 | 2018-06-03 12:09:52 +0200 | [diff] [blame] | 58 | /* Clear/disable fixed MTRRs */ |
| 59 | mov $fixed_mtrr_list_size, %ebx |
| 60 | xor %eax, %eax |
| 61 | xor %edx, %edx |
| 62 | |
| 63 | clear_fixed_mtrr: |
| 64 | add $-2, %ebx |
| 65 | movzwl fixed_mtrr_list(%ebx), %ecx |
Arthur Heymans | dd4d895 | 2018-06-03 12:04:26 +0200 | [diff] [blame] | 66 | wrmsr |
Arthur Heymans | c2ccc97 | 2018-06-03 12:09:52 +0200 | [diff] [blame] | 67 | jnz clear_fixed_mtrr |
Arthur Heymans | dd4d895 | 2018-06-03 12:04:26 +0200 | [diff] [blame] | 68 | |
| 69 | /* Zero out all variable range MTRRs. */ |
| 70 | movl $MTRR_CAP_MSR, %ecx |
| 71 | rdmsr |
| 72 | andl $0xff, %eax |
| 73 | shl $1, %eax |
| 74 | movl %eax, %edi |
| 75 | movl $0x200, %ecx |
| 76 | xorl %eax, %eax |
| 77 | xorl %edx, %edx |
| 78 | clear_var_mtrrs: |
| 79 | wrmsr |
| 80 | add $1, %ecx |
| 81 | dec %edi |
| 82 | jnz clear_var_mtrrs |
| 83 | |
Arthur Heymans | c2ccc97 | 2018-06-03 12:09:52 +0200 | [diff] [blame] | 84 | /* Determine CPU_ADDR_BITS and load PHYSMASK high word to %edx. */ |
| 85 | movl $0x80000008, %eax |
| 86 | cpuid |
| 87 | movb %al, %cl |
| 88 | sub $32, %cl |
| 89 | movl $1, %edx |
| 90 | shl %cl, %edx |
| 91 | subl $1, %edx |
| 92 | |
| 93 | /* Preload high word of address mask (in %edx) for Variable |
| 94 | * MTRRs 0 and 1. |
| 95 | */ |
| 96 | addrsize_set_high: |
| 97 | xorl %eax, %eax |
| 98 | movl $MTRR_PHYS_MASK(0), %ecx |
| 99 | wrmsr |
| 100 | movl $MTRR_PHYS_MASK(1), %ecx |
| 101 | wrmsr |
| 102 | |
| 103 | |
Arthur Heymans | dd4d895 | 2018-06-03 12:04:26 +0200 | [diff] [blame] | 104 | post_code(0x23) |
| 105 | /* Set Cache-as-RAM base address. */ |
| 106 | movl $(MTRR_PHYS_BASE(0)), %ecx |
| 107 | movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax |
| 108 | xorl %edx, %edx |
| 109 | wrmsr |
| 110 | |
| 111 | post_code(0x24) |
| 112 | /* Set Cache-as-RAM mask. */ |
| 113 | movl $(MTRR_PHYS_MASK(0)), %ecx |
Arthur Heymans | c2ccc97 | 2018-06-03 12:09:52 +0200 | [diff] [blame] | 114 | rdmsr |
Arthur Heymans | dd4d895 | 2018-06-03 12:04:26 +0200 | [diff] [blame] | 115 | movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax |
Arthur Heymans | dd4d895 | 2018-06-03 12:04:26 +0200 | [diff] [blame] | 116 | wrmsr |
| 117 | |
Arthur Heymans | 48bf712 | 2019-01-05 17:18:11 +0100 | [diff] [blame] | 118 | /* Enable cache for our code in Flash because we do XIP here */ |
| 119 | movl $MTRR_PHYS_BASE(1), %ecx |
| 120 | xorl %edx, %edx |
Arthur Heymans | eeedf83 | 2019-02-08 16:27:35 +0100 | [diff] [blame] | 121 | movl $(CACHE_ROM_BASE | MTRR_TYPE_WRPROT), %eax |
Arthur Heymans | 48bf712 | 2019-01-05 17:18:11 +0100 | [diff] [blame] | 122 | wrmsr |
| 123 | |
| 124 | movl $MTRR_PHYS_MASK(1), %ecx |
| 125 | rdmsr |
| 126 | movl $(~(CACHE_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax |
| 127 | wrmsr |
| 128 | |
Arthur Heymans | dd4d895 | 2018-06-03 12:04:26 +0200 | [diff] [blame] | 129 | post_code(0x25) |
| 130 | |
| 131 | /* Enable MTRR. */ |
| 132 | movl $MTRR_DEF_TYPE_MSR, %ecx |
| 133 | rdmsr |
| 134 | orl $MTRR_DEF_TYPE_EN, %eax |
| 135 | wrmsr |
| 136 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame^] | 137 | #if CONFIG(CPU_HAS_L2_ENABLE_MSR) |
Arthur Heymans | 19e7273 | 2019-01-11 23:56:51 +0100 | [diff] [blame] | 138 | /* |
| 139 | * Enable the L2 cache. Currently this assumes that this |
| 140 | * only affect socketed CPU's for which this is always valid, |
| 141 | * hence the static preprocesser. |
| 142 | */ |
| 143 | movl $BBL_CR_CTL3_MSR, %ecx |
| 144 | rdmsr |
| 145 | orl $0x100, %eax |
| 146 | wrmsr |
| 147 | #endif |
| 148 | |
Arthur Heymans | dd4d895 | 2018-06-03 12:04:26 +0200 | [diff] [blame] | 149 | /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ |
| 150 | movl %cr0, %eax |
| 151 | andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax |
| 152 | invd |
| 153 | movl %eax, %cr0 |
| 154 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame^] | 155 | #if CONFIG(MICROCODE_UPDATE_PRE_RAM) |
Arthur Heymans | 48bf712 | 2019-01-05 17:18:11 +0100 | [diff] [blame] | 156 | update_microcode: |
| 157 | /* put the return address in %esp */ |
| 158 | movl $end_microcode_update, %esp |
| 159 | jmp update_bsp_microcode |
| 160 | end_microcode_update: |
| 161 | #endif |
| 162 | /* Disable caching to change MTRR's. */ |
| 163 | movl %cr0, %eax |
| 164 | orl $CR0_CacheDisable, %eax |
| 165 | movl %eax, %cr0 |
| 166 | |
| 167 | /* Clear the mask valid to disable the MTRR */ |
| 168 | movl $MTRR_PHYS_MASK(1), %ecx |
| 169 | rdmsr |
| 170 | andl $(~MTRR_PHYS_MASK_VALID), %eax |
| 171 | wrmsr |
| 172 | |
| 173 | /* Enable cache. */ |
| 174 | movl %cr0, %eax |
| 175 | andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax |
| 176 | invd |
| 177 | movl %eax, %cr0 |
| 178 | |
Arthur Heymans | dd4d895 | 2018-06-03 12:04:26 +0200 | [diff] [blame] | 179 | /* enable the 'no eviction' mode */ |
Arthur Heymans | a28befd | 2018-12-20 13:59:34 +0100 | [diff] [blame] | 180 | movl $NoEvictMod_MSR, %ecx |
Arthur Heymans | dd4d895 | 2018-06-03 12:04:26 +0200 | [diff] [blame] | 181 | rdmsr |
Arthur Heymans | a28befd | 2018-12-20 13:59:34 +0100 | [diff] [blame] | 182 | orl $1, %eax |
| 183 | andl $~2, %eax |
Arthur Heymans | dd4d895 | 2018-06-03 12:04:26 +0200 | [diff] [blame] | 184 | wrmsr |
| 185 | |
| 186 | /* Clear the cache memory region. This will also fill up the cache. */ |
| 187 | movl $CACHE_AS_RAM_BASE, %esi |
| 188 | movl %esi, %edi |
| 189 | movl $(CACHE_AS_RAM_SIZE >> 2), %ecx |
Arthur Heymans | dd4d895 | 2018-06-03 12:04:26 +0200 | [diff] [blame] | 190 | xorl %eax, %eax |
| 191 | rep stosl |
| 192 | |
| 193 | /* enable the 'no eviction run' state */ |
Arthur Heymans | a28befd | 2018-12-20 13:59:34 +0100 | [diff] [blame] | 194 | movl $NoEvictMod_MSR, %ecx |
Arthur Heymans | dd4d895 | 2018-06-03 12:04:26 +0200 | [diff] [blame] | 195 | rdmsr |
Arthur Heymans | a28befd | 2018-12-20 13:59:34 +0100 | [diff] [blame] | 196 | orl $3, %eax |
Arthur Heymans | dd4d895 | 2018-06-03 12:04:26 +0200 | [diff] [blame] | 197 | wrmsr |
| 198 | |
| 199 | post_code(0x26) |
| 200 | /* Enable Cache-as-RAM mode by disabling cache. */ |
| 201 | movl %cr0, %eax |
| 202 | orl $CR0_CacheDisable, %eax |
| 203 | movl %eax, %cr0 |
| 204 | |
Arthur Heymans | dd4d895 | 2018-06-03 12:04:26 +0200 | [diff] [blame] | 205 | movl $MTRR_PHYS_MASK(1), %ecx |
Arthur Heymans | c2ccc97 | 2018-06-03 12:09:52 +0200 | [diff] [blame] | 206 | rdmsr |
Arthur Heymans | 48bf712 | 2019-01-05 17:18:11 +0100 | [diff] [blame] | 207 | orl $MTRR_PHYS_MASK_VALID, %eax |
Arthur Heymans | dd4d895 | 2018-06-03 12:04:26 +0200 | [diff] [blame] | 208 | wrmsr |
| 209 | |
| 210 | post_code(0x28) |
| 211 | /* Enable cache. */ |
| 212 | movl %cr0, %eax |
| 213 | andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax |
| 214 | movl %eax, %cr0 |
| 215 | |
| 216 | /* Setup the stack. */ |
Kyösti Mälkki | c641f7e | 2018-12-28 16:54:54 +0200 | [diff] [blame] | 217 | mov $_car_stack_end, %esp |
Arthur Heymans | dd4d895 | 2018-06-03 12:04:26 +0200 | [diff] [blame] | 218 | |
Kyösti Mälkki | c641f7e | 2018-12-28 16:54:54 +0200 | [diff] [blame] | 219 | /* Need to align stack to 16 bytes at call instruction. Account for |
| 220 | the pushes below. */ |
Arthur Heymans | 348b79f | 2018-06-03 17:14:19 +0200 | [diff] [blame] | 221 | andl $0xfffffff0, %esp |
Kyösti Mälkki | c641f7e | 2018-12-28 16:54:54 +0200 | [diff] [blame] | 222 | subl $4, %esp |
Arthur Heymans | 348b79f | 2018-06-03 17:14:19 +0200 | [diff] [blame] | 223 | |
Kyösti Mälkki | c641f7e | 2018-12-28 16:54:54 +0200 | [diff] [blame] | 224 | /* push TSC and BIST to stack */ |
| 225 | movd %mm0, %eax |
Elyes HAOUAS | 87930b3 | 2019-01-16 12:41:57 +0100 | [diff] [blame] | 226 | pushl %eax /* BIST */ |
Kyösti Mälkki | c641f7e | 2018-12-28 16:54:54 +0200 | [diff] [blame] | 227 | movd %mm2, %eax |
| 228 | pushl %eax /* tsc[63:32] */ |
| 229 | movd %mm1, %eax |
Elyes HAOUAS | 87930b3 | 2019-01-16 12:41:57 +0100 | [diff] [blame] | 230 | pushl %eax /* tsc[31:0] */ |
Arthur Heymans | dd4d895 | 2018-06-03 12:04:26 +0200 | [diff] [blame] | 231 | |
Kyösti Mälkki | c641f7e | 2018-12-28 16:54:54 +0200 | [diff] [blame] | 232 | before_c_entry: |
Arthur Heymans | dd4d895 | 2018-06-03 12:04:26 +0200 | [diff] [blame] | 233 | post_code(0x29) |
Kyösti Mälkki | c641f7e | 2018-12-28 16:54:54 +0200 | [diff] [blame] | 234 | call bootblock_c_entry_bist |
Arthur Heymans | dd4d895 | 2018-06-03 12:04:26 +0200 | [diff] [blame] | 235 | |
| 236 | /* Should never see this postcode */ |
| 237 | post_code(POST_DEAD_CODE) |
| 238 | |
| 239 | |
| 240 | .Lhlt: |
| 241 | hlt |
| 242 | jmp .Lhlt |
| 243 | |
Arthur Heymans | c2ccc97 | 2018-06-03 12:09:52 +0200 | [diff] [blame] | 244 | fixed_mtrr_list: |
| 245 | .word MTRR_FIX_64K_00000 |
| 246 | .word MTRR_FIX_16K_80000 |
| 247 | .word MTRR_FIX_16K_A0000 |
| 248 | .word MTRR_FIX_4K_C0000 |
| 249 | .word MTRR_FIX_4K_C8000 |
| 250 | .word MTRR_FIX_4K_D0000 |
| 251 | .word MTRR_FIX_4K_D8000 |
| 252 | .word MTRR_FIX_4K_E0000 |
| 253 | .word MTRR_FIX_4K_E8000 |
| 254 | .word MTRR_FIX_4K_F0000 |
| 255 | .word MTRR_FIX_4K_F8000 |
| 256 | fixed_mtrr_list_size = . - fixed_mtrr_list |
Arthur Heymans | dd4d895 | 2018-06-03 12:04:26 +0200 | [diff] [blame] | 257 | |
| 258 | _cache_as_ram_setup_end: |