Gitiles
Code Review Sign In
review.coreboot.org / coreboot / 3f4af0da938e0d9f4d80e77a3d8abd1f6400e57e / . / src / soc / intel / common / block / pcie / pcie.c
blob: cc20a48d225712bc4a02f611f7052e55400680fe [file] [log] [blame]
Aamir Bohra2d689f92017-05-11 20:27:27 +0530[diff] [blame]1/*
2 * This file is part of the coreboot project.
3 *
praveen hodagatta praneshe26c4a42018-09-20 03:49:45 +0800[diff] [blame]4 * Copyright (C) 2017-2018 Intel Corporation.
Aamir Bohra2d689f92017-05-11 20:27:27 +0530[diff] [blame]5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <console/console.h>
17#include <device/pci.h>
18#include <device/pciexp.h>
19#include <device/pci_def.h>
20#include <device/pci_ids.h>
Patrick Rudolphe56189c2018-04-18 10:11:59 +0200[diff] [blame]21#include <device/pci_ops.h>
Aamir Bohra2d689f92017-05-11 20:27:27 +0530[diff] [blame]22
23#define CACHE_LINE_SIZE 0x10
Aamir Bohra2d689f92017-05-11 20:27:27 +0530[diff] [blame]24
25static void pch_pcie_init(struct device *dev)
26{
27 u16 reg16;
28
29 printk(BIOS_DEBUG, "Initializing PCH PCIe bridge.\n");
30
31 /* Enable SERR */
32 pci_or_config32(dev, PCI_COMMAND, PCI_COMMAND_SERR);
33
34 /* Enable Bus Master */
35 pci_or_config32(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
36
37 /* Set Cache Line Size to 0x10 */
38 pci_write_config8(dev, PCI_CACHE_LINE_SIZE, CACHE_LINE_SIZE);
39
40 /* disable parity error response, enable ISA */
Kyösti Mälkkidf128a52019-09-21 18:35:37 +0300[diff] [blame]41 pci_update_config16(dev, PCI_BRIDGE_CONTROL,
42 ~PCI_BRIDGE_CTL_PARITY, PCI_BRIDGE_CTL_NO_ISA);
Aamir Bohra2d689f92017-05-11 20:27:27 +0530[diff] [blame]43
Julius Wernercd49cce2019-03-05 16:53:33 -0800[diff] [blame]44 if (CONFIG(PCIE_DEBUG_INFO)) {
Aamir Bohra2d689f92017-05-11 20:27:27 +0530[diff] [blame]45 printk(BIOS_SPEW, " MBL = 0x%08x\n",
46 pci_read_config32(dev, PCI_MEMORY_BASE));
47 printk(BIOS_SPEW, " PMBL = 0x%08x\n",
48 pci_read_config32(dev, PCI_PREF_MEMORY_BASE));
49 printk(BIOS_SPEW, " PMBU32 = 0x%08x\n",
50 pci_read_config32(dev, PCI_PREF_BASE_UPPER32));
51 printk(BIOS_SPEW, " PMLU32 = 0x%08x\n",
52 pci_read_config32(dev, PCI_PREF_LIMIT_UPPER32));
53 }
54
55 /* Clear errors in status registers */
56 reg16 = pci_read_config16(dev, PCI_STATUS);
57 pci_write_config16(dev, PCI_STATUS, reg16);
58 reg16 = pci_read_config16(dev, PCI_SEC_STATUS);
59 pci_write_config16(dev, PCI_SEC_STATUS, reg16);
60}
61
Elyes HAOUAS4a131262018-09-16 17:35:48 +0200[diff] [blame]62static void pcie_set_L1_ss_max_latency(struct device *dev, unsigned int offset)
Aamir Bohra2d689f92017-05-11 20:27:27 +0530[diff] [blame]63{
64 /* Set max snoop and non-snoop latency for the SOC */
65 pci_write_config32(dev, offset,
Subrata Baniked6996f2019-03-25 21:49:39 +0530[diff] [blame]66 PCIE_LTR_MAX_NO_SNOOP_LATENCY_3146US << 16 |
67 PCIE_LTR_MAX_SNOOP_LATENCY_3146US);
Aamir Bohra2d689f92017-05-11 20:27:27 +0530[diff] [blame]68}
69
70static struct pci_operations pcie_ops = {
71 .set_L1_ss_latency = pcie_set_L1_ss_max_latency,
Subrata Banik15ccbf02019-03-20 15:09:44 +0530[diff] [blame]72 .set_subsystem = pci_dev_set_subsystem,
Aamir Bohra2d689f92017-05-11 20:27:27 +0530[diff] [blame]73};
74
75static struct device_operations device_ops = {
76 .read_resources = pci_bus_read_resources,
77 .set_resources = pci_dev_set_resources,
78 .enable_resources = pci_bus_enable_resources,
79 .init = pch_pcie_init,
80 .scan_bus = pciexp_scan_bridge,
81 .ops_pci = &pcie_ops,
82};
83
84static const unsigned short pcie_device_ids[] = {
85 PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP1,
86 PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP2,
87 PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP3,
88 PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP4,
89 PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP5,
90 PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP6,
91 PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP7,
92 PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP8,
93 PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP9,
94 PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP10,
95 PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP11,
96 PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP12,
97 PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP1,
98 PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP2,
99 PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP3,
100 PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP4,
101 PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP5,
102 PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP6,
103 PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP7,
104 PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP8,
105 PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP9,
106 PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP10,
107 PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP11,
108 PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP12,
109 PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP13,
110 PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP14,
111 PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP15,
112 PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP16,
113 PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP17,
114 PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP18,
115 PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP19,
116 PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP20,
Maxim Polyakov571d07d2019-08-22 13:11:32 +0300[diff] [blame]117 PCI_DEVICE_ID_INTEL_LWB_PCIE_RP1,
118 PCI_DEVICE_ID_INTEL_LWB_PCIE_RP2,
119 PCI_DEVICE_ID_INTEL_LWB_PCIE_RP3,
120 PCI_DEVICE_ID_INTEL_LWB_PCIE_RP4,
121 PCI_DEVICE_ID_INTEL_LWB_PCIE_RP5,
122 PCI_DEVICE_ID_INTEL_LWB_PCIE_RP6,
123 PCI_DEVICE_ID_INTEL_LWB_PCIE_RP7,
124 PCI_DEVICE_ID_INTEL_LWB_PCIE_RP8,
125 PCI_DEVICE_ID_INTEL_LWB_PCIE_RP9,
126 PCI_DEVICE_ID_INTEL_LWB_PCIE_RP10,
127 PCI_DEVICE_ID_INTEL_LWB_PCIE_RP11,
128 PCI_DEVICE_ID_INTEL_LWB_PCIE_RP12,
129 PCI_DEVICE_ID_INTEL_LWB_PCIE_RP13,
130 PCI_DEVICE_ID_INTEL_LWB_PCIE_RP14,
131 PCI_DEVICE_ID_INTEL_LWB_PCIE_RP15,
132 PCI_DEVICE_ID_INTEL_LWB_PCIE_RP16,
133 PCI_DEVICE_ID_INTEL_LWB_PCIE_RP17,
134 PCI_DEVICE_ID_INTEL_LWB_PCIE_RP18,
135 PCI_DEVICE_ID_INTEL_LWB_PCIE_RP19,
136 PCI_DEVICE_ID_INTEL_LWB_PCIE_RP20,
137 PCI_DEVICE_ID_INTEL_LWB_PCIE_RP1_SUPER,
138 PCI_DEVICE_ID_INTEL_LWB_PCIE_RP2_SUPER,
139 PCI_DEVICE_ID_INTEL_LWB_PCIE_RP3_SUPER,
140 PCI_DEVICE_ID_INTEL_LWB_PCIE_RP4_SUPER,
141 PCI_DEVICE_ID_INTEL_LWB_PCIE_RP5_SUPER,
142 PCI_DEVICE_ID_INTEL_LWB_PCIE_RP6_SUPER,
143 PCI_DEVICE_ID_INTEL_LWB_PCIE_RP7_SUPER,
144 PCI_DEVICE_ID_INTEL_LWB_PCIE_RP8_SUPER,
145 PCI_DEVICE_ID_INTEL_LWB_PCIE_RP9_SUPER,
146 PCI_DEVICE_ID_INTEL_LWB_PCIE_RP10_SUPER,
147 PCI_DEVICE_ID_INTEL_LWB_PCIE_RP11_SUPER,
148 PCI_DEVICE_ID_INTEL_LWB_PCIE_RP12_SUPER,
149 PCI_DEVICE_ID_INTEL_LWB_PCIE_RP13_SUPER,
150 PCI_DEVICE_ID_INTEL_LWB_PCIE_RP14_SUPER,
151 PCI_DEVICE_ID_INTEL_LWB_PCIE_RP15_SUPER,
152 PCI_DEVICE_ID_INTEL_LWB_PCIE_RP16_SUPER,
153 PCI_DEVICE_ID_INTEL_LWB_PCIE_RP17_SUPER,
154 PCI_DEVICE_ID_INTEL_LWB_PCIE_RP18_SUPER,
155 PCI_DEVICE_ID_INTEL_LWB_PCIE_RP19_SUPER,
156 PCI_DEVICE_ID_INTEL_LWB_PCIE_RP20_SUPER,
Aamir Bohra2d689f92017-05-11 20:27:27 +0530[diff] [blame]157 PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP1,
158 PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP2,
159 PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP3,
160 PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP4,
161 PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP5,
162 PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP6,
163 PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP7,
164 PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP8,
165 PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP9,
166 PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP10,
167 PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP11,
168 PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP12,
169 PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP13,
170 PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP14,
171 PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP15,
172 PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP16,
173 PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP17,
174 PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP18,
175 PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP19,
176 PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP20,
177 PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP21,
178 PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP22,
179 PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP23,
180 PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP24,
Lijian Zhaobbedef92017-07-29 16:38:38 -0700[diff] [blame]181 PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP1,
182 PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP2,
183 PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP3,
184 PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP4,
185 PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP5,
186 PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP6,
187 PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP7,
188 PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP8,
189 PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP9,
190 PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP10,
191 PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP11,
192 PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP12,
193 PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP13,
194 PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP14,
195 PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP15,
196 PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP16,
praveen hodagatta praneshe26c4a42018-09-20 03:49:45 +0800[diff] [blame]197 PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP1,
198 PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP2,
199 PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP3,
200 PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP4,
201 PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP5,
202 PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP6,
203 PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP7,
204 PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP8,
205 PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP9,
206 PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP10,
207 PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP11,
208 PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP12,
209 PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP13,
210 PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP14,
211 PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP15,
212 PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP16,
213 PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP17,
214 PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP18,
215 PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP19,
216 PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP20,
217 PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP21,
218 PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP22,
219 PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP23,
220 PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP24,
Aamir Bohra9eac0392018-06-30 12:07:04 +0530[diff] [blame]221 PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP1,
222 PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP2,
223 PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP3,
224 PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP4,
225 PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP5,
226 PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP6,
227 PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP7,
228 PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP8,
229 PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP9,
230 PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP10,
231 PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP11,
232 PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP12,
233 PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP13,
234 PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP14,
235 PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP15,
236 PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP16,
Ronak Kanabarda7ffb482019-02-05 01:51:13 +0530[diff] [blame]237 PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP1,
238 PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP2,
239 PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP3,
240 PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP4,
241 PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP5,
242 PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP6,
243 PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP7,
244 PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP8,
245 PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP9,
246 PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP10,
247 PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP11,
248 PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP12,
249 PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP13,
250 PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP14,
251 PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP15,
252 PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP16,
Gaggery Tsai12a651c2019-12-05 11:23:20 -0800[diff] [blame]253 PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP1,
254 PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP2,
255 PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP3,
256 PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP4,
257 PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP5,
258 PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP6,
259 PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP7,
260 PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP8,
261 PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP9,
262 PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP10,
263 PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP11,
264 PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP12,
265 PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP13,
266 PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP14,
267 PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP15,
268 PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP16,
269 PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP17,
270 PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP18,
271 PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP19,
272 PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP20,
273 PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP21,
274 PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP22,
275 PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP23,
276 PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP24,
Ravi Sarawadi6b5bf402019-10-21 22:25:04 -0700[diff] [blame]277 PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP1,
278 PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP2,
279 PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP3,
280 PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP4,
281 PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP5,
282 PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP6,
283 PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP7,
284 PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP8,
285 PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP9,
286 PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP10,
287 PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP11,
288 PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP12,
289 PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP13,
290 PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP14,
291 PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP15,
292 PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP16,
Tan, Lean Sheng26136092020-01-20 19:13:56 -0800[diff] [blame]293 PCI_DEVICE_ID_INTEL_MCC_PCIE_RP1,
294 PCI_DEVICE_ID_INTEL_MCC_PCIE_RP2,
295 PCI_DEVICE_ID_INTEL_MCC_PCIE_RP3,
296 PCI_DEVICE_ID_INTEL_MCC_PCIE_RP4,
297 PCI_DEVICE_ID_INTEL_MCC_PCIE_RP5,
298 PCI_DEVICE_ID_INTEL_MCC_PCIE_RP6,
299 PCI_DEVICE_ID_INTEL_MCC_PCIE_RP7,
Meera Ravindranath3f4af0d2020-02-12 16:01:22 +0530[diff] [blame^]300 PCI_DEVICE_ID_INTEL_JSP_PCIE_RP1,
301 PCI_DEVICE_ID_INTEL_JSP_PCIE_RP2,
302 PCI_DEVICE_ID_INTEL_JSP_PCIE_RP3,
303 PCI_DEVICE_ID_INTEL_JSP_PCIE_RP4,
304 PCI_DEVICE_ID_INTEL_JSP_PCIE_RP5,
305 PCI_DEVICE_ID_INTEL_JSP_PCIE_RP6,
306 PCI_DEVICE_ID_INTEL_JSP_PCIE_RP7,
307 PCI_DEVICE_ID_INTEL_JSP_PCIE_RP8,
Aamir Bohra2d689f92017-05-11 20:27:27 +0530[diff] [blame]308 0
309};
310
311static const struct pci_driver pch_pcie __pci_driver = {
312 .ops = &device_ops,
313 .vendor = PCI_VENDOR_ID_INTEL,
314 .devices = pcie_device_ids,
315};