commit 6b5bf407deb52a900ef0a8a0b99f853be1eb7e82
author Ravi Sarawadi <ravishankar.sarawadi@intel.com> Mon Oct 21 22:25:04 2019 -0700
committer Patrick Georgi <pgeorgi@google.com> Tue Nov 05 15:05:22 2019 +0000
tree 283c0d2d098d3439e1558729cbdb35f9721ab6e6
parent 8fc523e3137cfdde970a3c87e22b8bbc586a3f7e

soc/intel/common: Include Tigerlake device IDs

Add Tigerlake specific CPU, System Agent, PCH, IGD device IDs.

BUG=None
BRANCH=None
TEST=Build 'emerge-tglrvp coreboot'

Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Change-Id: I19047354718bdf510dffee4659d885f1313a751b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36225
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>

src/soc/intel/common/block/pcie/pcie.c

diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c
index c8ca4f4..406a227 100644
--- a/src/soc/intel/common/block/pcie/pcie.c
+++ b/src/soc/intel/common/block/pcie/pcie.c
@@ -250,6 +250,22 @@
 	PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP14,
 	PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP15,
 	PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP16,
+	PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP1,
+	PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP2,
+	PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP3,
+	PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP4,
+	PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP5,
+	PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP6,
+	PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP7,
+	PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP8,
+	PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP9,
+	PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP10,
+	PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP11,
+	PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP12,
+	PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP13,
+	PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP14,
+	PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP15,
+	PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP16,
 	0
 };