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review.coreboot.org / coreboot / 2d689f9e0d281b7ebe99340731511b51d9af21cc / . / src / soc / intel / common / block / pcie / pcie.c
blob: dfc92fed27d24af7a6873e950baeea3933817908 [file] [log] [blame]
Aamir Bohra2d689f92017-05-11 20:27:27 +0530[diff] [blame^]1/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2017 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <console/console.h>
17#include <device/pci.h>
18#include <device/pciexp.h>
19#include <device/pci_def.h>
20#include <device/pci_ids.h>
21
22#define CACHE_LINE_SIZE 0x10
23/* Latency tolerance reporting, max non-snoop latency value 3.14ms */
24#define PCIE_LTR_MAX_NO_SNOOP_LATENCY_VALUE 0x1003
25/* Latency tolerance reporting, max snoop latency value 3.14ms */
26#define PCIE_LTR_MAX_SNOOP_LATENCY_VALUE 0x1003
27
28static void pch_pcie_init(struct device *dev)
29{
30 u16 reg16;
31
32 printk(BIOS_DEBUG, "Initializing PCH PCIe bridge.\n");
33
34 /* Enable SERR */
35 pci_or_config32(dev, PCI_COMMAND, PCI_COMMAND_SERR);
36
37 /* Enable Bus Master */
38 pci_or_config32(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
39
40 /* Set Cache Line Size to 0x10 */
41 pci_write_config8(dev, PCI_CACHE_LINE_SIZE, CACHE_LINE_SIZE);
42
43 /* disable parity error response, enable ISA */
44 pci_update_config16(dev, PCI_BRIDGE_CONTROL, ~1, 1<<2);
45
46 if (IS_ENABLED(CONFIG_PCIE_DEBUG_INFO)) {
47 printk(BIOS_SPEW, " MBL = 0x%08x\n",
48 pci_read_config32(dev, PCI_MEMORY_BASE));
49 printk(BIOS_SPEW, " PMBL = 0x%08x\n",
50 pci_read_config32(dev, PCI_PREF_MEMORY_BASE));
51 printk(BIOS_SPEW, " PMBU32 = 0x%08x\n",
52 pci_read_config32(dev, PCI_PREF_BASE_UPPER32));
53 printk(BIOS_SPEW, " PMLU32 = 0x%08x\n",
54 pci_read_config32(dev, PCI_PREF_LIMIT_UPPER32));
55 }
56
57 /* Clear errors in status registers */
58 reg16 = pci_read_config16(dev, PCI_STATUS);
59 pci_write_config16(dev, PCI_STATUS, reg16);
60 reg16 = pci_read_config16(dev, PCI_SEC_STATUS);
61 pci_write_config16(dev, PCI_SEC_STATUS, reg16);
62}
63
64static void pcie_set_L1_ss_max_latency(device_t dev, unsigned int offset)
65{
66 /* Set max snoop and non-snoop latency for the SOC */
67 pci_write_config32(dev, offset,
68 PCIE_LTR_MAX_NO_SNOOP_LATENCY_VALUE << 16 |
69 PCIE_LTR_MAX_SNOOP_LATENCY_VALUE);
70}
71
72static struct pci_operations pcie_ops = {
73 .set_L1_ss_latency = pcie_set_L1_ss_max_latency,
74};
75
76static struct device_operations device_ops = {
77 .read_resources = pci_bus_read_resources,
78 .set_resources = pci_dev_set_resources,
79 .enable_resources = pci_bus_enable_resources,
80 .init = pch_pcie_init,
81 .scan_bus = pciexp_scan_bridge,
82 .ops_pci = &pcie_ops,
83};
84
85static const unsigned short pcie_device_ids[] = {
86 PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP1,
87 PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP2,
88 PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP3,
89 PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP4,
90 PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP5,
91 PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP6,
92 PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP7,
93 PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP8,
94 PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP9,
95 PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP10,
96 PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP11,
97 PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP12,
98 PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP1,
99 PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP2,
100 PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP3,
101 PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP4,
102 PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP5,
103 PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP6,
104 PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP7,
105 PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP8,
106 PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP9,
107 PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP10,
108 PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP11,
109 PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP12,
110 PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP13,
111 PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP14,
112 PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP15,
113 PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP16,
114 PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP17,
115 PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP18,
116 PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP19,
117 PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP20,
118 PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP1,
119 PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP2,
120 PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP3,
121 PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP4,
122 PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP5,
123 PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP6,
124 PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP7,
125 PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP8,
126 PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP9,
127 PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP10,
128 PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP11,
129 PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP12,
130 PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP13,
131 PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP14,
132 PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP15,
133 PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP16,
134 PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP17,
135 PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP18,
136 PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP19,
137 PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP20,
138 PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP21,
139 PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP22,
140 PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP23,
141 PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP24,
142 0
143};
144
145static const struct pci_driver pch_pcie __pci_driver = {
146 .ops = &device_ops,
147 .vendor = PCI_VENDOR_ID_INTEL,
148 .devices = pcie_device_ids,
149};