| Jonathan Zhang | 3ed903f | 2023-01-25 11:37:27 -0800 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #ifndef _SOC_CHIP_H_ |
| 4 | #define _SOC_CHIP_H_ |
| 5 | |
| 6 | #include <gpio.h> |
| 7 | #include <intelblocks/cfg.h> |
| 8 | #include <soc/acpi.h> |
| 9 | #include <soc/irq.h> |
| 10 | #include <stdint.h> |
| 11 | |
| 12 | #define MAX_PCH_PCIE_PORT 20 |
| 13 | |
| 14 | /** |
| 15 | UPD_PCH_PCIE_PORT: |
| 16 | ForceEnable - Enable/Disable PCH PCIe port |
| 17 | PortLinkSpeed - Port Link Speed. Use PCIE_LINK_SPEED to set |
| 18 | **/ |
| 19 | struct pch_pcie_port { |
| 20 | uint8_t ForceEnable; |
| 21 | uint8_t PortLinkSpeed; |
| 22 | }; |
| 23 | |
| 24 | struct soc_intel_xeon_sp_spr_config { |
| 25 | /* Common struct containing soc config data required by common code */ |
| 26 | struct soc_intel_common_config common_soc_config; |
| 27 | |
| 28 | /* Struct for configuring PCH PCIe port */ |
| 29 | struct pch_pcie_port pch_pci_port[MAX_PCH_PCIE_PORT]; |
| 30 | |
| 31 | /** |
| 32 | * Interrupt Routing configuration |
| 33 | * If bit7 is 1, the interrupt is disabled. |
| 34 | */ |
| 35 | uint8_t pirqa_routing; |
| 36 | uint8_t pirqb_routing; |
| 37 | uint8_t pirqc_routing; |
| 38 | uint8_t pirqd_routing; |
| 39 | uint8_t pirqe_routing; |
| 40 | uint8_t pirqf_routing; |
| 41 | uint8_t pirqg_routing; |
| 42 | uint8_t pirqh_routing; |
| 43 | |
| 44 | /** |
| 45 | * Device Interrupt Routing configuration |
| 46 | * Interrupt Pin x Route. |
| 47 | * 0h = PIRQA# |
| 48 | * 1h = PIRQB# |
| 49 | * 2h = PIRQC# |
| 50 | * 3h = PIRQD# |
| 51 | * 4h = PIRQE# |
| 52 | * 5h = PIRQF# |
| 53 | * 6h = PIRQG# |
| 54 | * 7h = PIRQH# |
| 55 | */ |
| 56 | uint16_t ir00_routing; |
| 57 | uint16_t ir01_routing; |
| 58 | uint16_t ir02_routing; |
| 59 | uint16_t ir03_routing; |
| 60 | uint16_t ir04_routing; |
| 61 | |
| 62 | /** |
| 63 | * Device Interrupt Polarity Control |
| 64 | * ipc0 - IRQ-00-31 - 1: Active low to IOAPIC, 0: Active high to IOAPIC |
| 65 | * ipc1 - IRQ-32-63 - 1: Active low to IOAPIC, 0: Active high to IOAPIC |
| 66 | * ipc2 - IRQ-64-95 - 1: Active low to IOAPIC, 0: Active high to IOAPIC |
| 67 | * ipc3 - IRQ-96-119 - 1: Active low to IOAPIC, 0: Active high to IOAPIC |
| 68 | */ |
| 69 | uint32_t ipc0; |
| 70 | uint32_t ipc1; |
| 71 | uint32_t ipc2; |
| 72 | uint32_t ipc3; |
| 73 | |
| 74 | uint64_t turbo_ratio_limit; |
| 75 | uint64_t turbo_ratio_limit_cores; |
| 76 | |
| 77 | uint32_t pstate_req_ratio; |
| 78 | |
| 79 | uint8_t vtd_support; |
| 80 | uint8_t x2apic; |
| 81 | |
| 82 | /* Generic IO decode ranges */ |
| 83 | uint32_t gen1_dec; |
| 84 | uint32_t gen2_dec; |
| 85 | uint32_t gen3_dec; |
| 86 | uint32_t gen4_dec; |
| 87 | |
| 88 | /* TCC activation offset */ |
| 89 | uint32_t tcc_offset; |
| 90 | |
| 91 | enum acpi_cstate_mode cstate_states; |
| 92 | }; |
| 93 | |
| 94 | typedef struct soc_intel_xeon_sp_spr_config config_t; |
| 95 | |
| 96 | #endif |