Angel Pons | ae59387 | 2020-04-04 18:50:57 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 2 | |
Furquan Shaikh | 91a7abf | 2020-04-27 18:48:48 -0700 | [diff] [blame] | 3 | #include <assert.h> |
Felix Held | 915c387 | 2023-04-11 21:21:35 +0200 | [diff] [blame] | 4 | #include <amdblocks/acpi.h> |
Michał Żygowski | f65c1e4 | 2019-12-01 18:14:39 +0100 | [diff] [blame] | 5 | #include <amdblocks/biosram.h> |
Furquan Shaikh | 91a7abf | 2020-04-27 18:48:48 -0700 | [diff] [blame] | 6 | #include <amdblocks/hda.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 7 | #include <device/pci_ops.h> |
Felix Held | 4b2464f | 2022-02-23 17:54:20 +0100 | [diff] [blame] | 8 | #include <arch/hpet.h> |
Marc Jones | d6a8200 | 2018-03-31 22:46:57 -0600 | [diff] [blame] | 9 | #include <arch/ioapic.h> |
Furquan Shaikh | 76cedd2 | 2020-05-02 10:24:23 -0700 | [diff] [blame] | 10 | #include <acpi/acpi.h> |
| 11 | #include <acpi/acpigen.h> |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 12 | #include <cbmem.h> |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 13 | #include <console/console.h> |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 14 | #include <cpu/amd/mtrr.h> |
Marshall Dawson | 154239a | 2017-11-02 09:49:30 -0600 | [diff] [blame] | 15 | #include <cpu/x86/lapic_def.h> |
Marshall Dawson | f82aa10 | 2017-09-20 18:01:41 -0600 | [diff] [blame] | 16 | #include <cpu/x86/msr.h> |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 17 | #include <device/device.h> |
| 18 | #include <device/pci.h> |
| 19 | #include <device/pci_ids.h> |
Richard Spiegel | 0ad74ac | 2017-12-08 16:53:29 -0700 | [diff] [blame] | 20 | #include <amdblocks/agesawrapper.h> |
| 21 | #include <amdblocks/agesawrapper_call.h> |
Felix Held | 604ffa6 | 2021-02-12 00:43:20 +0100 | [diff] [blame] | 22 | #include <amdblocks/ioapic.h> |
Marshall Dawson | 2942db6 | 2017-12-14 10:00:27 -0700 | [diff] [blame] | 23 | #include <agesa_headers.h> |
Marshall Dawson | 653f760 | 2018-09-04 13:25:39 -0600 | [diff] [blame] | 24 | #include <soc/cpu.h> |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 25 | #include <soc/northbridge.h> |
Marshall Dawson | 38bded0 | 2017-09-01 09:54:48 -0600 | [diff] [blame] | 26 | #include <soc/pci_devs.h> |
Marshall Dawson | 2942db6 | 2017-12-14 10:00:27 -0700 | [diff] [blame] | 27 | #include <soc/iomap.h> |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 28 | #include <stdint.h> |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 29 | #include <string.h> |
| 30 | |
Elyes HAOUAS | c338507 | 2019-03-21 15:38:06 +0100 | [diff] [blame] | 31 | #include "chip.h" |
| 32 | |
Elyes HAOUAS | 777ccd4 | 2018-05-22 10:52:05 +0200 | [diff] [blame] | 33 | static void set_io_addr_reg(struct device *dev, u32 nodeid, u32 linkn, u32 reg, |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 34 | u32 io_min, u32 io_max) |
| 35 | { |
| 36 | u32 tempreg; |
Marshall Dawson | 38bded0 | 2017-09-01 09:54:48 -0600 | [diff] [blame] | 37 | |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 38 | /* io range allocation. Limit */ |
| 39 | tempreg = (nodeid & 0xf) | ((nodeid & 0x30) << (8 - 4)) | (linkn << 4) |
| 40 | | ((io_max & 0xf0) << (12 - 4)); |
Richard Spiegel | 41baf0c | 2018-10-22 13:57:18 -0700 | [diff] [blame] | 41 | pci_write_config32(SOC_ADDR_DEV, reg + 4, tempreg); |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 42 | tempreg = 3 | ((io_min & 0xf0) << (12 - 4)); /* base: ISA and VGA ? */ |
Richard Spiegel | 41baf0c | 2018-10-22 13:57:18 -0700 | [diff] [blame] | 43 | pci_write_config32(SOC_ADDR_DEV, reg, tempreg); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 44 | } |
| 45 | |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 46 | static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, |
| 47 | u32 mmio_min, u32 mmio_max) |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 48 | { |
| 49 | u32 tempreg; |
Marshall Dawson | 38bded0 | 2017-09-01 09:54:48 -0600 | [diff] [blame] | 50 | |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 51 | /* io range allocation. Limit */ |
| 52 | tempreg = (nodeid & 0xf) | (linkn << 4) | (mmio_max & 0xffffff00); |
Felix Held | aec49ae | 2023-04-19 21:42:46 +0200 | [diff] [blame] | 53 | pci_write_config32(SOC_ADDR_DEV, reg + 4, tempreg); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 54 | tempreg = 3 | (nodeid & 0x30) | (mmio_min & 0xffffff00); |
Felix Held | aec49ae | 2023-04-19 21:42:46 +0200 | [diff] [blame] | 55 | pci_write_config32(SOC_ADDR_DEV, reg, tempreg); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 56 | } |
| 57 | |
Elyes HAOUAS | 777ccd4 | 2018-05-22 10:52:05 +0200 | [diff] [blame] | 58 | static void read_resources(struct device *dev) |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 59 | { |
Felix Held | 56b037b | 2022-03-02 22:57:01 +0100 | [diff] [blame] | 60 | unsigned int idx = 0; |
Marc Jones | d6a8200 | 2018-03-31 22:46:57 -0600 | [diff] [blame] | 61 | struct resource *res; |
| 62 | |
Felix Held | af17f0b | 2022-03-02 23:36:55 +0100 | [diff] [blame] | 63 | /* The northbridge has no PCI BARs implemented, so there's no need to call |
| 64 | pci_dev_read_resources for it */ |
| 65 | |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 66 | /* |
| 67 | * This MMCONF resource must be reserved in the PCI domain. |
| 68 | * It is not honored by the coreboot resource allocator if it is in |
| 69 | * the CPU_CLUSTER. |
| 70 | */ |
Felix Held | 56b037b | 2022-03-02 22:57:01 +0100 | [diff] [blame] | 71 | mmconf_resource(dev, idx++); |
Marc Jones | d6a8200 | 2018-03-31 22:46:57 -0600 | [diff] [blame] | 72 | |
| 73 | /* NB IOAPIC2 resource */ |
Felix Held | b1197af | 2022-03-02 23:02:31 +0100 | [diff] [blame] | 74 | res = new_resource(dev, idx++); /* IOAPIC2 */ |
Marc Jones | d6a8200 | 2018-03-31 22:46:57 -0600 | [diff] [blame] | 75 | res->base = IO_APIC2_ADDR; |
| 76 | res->size = 0x00001000; |
| 77 | res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 78 | } |
| 79 | |
Richard Spiegel | 2b7cd1d | 2018-10-22 14:39:37 -0700 | [diff] [blame] | 80 | static void set_resource(struct device *dev, struct resource *res, u32 nodeid) |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 81 | { |
| 82 | resource_t rbase, rend; |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 83 | unsigned int reg, link_num; |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 84 | char buf[50]; |
| 85 | |
| 86 | /* Make certain the resource has actually been set */ |
Richard Spiegel | 2b7cd1d | 2018-10-22 14:39:37 -0700 | [diff] [blame] | 87 | if (!(res->flags & IORESOURCE_ASSIGNED)) |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 88 | return; |
| 89 | |
| 90 | /* If I have already stored this resource don't worry about it */ |
Richard Spiegel | 2b7cd1d | 2018-10-22 14:39:37 -0700 | [diff] [blame] | 91 | if (res->flags & IORESOURCE_STORED) |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 92 | return; |
| 93 | |
| 94 | /* Only handle PCI memory and IO resources */ |
Richard Spiegel | 2b7cd1d | 2018-10-22 14:39:37 -0700 | [diff] [blame] | 95 | if (!(res->flags & (IORESOURCE_MEM | IORESOURCE_IO))) |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 96 | return; |
| 97 | |
| 98 | /* Ensure I am actually looking at a resource of function 1 */ |
Richard Spiegel | 2b7cd1d | 2018-10-22 14:39:37 -0700 | [diff] [blame] | 99 | if ((res->index & 0xffff) < 0x1000) |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 100 | return; |
| 101 | |
| 102 | /* Get the base address */ |
Richard Spiegel | 2b7cd1d | 2018-10-22 14:39:37 -0700 | [diff] [blame] | 103 | rbase = res->base; |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 104 | |
| 105 | /* Get the limit (rounded up) */ |
Richard Spiegel | 2b7cd1d | 2018-10-22 14:39:37 -0700 | [diff] [blame] | 106 | rend = resource_end(res); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 107 | |
| 108 | /* Get the register and link */ |
Richard Spiegel | 2b7cd1d | 2018-10-22 14:39:37 -0700 | [diff] [blame] | 109 | reg = res->index & 0xfff; /* 4k */ |
| 110 | link_num = IOINDEX_LINK(res->index); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 111 | |
Richard Spiegel | 2b7cd1d | 2018-10-22 14:39:37 -0700 | [diff] [blame] | 112 | if (res->flags & IORESOURCE_IO) |
Elyes Haouas | 55d0f40 | 2022-07-16 09:53:05 +0200 | [diff] [blame] | 113 | set_io_addr_reg(dev, nodeid, link_num, reg, rbase >> 8, rend >> 8); |
Richard Spiegel | 2b7cd1d | 2018-10-22 14:39:37 -0700 | [diff] [blame] | 114 | else if (res->flags & IORESOURCE_MEM) |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 115 | set_mmio_addr_reg(nodeid, link_num, reg, |
Richard Spiegel | 2b7cd1d | 2018-10-22 14:39:37 -0700 | [diff] [blame] | 116 | (res->index >> 24), rbase >> 8, rend >> 8); |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 117 | |
Richard Spiegel | 2b7cd1d | 2018-10-22 14:39:37 -0700 | [diff] [blame] | 118 | res->flags |= IORESOURCE_STORED; |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 119 | snprintf(buf, sizeof(buf), " <node %x link %x>", |
| 120 | nodeid, link_num); |
Richard Spiegel | 2b7cd1d | 2018-10-22 14:39:37 -0700 | [diff] [blame] | 121 | report_resource_stored(dev, res, buf); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 122 | } |
| 123 | |
| 124 | /** |
| 125 | * I tried to reuse the resource allocation code in set_resource() |
| 126 | * but it is too difficult to deal with the resource allocation magic. |
| 127 | */ |
| 128 | |
Elyes HAOUAS | 777ccd4 | 2018-05-22 10:52:05 +0200 | [diff] [blame] | 129 | static void create_vga_resource(struct device *dev) |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 130 | { |
| 131 | struct bus *link; |
| 132 | |
| 133 | /* find out which link the VGA card is connected, |
| 134 | * we only deal with the 'first' vga card */ |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 135 | for (link = dev->link_list ; link ; link = link->next) |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 136 | if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) |
| 137 | break; |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 138 | |
| 139 | /* no VGA card installed */ |
| 140 | if (link == NULL) |
| 141 | return; |
| 142 | |
Marshall Dawson | e2697de | 2017-09-06 10:46:36 -0600 | [diff] [blame] | 143 | printk(BIOS_DEBUG, "VGA: %s has VGA device\n", dev_path(dev)); |
Marshall Dawson | 38bded0 | 2017-09-01 09:54:48 -0600 | [diff] [blame] | 144 | /* Route A0000-BFFFF, IO 3B0-3BB 3C0-3DF */ |
Richard Spiegel | 41baf0c | 2018-10-22 13:57:18 -0700 | [diff] [blame] | 145 | pci_write_config32(SOC_ADDR_DEV, D18F1_VGAEN, VGA_ADDR_ENABLE); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 146 | } |
| 147 | |
Elyes HAOUAS | 777ccd4 | 2018-05-22 10:52:05 +0200 | [diff] [blame] | 148 | static void set_resources(struct device *dev) |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 149 | { |
| 150 | struct bus *bus; |
| 151 | struct resource *res; |
| 152 | |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 153 | /* do we need this? */ |
| 154 | create_vga_resource(dev); |
| 155 | |
| 156 | /* Set each resource we have found */ |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 157 | for (res = dev->resource_list ; res ; res = res->next) |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 158 | set_resource(dev, res, 0); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 159 | |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 160 | for (bus = dev->link_list ; bus ; bus = bus->next) |
| 161 | if (bus->children) |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 162 | assign_resources(bus); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 163 | } |
| 164 | |
| 165 | static void northbridge_init(struct device *dev) |
| 166 | { |
Kyösti Mälkki | 2e65e9c | 2021-06-16 11:00:40 +0300 | [diff] [blame] | 167 | register_new_ioapic((u8 *)IO_APIC2_ADDR); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 168 | } |
| 169 | |
| 170 | static unsigned long acpi_fill_hest(acpi_hest_t *hest) |
| 171 | { |
| 172 | void *addr, *current; |
| 173 | |
| 174 | /* Skip the HEST header. */ |
| 175 | current = (void *)(hest + 1); |
| 176 | |
| 177 | addr = agesawrapper_getlateinitptr(PICK_WHEA_MCE); |
| 178 | if (addr != NULL) |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 179 | current += acpi_create_hest_error_source(hest, current, 0, |
Richard Spiegel | 271b8a5 | 2018-11-06 16:32:28 -0700 | [diff] [blame] | 180 | (void *)((u32)addr + 2), *(uint16_t *)addr - 2); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 181 | |
| 182 | addr = agesawrapper_getlateinitptr(PICK_WHEA_CMC); |
| 183 | if (addr != NULL) |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 184 | current += acpi_create_hest_error_source(hest, current, 1, |
Richard Spiegel | 271b8a5 | 2018-11-06 16:32:28 -0700 | [diff] [blame] | 185 | (void *)((u32)addr + 2), *(uint16_t *)addr - 2); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 186 | |
| 187 | return (unsigned long)current; |
| 188 | } |
| 189 | |
Furquan Shaikh | 0f007d8 | 2020-04-24 06:41:18 -0700 | [diff] [blame] | 190 | static unsigned long agesa_write_acpi_tables(const struct device *device, |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 191 | unsigned long current, |
| 192 | acpi_rsdp_t *rsdp) |
| 193 | { |
| 194 | acpi_srat_t *srat; |
| 195 | acpi_slit_t *slit; |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 196 | acpi_header_t *alib; |
| 197 | acpi_header_t *ivrs; |
| 198 | acpi_hest_t *hest; |
| 199 | |
| 200 | /* HEST */ |
Felix Held | 9abc411 | 2023-01-18 15:47:39 +0100 | [diff] [blame] | 201 | current = acpi_align_current(current); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 202 | hest = (acpi_hest_t *)current; |
Richard Spiegel | 6a9e6cd | 2018-11-30 10:53:40 -0700 | [diff] [blame] | 203 | acpi_write_hest(hest, acpi_fill_hest); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 204 | acpi_add_table(rsdp, (void *)current); |
Richard Spiegel | 6a9e6cd | 2018-11-30 10:53:40 -0700 | [diff] [blame] | 205 | current += hest->header.length; |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 206 | |
Felix Held | 9abc411 | 2023-01-18 15:47:39 +0100 | [diff] [blame] | 207 | current = acpi_align_current(current); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 208 | printk(BIOS_DEBUG, "ACPI: * IVRS at %lx\n", current); |
| 209 | ivrs = agesawrapper_getlateinitptr(PICK_IVRS); |
| 210 | if (ivrs != NULL) { |
| 211 | memcpy((void *)current, ivrs, ivrs->length); |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 212 | ivrs = (acpi_header_t *)current; |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 213 | current += ivrs->length; |
| 214 | acpi_add_table(rsdp, ivrs); |
| 215 | } else { |
| 216 | printk(BIOS_DEBUG, " AGESA IVRS table NULL. Skipping.\n"); |
| 217 | } |
| 218 | |
| 219 | /* SRAT */ |
Felix Held | 9abc411 | 2023-01-18 15:47:39 +0100 | [diff] [blame] | 220 | current = acpi_align_current(current); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 221 | printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 222 | srat = (acpi_srat_t *)agesawrapper_getlateinitptr(PICK_SRAT); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 223 | if (srat != NULL) { |
| 224 | memcpy((void *)current, srat, srat->header.length); |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 225 | srat = (acpi_srat_t *)current; |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 226 | current += srat->header.length; |
| 227 | acpi_add_table(rsdp, srat); |
| 228 | } else { |
| 229 | printk(BIOS_DEBUG, " AGESA SRAT table NULL. Skipping.\n"); |
| 230 | } |
| 231 | |
| 232 | /* SLIT */ |
Felix Held | 9abc411 | 2023-01-18 15:47:39 +0100 | [diff] [blame] | 233 | current = acpi_align_current(current); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 234 | printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 235 | slit = (acpi_slit_t *)agesawrapper_getlateinitptr(PICK_SLIT); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 236 | if (slit != NULL) { |
| 237 | memcpy((void *)current, slit, slit->header.length); |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 238 | slit = (acpi_slit_t *)current; |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 239 | current += slit->header.length; |
| 240 | acpi_add_table(rsdp, slit); |
| 241 | } else { |
| 242 | printk(BIOS_DEBUG, " AGESA SLIT table NULL. Skipping.\n"); |
| 243 | } |
| 244 | |
| 245 | /* ALIB */ |
Felix Held | 9abc411 | 2023-01-18 15:47:39 +0100 | [diff] [blame] | 246 | current = acpi_align_current(current); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 247 | printk(BIOS_DEBUG, "ACPI: * AGESA ALIB SSDT at %lx\n", current); |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 248 | alib = (acpi_header_t *)agesawrapper_getlateinitptr(PICK_ALIB); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 249 | if (alib != NULL) { |
| 250 | memcpy((void *)current, alib, alib->length); |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 251 | alib = (acpi_header_t *)current; |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 252 | current += alib->length; |
| 253 | acpi_add_table(rsdp, (void *)alib); |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 254 | } else { |
| 255 | printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL." |
| 256 | " Skipping.\n"); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 257 | } |
| 258 | |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 259 | printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current); |
| 260 | return current; |
| 261 | } |
| 262 | |
Felix Held | 26651c8 | 2022-10-13 16:12:40 +0200 | [diff] [blame] | 263 | struct device_operations stoneyridge_northbridge_operations = { |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 264 | .read_resources = read_resources, |
| 265 | .set_resources = set_resources, |
| 266 | .enable_resources = pci_dev_enable_resources, |
| 267 | .init = northbridge_init, |
Felix Held | 915c387 | 2023-04-11 21:21:35 +0200 | [diff] [blame] | 268 | .acpi_fill_ssdt = acpi_fill_root_complex_tom, |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 269 | .write_acpi_tables = agesa_write_acpi_tables, |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 270 | }; |
| 271 | |
Marshall Dawson | 154239a | 2017-11-02 09:49:30 -0600 | [diff] [blame] | 272 | /* |
| 273 | * Enable VGA cycles. Set memory ranges of the FCH legacy devices (TPM, HPET, |
| 274 | * BIOS RAM, Watchdog Timer, IOAPIC and ACPI) as non-posted. Set remaining |
| 275 | * MMIO to posted. Route all I/O to the southbridge. |
| 276 | */ |
| 277 | void amd_initcpuio(void) |
| 278 | { |
Felix Held | 5e9afe7 | 2023-04-20 12:55:55 +0200 | [diff] [blame] | 279 | uintptr_t topmem = get_top_of_mem_below_4gb(); |
Marshall Dawson | 154239a | 2017-11-02 09:49:30 -0600 | [diff] [blame] | 280 | uintptr_t base, limit; |
| 281 | |
| 282 | /* Enable legacy video routing: D18F1xF4 VGA Enable */ |
| 283 | pci_write_config32(SOC_ADDR_DEV, D18F1_VGAEN, VGA_ADDR_ENABLE); |
| 284 | |
| 285 | /* Non-posted: range(HPET-LAPIC) or 0xfed00000 through 0xfee00000-1 */ |
| 286 | base = (HPET_BASE_ADDRESS >> 8) | MMIO_WE | MMIO_RE; |
Kyösti Mälkki | dea42e0 | 2021-05-31 20:26:16 +0300 | [diff] [blame] | 287 | limit = (ALIGN_DOWN(LAPIC_DEFAULT_BASE - 1, 64 * KiB) >> 8) | MMIO_NP; |
Marshall Dawson | 154239a | 2017-11-02 09:49:30 -0600 | [diff] [blame] | 288 | pci_write_config32(SOC_ADDR_DEV, NB_MMIO_LIMIT_LO(0), limit); |
| 289 | pci_write_config32(SOC_ADDR_DEV, NB_MMIO_BASE_LO(0), base); |
| 290 | |
| 291 | /* Remaining PCI hole posted MMIO: TOM-HPET (TOM through 0xfed00000-1 */ |
| 292 | base = (topmem >> 8) | MMIO_WE | MMIO_RE; |
| 293 | limit = ALIGN_DOWN(HPET_BASE_ADDRESS - 1, 64 * KiB) >> 8; |
| 294 | pci_write_config32(SOC_ADDR_DEV, NB_MMIO_LIMIT_LO(1), limit); |
| 295 | pci_write_config32(SOC_ADDR_DEV, NB_MMIO_BASE_LO(1), base); |
| 296 | |
| 297 | /* Route all I/O downstream */ |
| 298 | base = 0 | IO_WE | IO_RE; |
| 299 | limit = ALIGN_DOWN(0xffff, 4 * KiB); |
| 300 | pci_write_config32(SOC_ADDR_DEV, NB_IO_LIMIT(0), limit); |
| 301 | pci_write_config32(SOC_ADDR_DEV, NB_IO_BASE(0), base); |
| 302 | } |
| 303 | |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 304 | void fam15_finalize(void *chip_info) |
| 305 | { |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 306 | u32 value; |
Richard Spiegel | 41baf0c | 2018-10-22 13:57:18 -0700 | [diff] [blame] | 307 | |
| 308 | /* TODO: move IOAPIC code to dsdt.asl */ |
| 309 | pci_write_config32(SOC_GNB_DEV, NB_IOAPIC_INDEX, 0); |
| 310 | pci_write_config32(SOC_GNB_DEV, NB_IOAPIC_DATA, 5); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 311 | |
| 312 | /* disable No Snoop */ |
Richard Spiegel | 41baf0c | 2018-10-22 13:57:18 -0700 | [diff] [blame] | 313 | value = pci_read_config32(SOC_HDA0_DEV, HDA_DEV_CTRL_STATUS); |
Richard Spiegel | 3d34ae3 | 2018-04-13 13:20:08 -0700 | [diff] [blame] | 314 | value &= ~HDA_NO_SNOOP_EN; |
Richard Spiegel | 41baf0c | 2018-10-22 13:57:18 -0700 | [diff] [blame] | 315 | pci_write_config32(SOC_HDA0_DEV, HDA_DEV_CTRL_STATUS, value); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 316 | } |
| 317 | |
Elyes HAOUAS | 777ccd4 | 2018-05-22 10:52:05 +0200 | [diff] [blame] | 318 | void domain_enable_resources(struct device *dev) |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 319 | { |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 320 | /* Must be called after PCI enumeration and resource allocation */ |
Kyösti Mälkki | 9e591c4 | 2021-01-09 12:37:25 +0200 | [diff] [blame] | 321 | if (!acpi_is_wakeup_s3()) |
Kyösti Mälkki | 6e512c4 | 2018-06-14 06:57:05 +0300 | [diff] [blame] | 322 | do_agesawrapper(AMD_INIT_MID, "amdinitmid"); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 323 | } |
| 324 | |
Furquan Shaikh | fc752b6 | 2020-05-13 12:14:11 -0700 | [diff] [blame] | 325 | void domain_read_resources(struct device *dev) |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 326 | { |
Marc Jones | 5fd1d5a | 2018-02-08 15:41:54 -0700 | [diff] [blame] | 327 | uint64_t uma_base = get_uma_base(); |
| 328 | uint32_t uma_size = get_uma_size(); |
| 329 | uint32_t mem_useable = (uintptr_t)cbmem_top(); |
| 330 | msr_t tom = rdmsr(TOP_MEM); |
| 331 | msr_t high_tom = rdmsr(TOP_MEM2); |
| 332 | uint64_t high_mem_useable; |
| 333 | int idx = 0x10; |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 334 | |
Furquan Shaikh | fc752b6 | 2020-05-13 12:14:11 -0700 | [diff] [blame] | 335 | pci_domain_read_resources(dev); |
| 336 | |
Marc Jones | 5fd1d5a | 2018-02-08 15:41:54 -0700 | [diff] [blame] | 337 | /* 0x0 -> 0x9ffff */ |
Kyösti Mälkki | 27d6299 | 2022-05-24 20:25:58 +0300 | [diff] [blame] | 338 | ram_resource_kb(dev, idx++, 0, 0xa0000 / KiB); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 339 | |
Marc Jones | 5fd1d5a | 2018-02-08 15:41:54 -0700 | [diff] [blame] | 340 | /* 0xa0000 -> 0xbffff: legacy VGA */ |
Kyösti Mälkki | 27d6299 | 2022-05-24 20:25:58 +0300 | [diff] [blame] | 341 | mmio_resource_kb(dev, idx++, 0xa0000 / KiB, 0x20000 / KiB); |
Marc Jones | 5fd1d5a | 2018-02-08 15:41:54 -0700 | [diff] [blame] | 342 | |
| 343 | /* 0xc0000 -> 0xfffff: Option ROM */ |
Kyösti Mälkki | 27d6299 | 2022-05-24 20:25:58 +0300 | [diff] [blame] | 344 | reserved_ram_resource_kb(dev, idx++, 0xc0000 / KiB, 0x40000 / KiB); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 345 | |
Marshall Dawson | 29f1b74 | 2017-09-06 14:59:45 -0600 | [diff] [blame] | 346 | /* |
Martin Roth | 26f97f9 | 2021-10-01 14:53:22 -0600 | [diff] [blame] | 347 | * 0x100000 (1MiB) -> low top usable RAM |
Marc Jones | 5fd1d5a | 2018-02-08 15:41:54 -0700 | [diff] [blame] | 348 | * cbmem_top() accounts for low UMA and TSEG if they are used. |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 349 | */ |
Kyösti Mälkki | 27d6299 | 2022-05-24 20:25:58 +0300 | [diff] [blame] | 350 | ram_resource_kb(dev, idx++, (1 * MiB) / KiB, |
Marc Jones | 5fd1d5a | 2018-02-08 15:41:54 -0700 | [diff] [blame] | 351 | (mem_useable - (1 * MiB)) / KiB); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 352 | |
Martin Roth | 26f97f9 | 2021-10-01 14:53:22 -0600 | [diff] [blame] | 353 | /* Low top usable RAM -> Low top RAM (bottom pci mmio hole) */ |
Kyösti Mälkki | 27d6299 | 2022-05-24 20:25:58 +0300 | [diff] [blame] | 354 | reserved_ram_resource_kb(dev, idx++, mem_useable / KiB, |
Marc Jones | 5fd1d5a | 2018-02-08 15:41:54 -0700 | [diff] [blame] | 355 | (tom.lo - mem_useable) / KiB); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 356 | |
Marc Jones | 5fd1d5a | 2018-02-08 15:41:54 -0700 | [diff] [blame] | 357 | /* If there is memory above 4GiB */ |
| 358 | if (high_tom.hi) { |
Martin Roth | 26f97f9 | 2021-10-01 14:53:22 -0600 | [diff] [blame] | 359 | /* 4GiB -> high top usable */ |
Marc Jones | 5fd1d5a | 2018-02-08 15:41:54 -0700 | [diff] [blame] | 360 | if (uma_base >= (4ull * GiB)) |
| 361 | high_mem_useable = uma_base; |
| 362 | else |
| 363 | high_mem_useable = ((uint64_t)high_tom.lo | |
| 364 | ((uint64_t)high_tom.hi << 32)); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 365 | |
Kyösti Mälkki | 27d6299 | 2022-05-24 20:25:58 +0300 | [diff] [blame] | 366 | ram_resource_kb(dev, idx++, (4ull * GiB) / KiB, |
Marc Jones | 5fd1d5a | 2018-02-08 15:41:54 -0700 | [diff] [blame] | 367 | ((high_mem_useable - (4ull * GiB)) / KiB)); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 368 | |
Martin Roth | 26f97f9 | 2021-10-01 14:53:22 -0600 | [diff] [blame] | 369 | /* High top usable RAM -> high top RAM */ |
Marc Jones | 5fd1d5a | 2018-02-08 15:41:54 -0700 | [diff] [blame] | 370 | if (uma_base >= (4ull * GiB)) { |
Kyösti Mälkki | 27d6299 | 2022-05-24 20:25:58 +0300 | [diff] [blame] | 371 | reserved_ram_resource_kb(dev, idx++, uma_base / KiB, |
Marc Jones | 5fd1d5a | 2018-02-08 15:41:54 -0700 | [diff] [blame] | 372 | uma_size / KiB); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 373 | } |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 374 | } |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 375 | } |
| 376 | |
Richard Spiegel | 2e90ee3 | 2018-07-24 12:08:22 -0700 | [diff] [blame] | 377 | __weak void set_board_env_params(GNB_ENV_CONFIGURATION *params) { } |
| 378 | |
Marshall Dawson | 2942db6 | 2017-12-14 10:00:27 -0700 | [diff] [blame] | 379 | void SetNbEnvParams(GNB_ENV_CONFIGURATION *params) |
| 380 | { |
Martin Roth | 50f2e4c | 2018-10-29 11:16:53 -0600 | [diff] [blame] | 381 | const struct device *dev = SOC_IOMMU_DEV; |
| 382 | params->IommuSupport = dev && dev->enabled; |
Richard Spiegel | 2e90ee3 | 2018-07-24 12:08:22 -0700 | [diff] [blame] | 383 | set_board_env_params(params); |
Marshall Dawson | 2942db6 | 2017-12-14 10:00:27 -0700 | [diff] [blame] | 384 | } |
| 385 | |
| 386 | void SetNbMidParams(GNB_MID_CONFIGURATION *params) |
| 387 | { |
| 388 | /* 0=Primary and decode all VGA resources, 1=Secondary - decode none */ |
| 389 | params->iGpuVgaMode = 0; |
| 390 | params->GnbIoapicAddress = IO_APIC2_ADDR; |
| 391 | } |
Furquan Shaikh | 91a7abf | 2020-04-27 18:48:48 -0700 | [diff] [blame] | 392 | |
| 393 | void hda_soc_ssdt_quirks(const struct device *dev) |
| 394 | { |
| 395 | const char *scope = acpi_device_path(dev); |
| 396 | static const struct fieldlist list[] = { |
| 397 | FIELDLIST_OFFSET(0x42), |
| 398 | FIELDLIST_NAMESTR("NSDI", 1), |
| 399 | FIELDLIST_NAMESTR("NSDO", 1), |
| 400 | FIELDLIST_NAMESTR("NSEN", 1), |
| 401 | }; |
| 402 | struct opregion opreg = OPREGION("AZPD", PCI_CONFIG, 0x0, 0x100); |
| 403 | |
| 404 | assert(scope); |
| 405 | |
| 406 | acpigen_write_scope(scope); |
| 407 | |
| 408 | /* |
| 409 | * OperationRegion(AZPD, PCI_Config, 0x00, 0x100) |
| 410 | * Field (AZPD, AnyAcc, NoLock, Preserve) { |
| 411 | * Offset (0x42), |
| 412 | * NSDI, 1, |
| 413 | * NSDO, 1, |
| 414 | * NSEN, 1, |
| 415 | * } |
| 416 | */ |
| 417 | acpigen_write_opregion(&opreg); |
| 418 | acpigen_write_field(opreg.name, list, ARRAY_SIZE(list), |
| 419 | FIELD_ANYACC | FIELD_NOLOCK | FIELD_PRESERVE); |
| 420 | |
| 421 | /* |
| 422 | * Method (_INI, 0, NotSerialized) { |
Kyösti Mälkki | ff9ba54 | 2021-02-09 17:38:23 +0200 | [diff] [blame] | 423 | * Store (Zero, NSEN) |
| 424 | * Store (One, NSDO) |
| 425 | * Store (One, NSDI) |
Furquan Shaikh | 91a7abf | 2020-04-27 18:48:48 -0700 | [diff] [blame] | 426 | * } |
| 427 | */ |
| 428 | acpigen_write_method("_INI", 0); |
| 429 | |
Furquan Shaikh | ac204ba | 2021-02-19 10:23:17 -0800 | [diff] [blame] | 430 | acpigen_write_store_op_to_namestr(ZERO_OP, "NSEN"); |
| 431 | acpigen_write_store_op_to_namestr(ONE_OP, "NSDO"); |
| 432 | acpigen_write_store_op_to_namestr(ONE_OP, "NSDI"); |
Furquan Shaikh | 91a7abf | 2020-04-27 18:48:48 -0700 | [diff] [blame] | 433 | |
Furquan Shaikh | 91a7abf | 2020-04-27 18:48:48 -0700 | [diff] [blame] | 434 | acpigen_pop_len(); /* Method _INI */ |
| 435 | |
| 436 | acpigen_pop_len(); /* Scope */ |
| 437 | } |