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Elyes HAOUAS36787b02020-05-07 12:07:24 +02001# This file is part of the coreboot project.
2# SPDX-License-Identifier: GPL-2.0-only
Damien Zammit43a1f782015-08-19 15:16:59 +10003
4config NORTHBRIDGE_INTEL_X4X
5 bool
6
7if NORTHBRIDGE_INTEL_X4X
8
9config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
10 def_bool y
11 select HAVE_DEBUG_RAM_SETUP
Damien Zammit43a1f782015-08-19 15:16:59 +100012 select VGA
13 select INTEL_GMA_ACPI
Arthur Heymansadc571a2017-09-25 09:40:54 +020014 select CACHE_MRC_SETTINGS
Arthur Heymansc82950b2018-04-10 15:16:48 +020015 select PARALLEL_MP
Damien Zammit43a1f782015-08-19 15:16:59 +100016
Martin Roth59ff3402016-02-09 09:06:46 -070017config CBFS_SIZE
18 hex
Arthur Heymans4bc9c282017-04-06 21:37:49 +020019 default 0x100000 if !SOUTHBRIDGE_INTEL_I82801GX
Martin Roth59ff3402016-02-09 09:06:46 -070020
Damien Zammit43a1f782015-08-19 15:16:59 +100021config VGA_BIOS_ID
22 string
23 default "8086,2e32"
24
Arthur Heymans512a2d12017-05-10 13:12:37 +020025config MMCONF_BASE_ADDRESS
26 hex
27 default 0xe0000000
28
Arthur Heymansa402a9e2018-04-10 16:18:09 +020029config SMM_RESERVED_SIZE
30 hex
31 default 0x100000
32
Damien Zammit43a1f782015-08-19 15:16:59 +100033endif