Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0-only |
| 2 | |
| 3 | # TODO: Evaluate what can be moved to a common directory |
Martin Roth | 20646cd | 2023-01-04 21:27:06 -0700 | [diff] [blame] | 4 | # TODO: Update for Phoenix |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 5 | |
Felix Held | 73045b2 | 2024-01-15 17:34:37 +0100 | [diff] [blame] | 6 | config SOC_AMD_PHOENIX_BASE |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 7 | bool |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 8 | select ACPI_SOC_NVS |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 9 | select ARCH_X86 |
| 10 | select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH |
Fred Reitberger | 097f540 | 2023-02-24 13:27:13 -0500 | [diff] [blame] | 11 | select CACHE_MRC_SETTINGS |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 12 | select DRIVERS_USB_ACPI |
| 13 | select DRIVERS_USB_PCI_XHCI |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 14 | select GENERIC_GPIO_LIB |
| 15 | select HAVE_ACPI_TABLES |
| 16 | select HAVE_CF9_RESET |
| 17 | select HAVE_EM100_SUPPORT |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 18 | select HAVE_SMI_HANDLER |
| 19 | select IDT_IN_EVERY_STAGE |
| 20 | select PARALLEL_MP_AP_WORK |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 21 | select PROVIDES_ROM_SHARING |
| 22 | select PSP_SUPPORTS_EFS2_RELATIVE_ADDR if VBOOT_STARTS_BEFORE_BOOTBLOCK |
Karthikeyan Ramasubramanian | 637a21e | 2023-10-04 17:50:52 -0600 | [diff] [blame] | 23 | # TODO: (b/303516266) Re-enable CCP DMA after addressing a stall |
| 24 | # select PSP_VERSTAGE_CCP_DMA if VBOOT_STARTS_BEFORE_BOOTBLOCK |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 25 | select RESET_VECTOR_IN_RAM |
| 26 | select RTC |
| 27 | select SOC_AMD_COMMON |
Fred Reitberger | 2dceb12 | 2022-11-04 14:37:34 -0400 | [diff] [blame] | 28 | select SOC_AMD_COMMON_BLOCK_ACP_GEN2 |
Martin Roth | 9c64c08 | 2022-10-18 17:54:52 -0600 | [diff] [blame] | 29 | select SOC_AMD_COMMON_BLOCK_ACPI # TODO: Check if this is still correct |
| 30 | select SOC_AMD_COMMON_BLOCK_ACPIMMIO # TODO: Check if this is still correct |
| 31 | select SOC_AMD_COMMON_BLOCK_ACPI_ALIB # TODO: Check if this is still correct |
Felix Held | 0d59530 | 2024-02-01 17:16:06 +0100 | [diff] [blame] | 32 | select SOC_AMD_COMMON_BLOCK_ACPI_CPPC if !SOC_AMD_PHOENIX_OPENSIL # TODO: add support for openSIL case |
Felix Held | 8ec90ac | 2023-03-07 00:31:41 +0100 | [diff] [blame] | 33 | select SOC_AMD_COMMON_BLOCK_ACPI_CPU_POWER_STATE |
Martin Roth | 9c64c08 | 2022-10-18 17:54:52 -0600 | [diff] [blame] | 34 | select SOC_AMD_COMMON_BLOCK_ACPI_GPIO # TODO: Check if this is still correct |
| 35 | select SOC_AMD_COMMON_BLOCK_ACPI_IVRS # TODO: Check if this is still correct |
Felix Held | aab8a22 | 2024-01-08 23:30:38 +0100 | [diff] [blame] | 36 | select SOC_AMD_COMMON_BLOCK_ACPI_MADT |
Fred Reitberger | 2dceb12 | 2022-11-04 14:37:34 -0400 | [diff] [blame] | 37 | select SOC_AMD_COMMON_BLOCK_AOAC |
Fred Reitberger | c53ab57 | 2023-07-17 08:31:45 -0400 | [diff] [blame] | 38 | select SOC_AMD_COMMON_BLOCK_APOB |
| 39 | select SOC_AMD_COMMON_BLOCK_APOB_HASH |
Fred Reitberger | 2dceb12 | 2022-11-04 14:37:34 -0400 | [diff] [blame] | 40 | select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS |
Felix Held | a63f859 | 2023-03-24 16:30:55 +0100 | [diff] [blame] | 41 | select SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H |
Fred Reitberger | 2890841 | 2022-11-01 10:49:16 -0400 | [diff] [blame] | 42 | select SOC_AMD_COMMON_BLOCK_DATA_FABRIC |
Felix Held | 268dadb | 2023-05-31 16:23:38 +0200 | [diff] [blame] | 43 | select SOC_AMD_COMMON_BLOCK_DATA_FABRIC_DOMAIN |
Felix Held | ea83139 | 2023-08-08 02:55:09 +0200 | [diff] [blame] | 44 | select SOC_AMD_COMMON_BLOCK_DATA_FABRIC_MULTI_PCI_SEGMENT |
Fred Reitberger | 267edec | 2022-12-13 12:56:09 -0500 | [diff] [blame] | 45 | select SOC_AMD_COMMON_BLOCK_ESPI_EXTENDED_DECODE_RANGES |
Varshit Pandya | 0452d09 | 2024-02-08 21:32:57 +0530 | [diff] [blame] | 46 | select SOC_AMD_COMMON_BLOCK_GPP_CLK |
Martin Roth | 9c64c08 | 2022-10-18 17:54:52 -0600 | [diff] [blame] | 47 | select SOC_AMD_COMMON_BLOCK_GRAPHICS # TODO: Check if this is still correct |
Fred Reitberger | 267edec | 2022-12-13 12:56:09 -0500 | [diff] [blame] | 48 | select SOC_AMD_COMMON_BLOCK_HAS_ESPI |
| 49 | select SOC_AMD_COMMON_BLOCK_HAS_ESPI_ALERT_ENABLE |
Fred Reitberger | 2dceb12 | 2022-11-04 14:37:34 -0400 | [diff] [blame] | 50 | select SOC_AMD_COMMON_BLOCK_I2C |
| 51 | select SOC_AMD_COMMON_BLOCK_I23C_PAD_CTRL |
| 52 | select SOC_AMD_COMMON_BLOCK_IOMMU |
Fred Reitberger | 267edec | 2022-12-13 12:56:09 -0500 | [diff] [blame] | 53 | select SOC_AMD_COMMON_BLOCK_LPC |
Fred Reitberger | 2dceb12 | 2022-11-04 14:37:34 -0400 | [diff] [blame] | 54 | select SOC_AMD_COMMON_BLOCK_MCAX |
| 55 | select SOC_AMD_COMMON_BLOCK_NONCAR |
Fred Reitberger | a6514e2 | 2022-12-07 08:39:55 -0500 | [diff] [blame] | 56 | select SOC_AMD_COMMON_BLOCK_PCI |
| 57 | select SOC_AMD_COMMON_BLOCK_PCI_MMCONF |
| 58 | select SOC_AMD_COMMON_BLOCK_PCIE_GPP_DRIVER |
Fred Reitberger | 2dceb12 | 2022-11-04 14:37:34 -0400 | [diff] [blame] | 59 | select SOC_AMD_COMMON_BLOCK_PM |
| 60 | select SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE |
Martin Roth | 9c64c08 | 2022-10-18 17:54:52 -0600 | [diff] [blame] | 61 | select SOC_AMD_COMMON_BLOCK_PSP_GEN2 # TODO: Check if this is still correct |
Felix Held | 51d1f30 | 2023-10-04 21:10:36 +0200 | [diff] [blame] | 62 | select SOC_AMD_COMMON_BLOCK_PSP_SPL |
Martin Roth | 10c43a2 | 2023-02-02 17:21:37 -0700 | [diff] [blame] | 63 | select SOC_AMD_COMMON_BLOCK_RESET |
Fred Reitberger | 2dceb12 | 2022-11-04 14:37:34 -0400 | [diff] [blame] | 64 | select SOC_AMD_COMMON_BLOCK_SMBUS |
| 65 | select SOC_AMD_COMMON_BLOCK_SMI |
Fred Reitberger | 267edec | 2022-12-13 12:56:09 -0500 | [diff] [blame] | 66 | select SOC_AMD_COMMON_BLOCK_SMM |
| 67 | select SOC_AMD_COMMON_BLOCK_SMU |
Felix Held | 65d822e | 2023-01-12 23:11:42 +0100 | [diff] [blame] | 68 | select SOC_AMD_COMMON_BLOCK_SMU_SX_ENTRY |
Fred Reitberger | 2dceb12 | 2022-11-04 14:37:34 -0400 | [diff] [blame] | 69 | select SOC_AMD_COMMON_BLOCK_SPI |
Felix Held | 23a398e | 2023-03-23 23:44:03 +0100 | [diff] [blame] | 70 | select SOC_AMD_COMMON_BLOCK_SVI3 |
Felix Held | 60df7ca | 2023-03-24 20:33:15 +0100 | [diff] [blame] | 71 | select SOC_AMD_COMMON_BLOCK_TSC |
Fred Reitberger | 2dceb12 | 2022-11-04 14:37:34 -0400 | [diff] [blame] | 72 | select SOC_AMD_COMMON_BLOCK_UART |
| 73 | select SOC_AMD_COMMON_BLOCK_UCODE |
Jon Murphy | df2edde | 2023-04-06 17:15:14 -0600 | [diff] [blame] | 74 | select SOC_AMD_COMMON_BLOCK_XHCI |
Felix Held | ce60fb1 | 2024-01-18 20:42:54 +0100 | [diff] [blame] | 75 | select SOC_AMD_COMMON_ROMSTAGE_LEGACY_DMA_FIXUP |
Felix Held | 73045b2 | 2024-01-15 17:34:37 +0100 | [diff] [blame] | 76 | select SSE2 |
| 77 | select USE_DDR5 |
| 78 | select VBOOT_DEFINE_WIDEVINE_COUNTERS if VBOOT_STARTS_BEFORE_BOOTBLOCK |
| 79 | select VBOOT_X86_SHA256_ACCELERATION if VBOOT |
| 80 | select X86_AMD_FIXED_MTRRS |
| 81 | select X86_INIT_NEED_1_SIPI |
| 82 | |
| 83 | config SOC_AMD_PHOENIX_FSP |
| 84 | bool |
| 85 | select SOC_AMD_PHOENIX_BASE |
| 86 | select FSP_COMPRESS_FSP_M_LZMA if !ASYNC_FILE_LOADING |
| 87 | select FSP_COMPRESS_FSP_M_LZ4 if ASYNC_FILE_LOADING |
| 88 | select FSP_COMPRESS_FSP_S_LZ4 |
| 89 | select HAVE_FSP_GOP |
| 90 | select PLATFORM_USES_FSP2_0 |
Fred Reitberger | 559f3d4 | 2023-06-29 15:13:49 -0400 | [diff] [blame] | 91 | select SOC_AMD_COMMON_FSP_CCX_CPPC_HOB |
Konrad Adamczyk | ff786b5 | 2023-06-27 13:18:30 +0000 | [diff] [blame] | 92 | select SOC_AMD_COMMON_FSP_DMI_TABLES |
Martin Roth | 9c64c08 | 2022-10-18 17:54:52 -0600 | [diff] [blame] | 93 | select SOC_AMD_COMMON_FSP_PCI # TODO: Check if this is still correct |
Matt DeVillier | 6bb0f8a | 2023-11-13 20:57:12 -0600 | [diff] [blame] | 94 | select SOC_AMD_COMMON_FSP_PCIE_CLK_REQ |
Fred Reitberger | 010c408 | 2023-01-11 15:11:48 -0500 | [diff] [blame] | 95 | select SOC_AMD_COMMON_FSP_PRELOAD_FSPS |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 96 | select UDK_2017_BINDING |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 97 | select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM |
| 98 | select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT |
| 99 | select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE |
Elyes Haouas | 3cd06cc | 2023-01-05 07:42:24 +0100 | [diff] [blame] | 100 | help |
Felix Held | 73045b2 | 2024-01-15 17:34:37 +0100 | [diff] [blame] | 101 | AMD Phoenix support using FSP |
Elyes Haouas | 3cd06cc | 2023-01-05 07:42:24 +0100 | [diff] [blame] | 102 | |
Felix Held | 0d59530 | 2024-02-01 17:16:06 +0100 | [diff] [blame] | 103 | config SOC_AMD_PHOENIX_OPENSIL |
| 104 | bool |
| 105 | select SOC_AMD_PHOENIX_BASE |
| 106 | select SOC_AMD_OPENSIL |
Felix Held | 0d59530 | 2024-02-01 17:16:06 +0100 | [diff] [blame] | 107 | |
Felix Held | 73045b2 | 2024-01-15 17:34:37 +0100 | [diff] [blame] | 108 | if SOC_AMD_PHOENIX_BASE |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 109 | |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 110 | config CHIPSET_DEVICETREE |
| 111 | string |
Martin Roth | 20646cd | 2023-01-04 21:27:06 -0700 | [diff] [blame] | 112 | default "soc/amd/phoenix/chipset.cb" |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 113 | |
| 114 | config EARLY_RESERVED_DRAM_BASE |
| 115 | hex |
| 116 | default 0x2000000 |
| 117 | help |
| 118 | This variable defines the base address of the DRAM which is reserved |
| 119 | for usage by coreboot in early stages (i.e. before ramstage is up). |
| 120 | This memory gets reserved in BIOS tables to ensure that the OS does |
| 121 | not use it, thus preventing corruption of OS memory in case of S3 |
| 122 | resume. |
| 123 | |
| 124 | config EARLYRAM_BSP_STACK_SIZE |
| 125 | hex |
| 126 | default 0x1000 |
| 127 | |
| 128 | config PSP_APOB_DRAM_ADDRESS |
| 129 | hex |
| 130 | default 0x2001000 |
| 131 | help |
| 132 | Location in DRAM where the PSP will copy the AGESA PSP Output |
| 133 | Block. |
| 134 | |
| 135 | config PSP_APOB_DRAM_SIZE |
| 136 | hex |
Fred Reitberger | 4064677 | 2023-02-08 13:05:05 -0500 | [diff] [blame] | 137 | default 0x40000 |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 138 | |
| 139 | config PSP_SHAREDMEM_BASE |
| 140 | hex |
Fred Reitberger | 4064677 | 2023-02-08 13:05:05 -0500 | [diff] [blame] | 141 | default 0x2041000 if VBOOT |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 142 | default 0x0 |
| 143 | help |
| 144 | This variable defines the base address in DRAM memory where PSP copies |
| 145 | the vboot workbuf. This is used in the linker script to have a static |
| 146 | allocation for the buffer as well as for adding relevant entries in |
| 147 | the BIOS directory table for the PSP. |
| 148 | |
| 149 | config PSP_SHAREDMEM_SIZE |
| 150 | hex |
| 151 | default 0x8000 if VBOOT |
| 152 | default 0x0 |
| 153 | help |
| 154 | Sets the maximum size for the PSP to pass the vboot workbuf and |
| 155 | any logs or timestamps back to coreboot. This will be copied |
| 156 | into main memory by the PSP and will be available when the x86 is |
| 157 | started. The workbuf's base depends on the address of the reset |
| 158 | vector. |
| 159 | |
| 160 | config PRE_X86_CBMEM_CONSOLE_SIZE |
| 161 | hex |
| 162 | default 0x1600 |
| 163 | help |
| 164 | Size of the CBMEM console used in PSP verstage. |
| 165 | |
| 166 | config PRERAM_CBMEM_CONSOLE_SIZE |
| 167 | hex |
| 168 | default 0x1600 |
| 169 | help |
| 170 | Increase this value if preram cbmem console is getting truncated |
| 171 | |
| 172 | config CBFS_MCACHE_SIZE |
| 173 | hex |
| 174 | default 0x2000 if VBOOT_STARTS_BEFORE_BOOTBLOCK |
| 175 | |
| 176 | config C_ENV_BOOTBLOCK_SIZE |
| 177 | hex |
Arthur Heymans | 34684ca | 2024-02-05 15:45:21 +0100 | [diff] [blame^] | 178 | default 0x20000 |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 179 | help |
| 180 | Sets the size of the bootblock stage that should be loaded in DRAM. |
| 181 | This variable controls the DRAM allocation size in linker script |
| 182 | for bootblock stage. |
| 183 | |
| 184 | config ROMSTAGE_ADDR |
| 185 | hex |
Arthur Heymans | 34684ca | 2024-02-05 15:45:21 +0100 | [diff] [blame^] | 186 | default 0x2070000 |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 187 | help |
| 188 | Sets the address in DRAM where romstage should be loaded. |
| 189 | |
| 190 | config ROMSTAGE_SIZE |
| 191 | hex |
Arthur Heymans | 34684ca | 2024-02-05 15:45:21 +0100 | [diff] [blame^] | 192 | default 0x70000 |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 193 | help |
| 194 | Sets the size of DRAM allocation for romstage in linker script. |
| 195 | |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 196 | config VERSTAGE_ADDR |
| 197 | hex |
| 198 | depends on VBOOT_SEPARATE_VERSTAGE |
Fred Reitberger | 4064677 | 2023-02-08 13:05:05 -0500 | [diff] [blame] | 199 | default 0x21A0000 |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 200 | help |
| 201 | Sets the address in DRAM where verstage should be loaded if running |
| 202 | as a separate stage on x86. |
| 203 | |
| 204 | config VERSTAGE_SIZE |
| 205 | hex |
| 206 | depends on VBOOT_SEPARATE_VERSTAGE |
| 207 | default 0x80000 |
| 208 | help |
| 209 | Sets the size of DRAM allocation for verstage in linker script if |
| 210 | running as a separate stage on x86. |
| 211 | |
| 212 | config ASYNC_FILE_LOADING |
| 213 | bool "Loads files from SPI asynchronously" |
| 214 | select COOP_MULTITASKING |
| 215 | select SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA |
| 216 | select CBFS_PRELOAD |
| 217 | help |
| 218 | When enabled, the platform will use the LPC SPI DMA controller to |
| 219 | asynchronously load contents from the SPI ROM. This will improve |
| 220 | boot time because the CPUs can be performing useful work while the |
| 221 | SPI contents are being preloaded. |
| 222 | |
| 223 | config CBFS_CACHE_SIZE |
| 224 | hex |
| 225 | default 0x40000 if CBFS_PRELOAD |
| 226 | |
| 227 | config RO_REGION_ONLY |
| 228 | string |
| 229 | depends on VBOOT_SLOTS_RW_AB || VBOOT_SLOTS_RW_A |
| 230 | default "apu/amdfw" |
| 231 | |
| 232 | config ECAM_MMCONF_BASE_ADDRESS |
Ritul Guru | 75a073d | 2023-01-12 17:42:54 +0530 | [diff] [blame] | 233 | default 0xE0000000 |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 234 | |
| 235 | config ECAM_MMCONF_BUS_NUMBER |
Ritul Guru | 75a073d | 2023-01-12 17:42:54 +0530 | [diff] [blame] | 236 | default 256 |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 237 | |
| 238 | config MAX_CPUS |
| 239 | int |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 240 | default 16 |
| 241 | help |
| 242 | Maximum number of threads the platform can have. |
| 243 | |
Martin Roth | ab05964 | 2023-05-01 14:00:40 -0600 | [diff] [blame] | 244 | config VGA_BIOS_ID |
| 245 | string |
Felix Held | bc069ea | 2023-05-26 18:23:43 +0200 | [diff] [blame] | 246 | default "1002,15bf" |
Martin Roth | ab05964 | 2023-05-01 14:00:40 -0600 | [diff] [blame] | 247 | help |
| 248 | The default VGA BIOS PCI vendor/device ID should be set to the |
| 249 | result of the map_oprom_vendev() function in graphics.c. |
| 250 | |
Felix Held | d4440dd | 2023-05-26 18:25:33 +0200 | [diff] [blame] | 251 | # TODO: add VGA_BIOS_FILE default once the correct VBIOS binaries are available in amd_blobs |
Martin Roth | ab05964 | 2023-05-01 14:00:40 -0600 | [diff] [blame] | 252 | |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 253 | config CONSOLE_UART_BASE_ADDRESS |
| 254 | depends on CONSOLE_SERIAL && AMD_SOC_CONSOLE_UART |
| 255 | hex |
| 256 | default 0xfedc9000 if UART_FOR_CONSOLE = 0 |
| 257 | default 0xfedca000 if UART_FOR_CONSOLE = 1 |
| 258 | default 0xfedce000 if UART_FOR_CONSOLE = 2 |
| 259 | default 0xfedcf000 if UART_FOR_CONSOLE = 3 |
| 260 | default 0xfedd1000 if UART_FOR_CONSOLE = 4 |
| 261 | |
| 262 | config SMM_TSEG_SIZE |
| 263 | hex |
| 264 | default 0x800000 if HAVE_SMI_HANDLER |
| 265 | default 0x0 |
| 266 | |
| 267 | config SMM_RESERVED_SIZE |
| 268 | hex |
| 269 | default 0x180000 |
| 270 | |
| 271 | config SMM_MODULE_STACK_SIZE |
| 272 | hex |
| 273 | default 0x800 |
| 274 | |
| 275 | config ACPI_BERT |
| 276 | bool "Build ACPI BERT Table" |
| 277 | default y |
| 278 | depends on HAVE_ACPI_TABLES |
| 279 | help |
| 280 | Report Machine Check errors identified in POST to the OS in an |
| 281 | ACPI Boot Error Record Table. |
| 282 | |
| 283 | config ACPI_BERT_SIZE |
| 284 | hex |
| 285 | default 0x4000 if ACPI_BERT |
| 286 | default 0x0 |
| 287 | help |
| 288 | Specify the amount of DRAM reserved for gathering the data used to |
| 289 | generate the ACPI table. |
| 290 | |
| 291 | config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ |
| 292 | int |
| 293 | default 150 |
| 294 | |
| 295 | config DISABLE_SPI_FLASH_ROM_SHARING |
| 296 | def_bool n |
| 297 | help |
| 298 | Instruct the chipset to not honor the EGPIO67_SPI_ROM_REQ pin |
| 299 | which indicates a board level ROM transaction request. This |
| 300 | removes arbitration with board and assumes the chipset controls |
| 301 | the SPI flash bus entirely. |
| 302 | |
| 303 | config DISABLE_KEYBOARD_RESET_PIN |
| 304 | bool |
| 305 | help |
Martin Roth | 9ceac74 | 2023-02-08 14:26:02 -0700 | [diff] [blame] | 306 | Instruct the SoC to not to reset based on the state of GPIO_21, KBDRST_L. |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 307 | |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 308 | menu "PSP Configuration Options" |
| 309 | |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 310 | config AMDFW_CONFIG_FILE |
| 311 | string "AMD PSP Firmware config file" |
Martin Roth | 20646cd | 2023-01-04 21:27:06 -0700 | [diff] [blame] | 312 | default "src/soc/amd/phoenix/fw.cfg" |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 313 | help |
| 314 | Specify the path/location of AMD PSP Firmware config file. |
| 315 | |
| 316 | config PSP_DISABLE_POSTCODES |
| 317 | bool "Disable PSP post codes" |
| 318 | help |
| 319 | Disables the output of port80 post codes from PSP. |
| 320 | |
| 321 | config PSP_POSTCODES_ON_ESPI |
| 322 | bool "Use eSPI bus for PSP post codes" |
| 323 | default y |
| 324 | depends on !PSP_DISABLE_POSTCODES |
| 325 | help |
| 326 | Select to send PSP port80 post codes on eSPI bus. |
| 327 | If not selected, PSP port80 codes will be sent on LPC bus. |
| 328 | |
| 329 | config PSP_LOAD_MP2_FW |
| 330 | bool |
| 331 | default n |
| 332 | help |
| 333 | Include the MP2 firmwares and configuration into the PSP build. |
| 334 | |
| 335 | If unsure, answer 'n' |
| 336 | |
| 337 | config PSP_UNLOCK_SECURE_DEBUG |
| 338 | bool "Unlock secure debug" |
| 339 | default y |
| 340 | help |
| 341 | Select this item to enable secure debug options in PSP. |
| 342 | |
| 343 | config HAVE_PSP_WHITELIST_FILE |
| 344 | bool "Include a debug whitelist file in PSP build" |
| 345 | default n |
| 346 | help |
| 347 | Support secured unlock prior to reset using a whitelisted |
| 348 | serial number. This feature requires a signed whitelist image |
| 349 | and bootloader from AMD. |
| 350 | |
| 351 | If unsure, answer 'n' |
| 352 | |
| 353 | config PSP_WHITELIST_FILE |
| 354 | string "Debug whitelist file path" |
| 355 | depends on HAVE_PSP_WHITELIST_FILE |
Martin Roth | 20646cd | 2023-01-04 21:27:06 -0700 | [diff] [blame] | 356 | default "site-local/3rdparty/amd_blobs/phoenix/PSP/wtl-phx.sbin" |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 357 | |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 358 | config PSP_SOFTFUSE_BITS |
| 359 | string "PSP Soft Fuse bits to enable" |
Fred Reitberger | 5c1c7b6 | 2023-05-12 12:53:52 -0400 | [diff] [blame] | 360 | default "36 28 6" |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 361 | help |
| 362 | Space separated list of Soft Fuse bits to enable. |
| 363 | Bit 0: Enable secure debug (Set by PSP_UNLOCK_SECURE_DEBUG) |
| 364 | Bit 7: Disable PSP postcodes on Renoir and newer chips only |
| 365 | (Set by PSP_DISABLE_PORT80) |
| 366 | Bit 15: PSP debug output destination: |
| 367 | 0=SoC MMIO UART, 1=IO port 0x3F8 |
| 368 | Bit 29: Disable MP2 firmware loading (Set by PSP_LOAD_MP2_FW) |
| 369 | |
| 370 | See #55758 (NDA) for additional bit definitions. |
| 371 | |
| 372 | config PSP_VERSTAGE_FILE |
| 373 | string "Specify the PSP_verstage file path" |
| 374 | depends on VBOOT_STARTS_BEFORE_BOOTBLOCK |
| 375 | default "\$(obj)/psp_verstage.bin" |
| 376 | help |
| 377 | Add psp_verstage file to the build & PSP Directory Table |
| 378 | |
| 379 | config PSP_VERSTAGE_SIGNING_TOKEN |
| 380 | string "Specify the PSP_verstage Signature Token file path" |
| 381 | depends on VBOOT_STARTS_BEFORE_BOOTBLOCK |
| 382 | default "" |
| 383 | help |
| 384 | Add psp_verstage signature token to the build & PSP Directory Table |
| 385 | |
| 386 | endmenu |
| 387 | |
| 388 | config VBOOT |
| 389 | select VBOOT_VBNV_CMOS |
| 390 | select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH |
| 391 | |
| 392 | config VBOOT_STARTS_BEFORE_BOOTBLOCK |
| 393 | def_bool n |
| 394 | depends on VBOOT |
| 395 | select ARCH_VERSTAGE_ARMV7 |
| 396 | help |
| 397 | Runs verstage on the PSP. Only available on |
| 398 | certain ChromeOS branded parts from AMD. |
| 399 | |
| 400 | config VBOOT_HASH_BLOCK_SIZE |
| 401 | hex |
| 402 | default 0x9000 |
| 403 | depends on VBOOT_STARTS_BEFORE_BOOTBLOCK |
| 404 | help |
| 405 | Because the bulk of the time in psp_verstage to hash the RO cbfs is |
| 406 | spent in the overhead of doing svc calls, increasing the hash block |
| 407 | size significantly cuts the verstage hashing time as seen below. |
| 408 | |
| 409 | 4k takes 180ms |
| 410 | 16k takes 44ms |
| 411 | 32k takes 33.7ms |
| 412 | 36k takes 32.5ms |
| 413 | There's actually still room for an even bigger stack, but we've |
| 414 | reached a point of diminishing returns. |
| 415 | |
| 416 | config CMOS_RECOVERY_BYTE |
| 417 | hex |
| 418 | default 0x51 |
| 419 | depends on VBOOT_STARTS_BEFORE_BOOTBLOCK |
| 420 | help |
| 421 | If the workbuf is not passed from the PSP to coreboot, set the |
| 422 | recovery flag and reboot. The PSP will read this byte, mark the |
| 423 | recovery request in VBNV, and reset the system into recovery mode. |
| 424 | |
| 425 | This is the byte before the default first byte used by VBNV |
| 426 | (0x26 + 0x0E - 1) |
| 427 | |
| 428 | if VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK |
| 429 | |
| 430 | config RWA_REGION_ONLY |
| 431 | string |
| 432 | default "apu/amdfw_a" |
| 433 | help |
| 434 | Add a space-delimited list of filenames that should only be in the |
| 435 | RW-A section. |
| 436 | |
| 437 | config RWB_REGION_ONLY |
| 438 | string |
| 439 | default "apu/amdfw_b" |
| 440 | help |
| 441 | Add a space-delimited list of filenames that should only be in the |
| 442 | RW-B section. |
| 443 | |
| 444 | endif # VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK |
| 445 | |
Felix Held | 73045b2 | 2024-01-15 17:34:37 +0100 | [diff] [blame] | 446 | endif # SOC_AMD_PHOENIX_BASE |
| 447 | |
| 448 | if SOC_AMD_PHOENIX_FSP |
| 449 | |
| 450 | config FSP_M_ADDR |
| 451 | hex |
| 452 | default 0x20E0000 |
| 453 | help |
| 454 | Sets the address in DRAM where FSP-M should be loaded. cbfstool |
| 455 | performs relocation of FSP-M to this address. |
| 456 | |
| 457 | config FSP_M_SIZE |
| 458 | hex |
| 459 | default 0xC0000 |
| 460 | help |
| 461 | Sets the size of DRAM allocation for FSP-M in linker script. |
| 462 | |
| 463 | config FSP_TEMP_RAM_SIZE |
| 464 | hex |
| 465 | default 0x40000 |
| 466 | help |
| 467 | The amount of coreboot-allocated heap and stack usage by the FSP. |
| 468 | |
| 469 | endif # SOC_AMD_PHOENIX_FSP |
Marshall Dawson | ee01de8 | 2024-03-13 15:47:15 -0600 | [diff] [blame] | 470 | |
| 471 | if SOC_AMD_PHOENIX_OPENSIL |
| 472 | |
| 473 | config SOC_AMD_OPENSIL_STUB |
| 474 | prompt "Build with openSIL stub" |
| 475 | default y |
| 476 | |
| 477 | endif # SOC_AMD_PHOENIX_OPENSIL |