Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0-only |
| 2 | |
| 3 | # TODO: Evaluate what can be moved to a common directory |
Martin Roth | 20646cd | 2023-01-04 21:27:06 -0700 | [diff] [blame] | 4 | # TODO: Update for Phoenix |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 5 | |
Martin Roth | 20646cd | 2023-01-04 21:27:06 -0700 | [diff] [blame] | 6 | config SOC_AMD_PHOENIX |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 7 | bool |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 8 | select ACPI_SOC_NVS |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 9 | select ARCH_X86 |
| 10 | select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH |
Fred Reitberger | 097f540 | 2023-02-24 13:27:13 -0500 | [diff] [blame] | 11 | select CACHE_MRC_SETTINGS |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 12 | select DRIVERS_USB_ACPI |
| 13 | select DRIVERS_USB_PCI_XHCI |
| 14 | select FSP_COMPRESS_FSP_M_LZMA if !ASYNC_FILE_LOADING |
| 15 | select FSP_COMPRESS_FSP_M_LZ4 if ASYNC_FILE_LOADING |
| 16 | select FSP_COMPRESS_FSP_S_LZ4 |
| 17 | select GENERIC_GPIO_LIB |
| 18 | select HAVE_ACPI_TABLES |
| 19 | select HAVE_CF9_RESET |
| 20 | select HAVE_EM100_SUPPORT |
| 21 | select HAVE_FSP_GOP |
| 22 | select HAVE_SMI_HANDLER |
| 23 | select IDT_IN_EVERY_STAGE |
Martin Roth | bcb610a | 2022-10-29 13:31:54 -0600 | [diff] [blame] | 24 | select NO_DDR4 |
| 25 | select NO_DDR3 |
| 26 | select NO_DDR2 |
| 27 | select NO_LPDDR4 |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 28 | select PARALLEL_MP_AP_WORK |
| 29 | select PLATFORM_USES_FSP2_0 |
| 30 | select PROVIDES_ROM_SHARING |
| 31 | select PSP_SUPPORTS_EFS2_RELATIVE_ADDR if VBOOT_STARTS_BEFORE_BOOTBLOCK |
| 32 | select PSP_VERSTAGE_CCP_DMA if VBOOT_STARTS_BEFORE_BOOTBLOCK |
| 33 | select RESET_VECTOR_IN_RAM |
| 34 | select RTC |
| 35 | select SOC_AMD_COMMON |
Fred Reitberger | 2dceb12 | 2022-11-04 14:37:34 -0400 | [diff] [blame] | 36 | select SOC_AMD_COMMON_BLOCK_ACP_GEN2 |
Martin Roth | 9c64c08 | 2022-10-18 17:54:52 -0600 | [diff] [blame] | 37 | select SOC_AMD_COMMON_BLOCK_ACPI # TODO: Check if this is still correct |
| 38 | select SOC_AMD_COMMON_BLOCK_ACPIMMIO # TODO: Check if this is still correct |
| 39 | select SOC_AMD_COMMON_BLOCK_ACPI_ALIB # TODO: Check if this is still correct |
| 40 | select SOC_AMD_COMMON_BLOCK_ACPI_CPPC # TODO: Check if this is still correct |
Felix Held | 8ec90ac | 2023-03-07 00:31:41 +0100 | [diff] [blame] | 41 | select SOC_AMD_COMMON_BLOCK_ACPI_CPU_POWER_STATE |
Martin Roth | 9c64c08 | 2022-10-18 17:54:52 -0600 | [diff] [blame] | 42 | select SOC_AMD_COMMON_BLOCK_ACPI_GPIO # TODO: Check if this is still correct |
| 43 | select SOC_AMD_COMMON_BLOCK_ACPI_IVRS # TODO: Check if this is still correct |
Fred Reitberger | 2dceb12 | 2022-11-04 14:37:34 -0400 | [diff] [blame] | 44 | select SOC_AMD_COMMON_BLOCK_AOAC |
Martin Roth | 9c64c08 | 2022-10-18 17:54:52 -0600 | [diff] [blame] | 45 | select SOC_AMD_COMMON_BLOCK_APOB # TODO: Check if this is still correct |
Fred Reitberger | 2dceb12 | 2022-11-04 14:37:34 -0400 | [diff] [blame] | 46 | select SOC_AMD_COMMON_BLOCK_APOB_HASH |
| 47 | select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS |
Felix Held | a63f859 | 2023-03-24 16:30:55 +0100 | [diff] [blame] | 48 | select SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H |
Fred Reitberger | 2890841 | 2022-11-01 10:49:16 -0400 | [diff] [blame] | 49 | select SOC_AMD_COMMON_BLOCK_DATA_FABRIC |
Fred Reitberger | 267edec | 2022-12-13 12:56:09 -0500 | [diff] [blame] | 50 | select SOC_AMD_COMMON_BLOCK_ESPI_EXTENDED_DECODE_RANGES |
Martin Roth | 9c64c08 | 2022-10-18 17:54:52 -0600 | [diff] [blame] | 51 | select SOC_AMD_COMMON_BLOCK_GRAPHICS # TODO: Check if this is still correct |
Fred Reitberger | 267edec | 2022-12-13 12:56:09 -0500 | [diff] [blame] | 52 | select SOC_AMD_COMMON_BLOCK_HAS_ESPI |
| 53 | select SOC_AMD_COMMON_BLOCK_HAS_ESPI_ALERT_ENABLE |
Fred Reitberger | 2dceb12 | 2022-11-04 14:37:34 -0400 | [diff] [blame] | 54 | select SOC_AMD_COMMON_BLOCK_I2C |
| 55 | select SOC_AMD_COMMON_BLOCK_I23C_PAD_CTRL |
| 56 | select SOC_AMD_COMMON_BLOCK_IOMMU |
Fred Reitberger | 267edec | 2022-12-13 12:56:09 -0500 | [diff] [blame] | 57 | select SOC_AMD_COMMON_BLOCK_LPC |
Fred Reitberger | 2dceb12 | 2022-11-04 14:37:34 -0400 | [diff] [blame] | 58 | select SOC_AMD_COMMON_BLOCK_MCAX |
| 59 | select SOC_AMD_COMMON_BLOCK_NONCAR |
Fred Reitberger | a6514e2 | 2022-12-07 08:39:55 -0500 | [diff] [blame] | 60 | select SOC_AMD_COMMON_BLOCK_PCI |
| 61 | select SOC_AMD_COMMON_BLOCK_PCI_MMCONF |
| 62 | select SOC_AMD_COMMON_BLOCK_PCIE_GPP_DRIVER |
| 63 | select SOC_AMD_COMMON_BLOCK_PCIE_CLK_REQ |
Fred Reitberger | 2dceb12 | 2022-11-04 14:37:34 -0400 | [diff] [blame] | 64 | select SOC_AMD_COMMON_BLOCK_PM |
| 65 | select SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE |
Martin Roth | 9c64c08 | 2022-10-18 17:54:52 -0600 | [diff] [blame] | 66 | select SOC_AMD_COMMON_BLOCK_PSP_GEN2 # TODO: Check if this is still correct |
Martin Roth | 10c43a2 | 2023-02-02 17:21:37 -0700 | [diff] [blame] | 67 | select SOC_AMD_COMMON_BLOCK_RESET |
Fred Reitberger | 2dceb12 | 2022-11-04 14:37:34 -0400 | [diff] [blame] | 68 | select SOC_AMD_COMMON_BLOCK_SMBUS |
| 69 | select SOC_AMD_COMMON_BLOCK_SMI |
Fred Reitberger | 267edec | 2022-12-13 12:56:09 -0500 | [diff] [blame] | 70 | select SOC_AMD_COMMON_BLOCK_SMM |
| 71 | select SOC_AMD_COMMON_BLOCK_SMU |
Felix Held | 65d822e | 2023-01-12 23:11:42 +0100 | [diff] [blame] | 72 | select SOC_AMD_COMMON_BLOCK_SMU_SX_ENTRY |
Fred Reitberger | 2dceb12 | 2022-11-04 14:37:34 -0400 | [diff] [blame] | 73 | select SOC_AMD_COMMON_BLOCK_SPI |
Felix Held | 23a398e | 2023-03-23 23:44:03 +0100 | [diff] [blame] | 74 | select SOC_AMD_COMMON_BLOCK_SVI3 |
Felix Held | 60df7ca | 2023-03-24 20:33:15 +0100 | [diff] [blame] | 75 | select SOC_AMD_COMMON_BLOCK_TSC |
Fred Reitberger | 2dceb12 | 2022-11-04 14:37:34 -0400 | [diff] [blame] | 76 | select SOC_AMD_COMMON_BLOCK_UART |
| 77 | select SOC_AMD_COMMON_BLOCK_UCODE |
Jon Murphy | df2edde | 2023-04-06 17:15:14 -0600 | [diff] [blame] | 78 | select SOC_AMD_COMMON_BLOCK_XHCI |
Martin Roth | 9c64c08 | 2022-10-18 17:54:52 -0600 | [diff] [blame] | 79 | select SOC_AMD_COMMON_FSP_CCX_CPPC_HOB # TODO: Check if this is still correct |
| 80 | select SOC_AMD_COMMON_FSP_DMI_TABLES # TODO: Check if this is still correct |
| 81 | select SOC_AMD_COMMON_FSP_PCI # TODO: Check if this is still correct |
Fred Reitberger | 010c408 | 2023-01-11 15:11:48 -0500 | [diff] [blame] | 82 | select SOC_AMD_COMMON_FSP_PRELOAD_FSPS |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 83 | select SSE2 |
| 84 | select UDK_2017_BINDING |
Martin Roth | bcb610a | 2022-10-29 13:31:54 -0600 | [diff] [blame] | 85 | select USE_DDR5 |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 86 | select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM |
| 87 | select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT |
| 88 | select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE |
| 89 | select VBOOT_DEFINE_WIDEVINE_COUNTERS if VBOOT_STARTS_BEFORE_BOOTBLOCK |
| 90 | select X86_AMD_FIXED_MTRRS |
| 91 | select X86_INIT_NEED_1_SIPI |
Elyes Haouas | 3cd06cc | 2023-01-05 07:42:24 +0100 | [diff] [blame] | 92 | help |
Martin Roth | 20646cd | 2023-01-04 21:27:06 -0700 | [diff] [blame] | 93 | AMD Phoenix support |
Elyes Haouas | 3cd06cc | 2023-01-05 07:42:24 +0100 | [diff] [blame] | 94 | |
Martin Roth | 20646cd | 2023-01-04 21:27:06 -0700 | [diff] [blame] | 95 | if SOC_AMD_PHOENIX |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 96 | |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 97 | config CHIPSET_DEVICETREE |
| 98 | string |
Martin Roth | 20646cd | 2023-01-04 21:27:06 -0700 | [diff] [blame] | 99 | default "soc/amd/phoenix/chipset.cb" |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 100 | |
| 101 | config EARLY_RESERVED_DRAM_BASE |
| 102 | hex |
| 103 | default 0x2000000 |
| 104 | help |
| 105 | This variable defines the base address of the DRAM which is reserved |
| 106 | for usage by coreboot in early stages (i.e. before ramstage is up). |
| 107 | This memory gets reserved in BIOS tables to ensure that the OS does |
| 108 | not use it, thus preventing corruption of OS memory in case of S3 |
| 109 | resume. |
| 110 | |
| 111 | config EARLYRAM_BSP_STACK_SIZE |
| 112 | hex |
| 113 | default 0x1000 |
| 114 | |
| 115 | config PSP_APOB_DRAM_ADDRESS |
| 116 | hex |
| 117 | default 0x2001000 |
| 118 | help |
| 119 | Location in DRAM where the PSP will copy the AGESA PSP Output |
| 120 | Block. |
| 121 | |
| 122 | config PSP_APOB_DRAM_SIZE |
| 123 | hex |
Fred Reitberger | 4064677 | 2023-02-08 13:05:05 -0500 | [diff] [blame] | 124 | default 0x40000 |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 125 | |
| 126 | config PSP_SHAREDMEM_BASE |
| 127 | hex |
Fred Reitberger | 4064677 | 2023-02-08 13:05:05 -0500 | [diff] [blame] | 128 | default 0x2041000 if VBOOT |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 129 | default 0x0 |
| 130 | help |
| 131 | This variable defines the base address in DRAM memory where PSP copies |
| 132 | the vboot workbuf. This is used in the linker script to have a static |
| 133 | allocation for the buffer as well as for adding relevant entries in |
| 134 | the BIOS directory table for the PSP. |
| 135 | |
| 136 | config PSP_SHAREDMEM_SIZE |
| 137 | hex |
| 138 | default 0x8000 if VBOOT |
| 139 | default 0x0 |
| 140 | help |
| 141 | Sets the maximum size for the PSP to pass the vboot workbuf and |
| 142 | any logs or timestamps back to coreboot. This will be copied |
| 143 | into main memory by the PSP and will be available when the x86 is |
| 144 | started. The workbuf's base depends on the address of the reset |
| 145 | vector. |
| 146 | |
| 147 | config PRE_X86_CBMEM_CONSOLE_SIZE |
| 148 | hex |
| 149 | default 0x1600 |
| 150 | help |
| 151 | Size of the CBMEM console used in PSP verstage. |
| 152 | |
| 153 | config PRERAM_CBMEM_CONSOLE_SIZE |
| 154 | hex |
| 155 | default 0x1600 |
| 156 | help |
| 157 | Increase this value if preram cbmem console is getting truncated |
| 158 | |
| 159 | config CBFS_MCACHE_SIZE |
| 160 | hex |
| 161 | default 0x2000 if VBOOT_STARTS_BEFORE_BOOTBLOCK |
| 162 | |
| 163 | config C_ENV_BOOTBLOCK_SIZE |
| 164 | hex |
| 165 | default 0x10000 |
| 166 | help |
| 167 | Sets the size of the bootblock stage that should be loaded in DRAM. |
| 168 | This variable controls the DRAM allocation size in linker script |
| 169 | for bootblock stage. |
| 170 | |
| 171 | config ROMSTAGE_ADDR |
| 172 | hex |
Fred Reitberger | 4064677 | 2023-02-08 13:05:05 -0500 | [diff] [blame] | 173 | default 0x2060000 |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 174 | help |
| 175 | Sets the address in DRAM where romstage should be loaded. |
| 176 | |
| 177 | config ROMSTAGE_SIZE |
| 178 | hex |
| 179 | default 0x80000 |
| 180 | help |
| 181 | Sets the size of DRAM allocation for romstage in linker script. |
| 182 | |
| 183 | config FSP_M_ADDR |
| 184 | hex |
Fred Reitberger | 4064677 | 2023-02-08 13:05:05 -0500 | [diff] [blame] | 185 | default 0x20E0000 |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 186 | help |
| 187 | Sets the address in DRAM where FSP-M should be loaded. cbfstool |
| 188 | performs relocation of FSP-M to this address. |
| 189 | |
| 190 | config FSP_M_SIZE |
| 191 | hex |
| 192 | default 0xC0000 |
| 193 | help |
| 194 | Sets the size of DRAM allocation for FSP-M in linker script. |
| 195 | |
| 196 | config FSP_TEMP_RAM_SIZE |
| 197 | hex |
| 198 | default 0x40000 |
| 199 | help |
| 200 | The amount of coreboot-allocated heap and stack usage by the FSP. |
| 201 | |
| 202 | config VERSTAGE_ADDR |
| 203 | hex |
| 204 | depends on VBOOT_SEPARATE_VERSTAGE |
Fred Reitberger | 4064677 | 2023-02-08 13:05:05 -0500 | [diff] [blame] | 205 | default 0x21A0000 |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 206 | help |
| 207 | Sets the address in DRAM where verstage should be loaded if running |
| 208 | as a separate stage on x86. |
| 209 | |
| 210 | config VERSTAGE_SIZE |
| 211 | hex |
| 212 | depends on VBOOT_SEPARATE_VERSTAGE |
| 213 | default 0x80000 |
| 214 | help |
| 215 | Sets the size of DRAM allocation for verstage in linker script if |
| 216 | running as a separate stage on x86. |
| 217 | |
| 218 | config ASYNC_FILE_LOADING |
| 219 | bool "Loads files from SPI asynchronously" |
| 220 | select COOP_MULTITASKING |
| 221 | select SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA |
| 222 | select CBFS_PRELOAD |
| 223 | help |
| 224 | When enabled, the platform will use the LPC SPI DMA controller to |
| 225 | asynchronously load contents from the SPI ROM. This will improve |
| 226 | boot time because the CPUs can be performing useful work while the |
| 227 | SPI contents are being preloaded. |
| 228 | |
| 229 | config CBFS_CACHE_SIZE |
| 230 | hex |
| 231 | default 0x40000 if CBFS_PRELOAD |
| 232 | |
| 233 | config RO_REGION_ONLY |
| 234 | string |
| 235 | depends on VBOOT_SLOTS_RW_AB || VBOOT_SLOTS_RW_A |
| 236 | default "apu/amdfw" |
| 237 | |
| 238 | config ECAM_MMCONF_BASE_ADDRESS |
Ritul Guru | 75a073d | 2023-01-12 17:42:54 +0530 | [diff] [blame] | 239 | default 0xE0000000 |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 240 | |
| 241 | config ECAM_MMCONF_BUS_NUMBER |
Ritul Guru | 75a073d | 2023-01-12 17:42:54 +0530 | [diff] [blame] | 242 | default 256 |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 243 | |
| 244 | config MAX_CPUS |
| 245 | int |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 246 | default 16 |
| 247 | help |
| 248 | Maximum number of threads the platform can have. |
| 249 | |
Martin Roth | ab05964 | 2023-05-01 14:00:40 -0600 | [diff] [blame] | 250 | config VGA_BIOS_ID |
| 251 | string |
| 252 | default "1002,15BF" |
| 253 | help |
| 254 | The default VGA BIOS PCI vendor/device ID should be set to the |
| 255 | result of the map_oprom_vendev() function in graphics.c. |
| 256 | |
| 257 | config VGA_BIOS_FILE |
| 258 | string |
| 259 | default "3rdparty/amd_blobs/phoenix/Vbios.bin" |
| 260 | |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 261 | config CONSOLE_UART_BASE_ADDRESS |
| 262 | depends on CONSOLE_SERIAL && AMD_SOC_CONSOLE_UART |
| 263 | hex |
| 264 | default 0xfedc9000 if UART_FOR_CONSOLE = 0 |
| 265 | default 0xfedca000 if UART_FOR_CONSOLE = 1 |
| 266 | default 0xfedce000 if UART_FOR_CONSOLE = 2 |
| 267 | default 0xfedcf000 if UART_FOR_CONSOLE = 3 |
| 268 | default 0xfedd1000 if UART_FOR_CONSOLE = 4 |
| 269 | |
| 270 | config SMM_TSEG_SIZE |
| 271 | hex |
| 272 | default 0x800000 if HAVE_SMI_HANDLER |
| 273 | default 0x0 |
| 274 | |
| 275 | config SMM_RESERVED_SIZE |
| 276 | hex |
| 277 | default 0x180000 |
| 278 | |
| 279 | config SMM_MODULE_STACK_SIZE |
| 280 | hex |
| 281 | default 0x800 |
| 282 | |
| 283 | config ACPI_BERT |
| 284 | bool "Build ACPI BERT Table" |
| 285 | default y |
| 286 | depends on HAVE_ACPI_TABLES |
| 287 | help |
| 288 | Report Machine Check errors identified in POST to the OS in an |
| 289 | ACPI Boot Error Record Table. |
| 290 | |
| 291 | config ACPI_BERT_SIZE |
| 292 | hex |
| 293 | default 0x4000 if ACPI_BERT |
| 294 | default 0x0 |
| 295 | help |
| 296 | Specify the amount of DRAM reserved for gathering the data used to |
| 297 | generate the ACPI table. |
| 298 | |
| 299 | config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ |
| 300 | int |
| 301 | default 150 |
| 302 | |
| 303 | config DISABLE_SPI_FLASH_ROM_SHARING |
| 304 | def_bool n |
| 305 | help |
| 306 | Instruct the chipset to not honor the EGPIO67_SPI_ROM_REQ pin |
| 307 | which indicates a board level ROM transaction request. This |
| 308 | removes arbitration with board and assumes the chipset controls |
| 309 | the SPI flash bus entirely. |
| 310 | |
| 311 | config DISABLE_KEYBOARD_RESET_PIN |
| 312 | bool |
| 313 | help |
Martin Roth | 9ceac74 | 2023-02-08 14:26:02 -0700 | [diff] [blame] | 314 | Instruct the SoC to not to reset based on the state of GPIO_21, KBDRST_L. |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 315 | |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 316 | menu "PSP Configuration Options" |
| 317 | |
| 318 | config AMD_FWM_POSITION_INDEX |
| 319 | int "Firmware Directory Table location (0 to 5)" |
| 320 | range 0 5 |
| 321 | default 0 if BOARD_ROMSIZE_KB_512 |
| 322 | default 1 if BOARD_ROMSIZE_KB_1024 |
| 323 | default 2 if BOARD_ROMSIZE_KB_2048 |
| 324 | default 3 if BOARD_ROMSIZE_KB_4096 |
| 325 | default 4 if BOARD_ROMSIZE_KB_8192 |
| 326 | default 5 if BOARD_ROMSIZE_KB_16384 |
| 327 | help |
| 328 | Typically this is calculated by the ROM size, but there may |
| 329 | be situations where you want to put the firmware directory |
| 330 | table in a different location. |
| 331 | 0: 512 KB - 0xFFFA0000 |
| 332 | 1: 1 MB - 0xFFF20000 |
| 333 | 2: 2 MB - 0xFFE20000 |
| 334 | 3: 4 MB - 0xFFC20000 |
| 335 | 4: 8 MB - 0xFF820000 |
| 336 | 5: 16 MB - 0xFF020000 |
| 337 | |
| 338 | comment "AMD Firmware Directory Table set to location for 512KB ROM" |
| 339 | depends on AMD_FWM_POSITION_INDEX = 0 |
| 340 | comment "AMD Firmware Directory Table set to location for 1MB ROM" |
| 341 | depends on AMD_FWM_POSITION_INDEX = 1 |
| 342 | comment "AMD Firmware Directory Table set to location for 2MB ROM" |
| 343 | depends on AMD_FWM_POSITION_INDEX = 2 |
| 344 | comment "AMD Firmware Directory Table set to location for 4MB ROM" |
| 345 | depends on AMD_FWM_POSITION_INDEX = 3 |
| 346 | comment "AMD Firmware Directory Table set to location for 8MB ROM" |
| 347 | depends on AMD_FWM_POSITION_INDEX = 4 |
| 348 | comment "AMD Firmware Directory Table set to location for 16MB ROM" |
| 349 | depends on AMD_FWM_POSITION_INDEX = 5 |
| 350 | |
| 351 | config AMDFW_CONFIG_FILE |
| 352 | string "AMD PSP Firmware config file" |
Martin Roth | 20646cd | 2023-01-04 21:27:06 -0700 | [diff] [blame] | 353 | default "src/soc/amd/phoenix/fw.cfg" |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 354 | help |
| 355 | Specify the path/location of AMD PSP Firmware config file. |
| 356 | |
| 357 | config PSP_DISABLE_POSTCODES |
| 358 | bool "Disable PSP post codes" |
| 359 | help |
| 360 | Disables the output of port80 post codes from PSP. |
| 361 | |
| 362 | config PSP_POSTCODES_ON_ESPI |
| 363 | bool "Use eSPI bus for PSP post codes" |
| 364 | default y |
| 365 | depends on !PSP_DISABLE_POSTCODES |
| 366 | help |
| 367 | Select to send PSP port80 post codes on eSPI bus. |
| 368 | If not selected, PSP port80 codes will be sent on LPC bus. |
| 369 | |
| 370 | config PSP_LOAD_MP2_FW |
| 371 | bool |
| 372 | default n |
| 373 | help |
| 374 | Include the MP2 firmwares and configuration into the PSP build. |
| 375 | |
| 376 | If unsure, answer 'n' |
| 377 | |
| 378 | config PSP_UNLOCK_SECURE_DEBUG |
| 379 | bool "Unlock secure debug" |
| 380 | default y |
| 381 | help |
| 382 | Select this item to enable secure debug options in PSP. |
| 383 | |
| 384 | config HAVE_PSP_WHITELIST_FILE |
| 385 | bool "Include a debug whitelist file in PSP build" |
| 386 | default n |
| 387 | help |
| 388 | Support secured unlock prior to reset using a whitelisted |
| 389 | serial number. This feature requires a signed whitelist image |
| 390 | and bootloader from AMD. |
| 391 | |
| 392 | If unsure, answer 'n' |
| 393 | |
| 394 | config PSP_WHITELIST_FILE |
| 395 | string "Debug whitelist file path" |
| 396 | depends on HAVE_PSP_WHITELIST_FILE |
Martin Roth | 20646cd | 2023-01-04 21:27:06 -0700 | [diff] [blame] | 397 | default "site-local/3rdparty/amd_blobs/phoenix/PSP/wtl-phx.sbin" |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 398 | |
| 399 | config HAVE_SPL_FILE |
| 400 | bool "Have a mainboard specific SPL table file" |
| 401 | default n |
| 402 | help |
| 403 | Have a mainboard specific Security Patch Level (SPL) table file. SPL file |
| 404 | is required to support PSP FW anti-rollback and needs to be created by AMD. |
| 405 | The default SPL file applies to all boards that use the concerned SoC and |
| 406 | is dropped under 3rdparty/blobs. The mainboard specific SPL file override |
| 407 | can be applied through SPL_TABLE_FILE config. |
| 408 | |
| 409 | If unsure, answer 'n' |
| 410 | |
| 411 | config SPL_TABLE_FILE |
| 412 | string "SPL table file" |
| 413 | depends on HAVE_SPL_FILE |
Martin Roth | 20646cd | 2023-01-04 21:27:06 -0700 | [diff] [blame] | 414 | default "3rdparty/blobs/mainboard/\$(CONFIG_MAINBOARD_DIR)/TypeId0x55_SplTableBl_PHX.sbin" |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 415 | |
| 416 | config HAVE_SPL_RW_AB_FILE |
| 417 | bool "Have a separate mainboard-specific SPL file in RW A/B partitions" |
| 418 | default n |
| 419 | depends on HAVE_SPL_FILE |
| 420 | depends on VBOOT_SLOTS_RW_AB |
| 421 | help |
| 422 | Have separate mainboard-specific Security Patch Level (SPL) table |
| 423 | file for the RW A/B FMAP partitions. See the help text of |
| 424 | HAVE_SPL_FILE for a more detailed description. |
| 425 | |
| 426 | config SPL_RW_AB_TABLE_FILE |
| 427 | string "Separate SPL table file for RW A/B partitions" |
| 428 | depends on HAVE_SPL_RW_AB_FILE |
Martin Roth | 20646cd | 2023-01-04 21:27:06 -0700 | [diff] [blame] | 429 | default "3rdparty/blobs/mainboard/\$(CONFIG_MAINBOARD_DIR)/TypeId0x55_SplTableBl_PHX.sbin" |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 430 | |
| 431 | config PSP_SOFTFUSE_BITS |
| 432 | string "PSP Soft Fuse bits to enable" |
Fred Reitberger | 5c1c7b6 | 2023-05-12 12:53:52 -0400 | [diff] [blame^] | 433 | default "36 28 6" |
Martin Roth | 1a3de8e | 2022-10-06 15:57:21 -0600 | [diff] [blame] | 434 | help |
| 435 | Space separated list of Soft Fuse bits to enable. |
| 436 | Bit 0: Enable secure debug (Set by PSP_UNLOCK_SECURE_DEBUG) |
| 437 | Bit 7: Disable PSP postcodes on Renoir and newer chips only |
| 438 | (Set by PSP_DISABLE_PORT80) |
| 439 | Bit 15: PSP debug output destination: |
| 440 | 0=SoC MMIO UART, 1=IO port 0x3F8 |
| 441 | Bit 29: Disable MP2 firmware loading (Set by PSP_LOAD_MP2_FW) |
| 442 | |
| 443 | See #55758 (NDA) for additional bit definitions. |
| 444 | |
| 445 | config PSP_VERSTAGE_FILE |
| 446 | string "Specify the PSP_verstage file path" |
| 447 | depends on VBOOT_STARTS_BEFORE_BOOTBLOCK |
| 448 | default "\$(obj)/psp_verstage.bin" |
| 449 | help |
| 450 | Add psp_verstage file to the build & PSP Directory Table |
| 451 | |
| 452 | config PSP_VERSTAGE_SIGNING_TOKEN |
| 453 | string "Specify the PSP_verstage Signature Token file path" |
| 454 | depends on VBOOT_STARTS_BEFORE_BOOTBLOCK |
| 455 | default "" |
| 456 | help |
| 457 | Add psp_verstage signature token to the build & PSP Directory Table |
| 458 | |
| 459 | endmenu |
| 460 | |
| 461 | config VBOOT |
| 462 | select VBOOT_VBNV_CMOS |
| 463 | select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH |
| 464 | |
| 465 | config VBOOT_STARTS_BEFORE_BOOTBLOCK |
| 466 | def_bool n |
| 467 | depends on VBOOT |
| 468 | select ARCH_VERSTAGE_ARMV7 |
| 469 | help |
| 470 | Runs verstage on the PSP. Only available on |
| 471 | certain ChromeOS branded parts from AMD. |
| 472 | |
| 473 | config VBOOT_HASH_BLOCK_SIZE |
| 474 | hex |
| 475 | default 0x9000 |
| 476 | depends on VBOOT_STARTS_BEFORE_BOOTBLOCK |
| 477 | help |
| 478 | Because the bulk of the time in psp_verstage to hash the RO cbfs is |
| 479 | spent in the overhead of doing svc calls, increasing the hash block |
| 480 | size significantly cuts the verstage hashing time as seen below. |
| 481 | |
| 482 | 4k takes 180ms |
| 483 | 16k takes 44ms |
| 484 | 32k takes 33.7ms |
| 485 | 36k takes 32.5ms |
| 486 | There's actually still room for an even bigger stack, but we've |
| 487 | reached a point of diminishing returns. |
| 488 | |
| 489 | config CMOS_RECOVERY_BYTE |
| 490 | hex |
| 491 | default 0x51 |
| 492 | depends on VBOOT_STARTS_BEFORE_BOOTBLOCK |
| 493 | help |
| 494 | If the workbuf is not passed from the PSP to coreboot, set the |
| 495 | recovery flag and reboot. The PSP will read this byte, mark the |
| 496 | recovery request in VBNV, and reset the system into recovery mode. |
| 497 | |
| 498 | This is the byte before the default first byte used by VBNV |
| 499 | (0x26 + 0x0E - 1) |
| 500 | |
| 501 | if VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK |
| 502 | |
| 503 | config RWA_REGION_ONLY |
| 504 | string |
| 505 | default "apu/amdfw_a" |
| 506 | help |
| 507 | Add a space-delimited list of filenames that should only be in the |
| 508 | RW-A section. |
| 509 | |
| 510 | config RWB_REGION_ONLY |
| 511 | string |
| 512 | default "apu/amdfw_b" |
| 513 | help |
| 514 | Add a space-delimited list of filenames that should only be in the |
| 515 | RW-B section. |
| 516 | |
| 517 | endif # VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK |
| 518 | |
Fred Reitberger | d45402a | 2023-04-24 12:18:31 -0400 | [diff] [blame] | 519 | endif # SOC_AMD_PHOENIX |