Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 1 | |
| 2 | /** |
| 3 | * @file |
| 4 | * |
| 5 | * Southbridge CIMx configuration structure define |
| 6 | * |
| 7 | * |
| 8 | * |
| 9 | * @xrefitem bom "File Content Label" "Release Content" |
| 10 | * @e project: CIMx-SB |
| 11 | * @e sub-project: |
| 12 | * @e \$Revision:$ @e \$Date:$ |
| 13 | * |
| 14 | */ |
| 15 | /* |
| 16 | ***************************************************************************** |
| 17 | * |
| 18 | * Copyright (c) 2011, Advanced Micro Devices, Inc. |
| 19 | * All rights reserved. |
Edward O'Callaghan | b9a6700 | 2014-07-06 19:29:03 +1000 | [diff] [blame] | 20 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 21 | * Redistribution and use in source and binary forms, with or without |
| 22 | * modification, are permitted provided that the following conditions are met: |
| 23 | * * Redistributions of source code must retain the above copyright |
| 24 | * notice, this list of conditions and the following disclaimer. |
| 25 | * * Redistributions in binary form must reproduce the above copyright |
| 26 | * notice, this list of conditions and the following disclaimer in the |
| 27 | * documentation and/or other materials provided with the distribution. |
Edward O'Callaghan | b9a6700 | 2014-07-06 19:29:03 +1000 | [diff] [blame] | 28 | * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| 29 | * its contributors may be used to endorse or promote products derived |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 30 | * from this software without specific prior written permission. |
Edward O'Callaghan | b9a6700 | 2014-07-06 19:29:03 +1000 | [diff] [blame] | 31 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 32 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 33 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 34 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 35 | * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| 36 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 37 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 38 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 39 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 40 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 41 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
Edward O'Callaghan | b9a6700 | 2014-07-06 19:29:03 +1000 | [diff] [blame] | 42 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 43 | * *************************************************************************** |
| 44 | * |
| 45 | */ |
| 46 | |
| 47 | #ifndef _AMD_SBTYPE_H_ |
| 48 | #define _AMD_SBTYPE_H_ |
| 49 | |
| 50 | #pragma pack (push, 1) |
| 51 | |
| 52 | /** |
| 53 | * Entry point of Southbridge CIMx |
| 54 | * |
| 55 | * |
| 56 | * @param[in] Param1 Southbridge CIMx Function ID. |
| 57 | * @param[in] Param2 Southbridge Input Data. |
| 58 | * @param[in] pConfig Southbridge configuration structure pointer. |
| 59 | * |
| 60 | */ |
| 61 | typedef unsigned int (*SBCIM_HOOK_ENTRY) (unsigned int Param1, unsigned int Param2, void* pConfig); |
| 62 | /** |
| 63 | * SMM_SERVICE_ROUTINE - Southbridge SMI service routine |
| 64 | * |
| 65 | */ |
| 66 | typedef void (*SMM_SERVICE_ROUTINE) (void); |
| 67 | |
| 68 | |
| 69 | /** |
| 70 | * The STATIC platform information for CIMx Module. |
| 71 | * |
| 72 | */ |
| 73 | typedef struct _BUILDPARAM { |
| 74 | unsigned int BiosSize:3; /**< BiosSize |
| 75 | * @par |
| 76 | * BIOSSize [2.0] - BIOS Image Size |
| 77 | * @li <b>0</b> - 1M |
| 78 | * @li <b>1</b> - 2M |
| 79 | * @li <b>3</b> - 4M |
| 80 | * @li <b>7</b> - 8M |
| 81 | * In SB800, default ROM size is 1M Bytes, if your platform ROM bigger then 1M |
| 82 | * you have to set the ROM size outside CIMx module and before AGESA module get call |
| 83 | * |
| 84 | */ |
| 85 | unsigned int LegacyFree:1; /**< LegacyFree |
| 86 | * @par |
| 87 | * Config Southbridge CIMx module for Legacy Free Mode |
| 88 | */ |
| 89 | unsigned int SpiSpeed:2; /**< SpiSpeed |
| 90 | * @par |
| 91 | * SPI Speed [1.0] - the clock speed for non-fast read command |
| 92 | * @li <b>00</b> - 66Mhz |
| 93 | * @li <b>01</b> - 33Mhz |
| 94 | * @li <b>10</b> - 22Mhz |
| 95 | * @li <b>11</b> - 16.5Mhz |
| 96 | * |
| 97 | */ |
| 98 | unsigned int ImcEnableOverWrite:2; /**< ImcEnableOverWrite |
| 99 | * @par |
| 100 | * Imc Enable OverWrite |
| 101 | * @li <b>00</b> - by default strapping |
| 102 | * @li <b>01</b> - On |
| 103 | * @li <b>10</b> - Off |
| 104 | * |
| 105 | */ |
| 106 | unsigned int SpiFastReadEnable:1; /**< SpiFastReadEnable |
| 107 | * @par |
| 108 | * @li <b>00</b> - Disable SPI Fast Read Function |
| 109 | * @li <b>01</b> - Enable SPI Fast Read Function |
| 110 | */ |
| 111 | unsigned int SpiFastReadSpeed:2; /**< SpiFastReadSpeed |
| 112 | * @par |
| 113 | * @li <b>00</b> - 66Mhz |
| 114 | * @li <b>01</b> - 33Mhz |
| 115 | * @li <b>10</b> - 22Mhz |
| 116 | * @li <b>11</b> - 16.5Mhz |
| 117 | */ |
| 118 | unsigned int SpreadSpectrumType:1; /**< SpreadSpectrumType |
| 119 | * @par |
| 120 | * @li <b>0</b> - Spread Spectrum for normal platform |
| 121 | * @li <b>1</b> - Spread Spectrum for Ontario platform |
| 122 | */ |
| 123 | /** Dummy0 - Reserved */ |
| 124 | unsigned int Dummy0:4; |
| 125 | unsigned int EcKbd:1; /**< EcKbd |
| 126 | * @par |
| 127 | * EcKbd [16] - Platform use EC (as SIO) or SIO chip for PS/2 Keyboard and Mouse |
| 128 | * @li <b>0</b> - Use SIO PS/2 function. |
| 129 | * @li <b>1</b> - Use EC PS/2 function instead of SIO PS/2 function. ** |
| 130 | * @li <b>**</b> When set 1, EC function have to enable, otherwise, CIMx treat as legacy-free system. |
| 131 | */ |
| 132 | /** EcChannel0 - Reserved */ |
| 133 | unsigned int EcChannel0:1; |
| 134 | /** UsbMsi - Reserved */ |
| 135 | unsigned int UsbMsi:1; |
| 136 | /** HdAudioMsi - Reserved */ |
| 137 | unsigned int HdAudioMsi:1; |
| 138 | /** LpcMsi - Reserved */ |
| 139 | unsigned int LpcMsi:1; |
| 140 | /** PcibMsi - Reserved */ |
| 141 | unsigned int PcibMsi:1; |
| 142 | /** AbMsi - Reserved */ |
| 143 | unsigned int AbMsi:1; |
| 144 | /** Dummy1 - Reserved */ |
| 145 | unsigned int Dummy1:9; |
| 146 | |
| 147 | unsigned int Smbus0BaseAddress; /**< Smbus0BaseAddress |
| 148 | * @par |
| 149 | * Smbus BASE Address |
| 150 | */ |
| 151 | unsigned int Smbus1BaseAddress; /**< Smbus1BaseAddress |
| 152 | * @par |
| 153 | * Smbus1 (ASF) BASE Address |
| 154 | */ |
| 155 | unsigned int SioPmeBaseAddress; /**< SioPmeBaseAddress |
| 156 | * @par |
| 157 | * SIO PME BASE Address |
| 158 | */ |
Kerry She | 6209c82 | 2011-08-18 18:44:00 +0800 | [diff] [blame] | 159 | unsigned int SioHwmBaseAddress; /**< SioHwmBaseAddress |
| 160 | * @par |
| 161 | * SIO HWM BASE Address |
| 162 | */ |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 163 | unsigned int WatchDogTimerBase; /**< WatchDogTimerBase |
| 164 | * @par |
| 165 | * Watch Dog Timer Address |
| 166 | */ |
| 167 | unsigned int GecShadowRomBase; /**< GecShadowRomBase |
| 168 | * @par |
| 169 | * GEC (NIC) SHADOWROM BASE Address |
| 170 | */ |
| 171 | unsigned int SpiRomBaseAddress; /**< SpiRomBaseAddress |
| 172 | * @par |
| 173 | * SPI ROM BASE Address |
| 174 | */ |
| 175 | unsigned short AcpiPm1EvtBlkAddr; /**< AcpiPm1EvtBlkAddr |
| 176 | * @par |
| 177 | * ACPI PM1 event block Address |
| 178 | */ |
| 179 | unsigned short AcpiPm1CntBlkAddr; /**< AcpiPm1CntBlkAddr |
| 180 | * @par |
| 181 | * ACPI PM1 Control block Address |
| 182 | */ |
| 183 | unsigned short AcpiPmTmrBlkAddr; /**< AcpiPmTmrBlkAddr |
| 184 | * @par |
| 185 | * ACPI PM timer block Address |
| 186 | */ |
| 187 | unsigned short CpuControlBlkAddr; /**< CpuControlBlkAddr |
| 188 | * @par |
| 189 | * ACPI CPU control block Address |
| 190 | */ |
| 191 | unsigned short AcpiGpe0BlkAddr; /**< AcpiGpe0BlkAddr |
| 192 | * @par |
| 193 | * ACPI GPE0 block Address |
| 194 | */ |
| 195 | unsigned short SmiCmdPortAddr; /**< SmiCmdPortAddr |
| 196 | * @par |
| 197 | * SMI command port Address |
| 198 | */ |
| 199 | unsigned short AcpiPmaCntBlkAddr; /**< AcpiPmaCntBlkAddr |
| 200 | * @par |
| 201 | * ACPI PMA Control block Address |
| 202 | */ |
| 203 | unsigned int HpetBase; /**< HpetBase |
| 204 | * @par |
| 205 | * HPET Base address |
| 206 | */ |
| 207 | unsigned int SataIDESsid; /**< SataIDESsid |
| 208 | * @par |
| 209 | * SATA IDE mode SSID |
| 210 | */ |
| 211 | unsigned int SataRAIDSsid; /**< SataRAIDSsid |
| 212 | * @par |
| 213 | * SATA RAID mode SSID |
| 214 | */ |
| 215 | unsigned int SataRAID5Ssid; /**< SataRAID5Ssid |
| 216 | * @par |
| 217 | * SATA RAID5 mode SSID |
| 218 | */ |
| 219 | unsigned int SataAHCISsid; /**< SataAHCISsid |
| 220 | * @par |
| 221 | * SATA AHCI mode SSID |
| 222 | */ |
| 223 | unsigned int OhciSsid; /**< OhciSsid |
| 224 | * @par |
| 225 | * OHCI Controller SSID |
| 226 | */ |
| 227 | unsigned int EhciSsid; /**< EhciSsid |
| 228 | * @par |
| 229 | * EHCI Controller SSID |
| 230 | */ |
| 231 | unsigned int Ohci4Ssid; /**< Ohci4Ssid |
| 232 | * @par |
| 233 | * OHCI4 Controller SSID (Force USB 1.1 mode) |
| 234 | */ |
| 235 | unsigned int SmbusSsid; /**< SmbusSsid |
| 236 | * @par |
| 237 | * SMBUS controller SSID |
| 238 | */ |
| 239 | unsigned int IdeSsid; /**< IdeSsid |
| 240 | * @par |
| 241 | * IDE (Sata) controller SSID |
| 242 | */ |
| 243 | unsigned int AzaliaSsid; /**< AzaliaSsid |
| 244 | * @par |
| 245 | * HD Audio controller SSID |
| 246 | */ |
| 247 | unsigned int LpcSsid; /**< LpcSsid |
| 248 | * @par |
| 249 | * LPC controller SSID |
| 250 | */ |
| 251 | unsigned int PCIBSsid; /**< PCIBSsid |
| 252 | * @par |
| 253 | * PCIB controller SSID |
| 254 | */ |
| 255 | } BUILDPARAM; |
| 256 | |
| 257 | /** |
| 258 | * The EC fan MSGREG struct for CIMx Module. * |
| 259 | */ |
| 260 | typedef struct _EC_struct { |
| 261 | unsigned char MSGFun81zone0MSGREG0; ///<Thermal zone |
| 262 | unsigned char MSGFun81zone0MSGREG1; ///<Thermal zone |
| 263 | unsigned char MSGFun81zone0MSGREG2; ///<Thermal zone control byte 1 |
| 264 | unsigned char MSGFun81zone0MSGREG3; ///<Thermal zone control byte 2 |
| 265 | unsigned char MSGFun81zone0MSGREG4; ///<Bit[3:0] - Thermal diode offset adjustment in degrees Celsius. |
| 266 | unsigned char MSGFun81zone0MSGREG5; ///<Hysteresis inforamtion |
| 267 | unsigned char MSGFun81zone0MSGREG6; ///<SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 |
| 268 | unsigned char MSGFun81zone0MSGREG7; ///<Bit[1:0]: 0 - 2, SMBUS bus number where the SMBUS based temperature sensor is located. |
| 269 | unsigned char MSGFun81zone0MSGREG8; ///< @todo Style_Analyzer: Add Doxygen comments to struct entry |
| 270 | unsigned char MSGFun81zone0MSGREG9; ///< @todo Style_Analyzer: Add Doxygen comments to struct entry |
| 271 | |
| 272 | //EC LDN9 funtion 81 zone 1 |
| 273 | unsigned char MSGFun81zone1MSGREG0; ///<Thermal zone |
| 274 | unsigned char MSGFun81zone1MSGREG1; ///<Thermal zone |
| 275 | unsigned char MSGFun81zone1MSGREG2; ///<Thermal zone control byte 1 |
| 276 | unsigned char MSGFun81zone1MSGREG3; ///<Thermal zone control byte 2 |
| 277 | unsigned char MSGFun81zone1MSGREG4; ///<Bit[3:0] - Thermal diode offset adjustment in degrees Celsius. |
| 278 | unsigned char MSGFun81zone1MSGREG5; ///<Hysteresis inforamtion |
| 279 | unsigned char MSGFun81zone1MSGREG6; ///<SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 |
| 280 | unsigned char MSGFun81zone1MSGREG7; ///<Bit[1:0]: 0 - 2, SMBUS bus number where the SMBUS based temperature sensor is located. |
| 281 | unsigned char MSGFun81zone1MSGREG8; ///< @todo Style_Analyzer: Add Doxygen comments to struct entry |
| 282 | unsigned char MSGFun81zone1MSGREG9; ///< @todo Style_Analyzer: Add Doxygen comments to struct entry |
| 283 | |
| 284 | //EC LDN9 funtion 81 zone 2 |
| 285 | unsigned char MSGFun81zone2MSGREG0; ///<Thermal zone |
| 286 | unsigned char MSGFun81zone2MSGREG1; ///<Thermal zone |
| 287 | unsigned char MSGFun81zone2MSGREG2; ///<Thermal zone control byte 1 |
| 288 | unsigned char MSGFun81zone2MSGREG3; ///<Thermal zone control byte 2 |
| 289 | unsigned char MSGFun81zone2MSGREG4; ///<Bit[3:0] - Thermal diode offset adjustment in degrees Celsius. |
| 290 | unsigned char MSGFun81zone2MSGREG5; ///<Hysteresis inforamtion |
| 291 | unsigned char MSGFun81zone2MSGREG6; ///<SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 |
| 292 | unsigned char MSGFun81zone2MSGREG7; ///<Bit[1:0]: 0 - 2, SMBUS bus number where the SMBUS based temperature sensor is located. |
| 293 | unsigned char MSGFun81zone2MSGREG8; ///< @todo Style_Analyzer: Add Doxygen comments to struct entry |
| 294 | unsigned char MSGFun81zone2MSGREG9; ///< @todo Style_Analyzer: Add Doxygen comments to struct entry |
| 295 | |
| 296 | //EC LDN9 funtion 81 zone 3 |
| 297 | unsigned char MSGFun81zone3MSGREG0; ///<Thermal zone |
| 298 | unsigned char MSGFun81zone3MSGREG1; ///<Thermal zone |
| 299 | unsigned char MSGFun81zone3MSGREG2; ///<Thermal zone control byte 1 |
| 300 | unsigned char MSGFun81zone3MSGREG3; ///<Thermal zone control byte 2 |
| 301 | unsigned char MSGFun81zone3MSGREG4; ///<Bit[3:0] - Thermal diode offset adjustment in degrees Celsius. |
| 302 | unsigned char MSGFun81zone3MSGREG5; ///<Hysteresis inforamtion |
| 303 | unsigned char MSGFun81zone3MSGREG6; ///<SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 |
| 304 | unsigned char MSGFun81zone3MSGREG7; ///<Bit[1:0]: 0 - 2, SMBUS bus number where the SMBUS based temperature sensor is located. |
| 305 | unsigned char MSGFun81zone3MSGREG8; ///< @todo Style_Analyzer: Add Doxygen comments to struct entry |
| 306 | unsigned char MSGFun81zone3MSGREG9; ///< @todo Style_Analyzer: Add Doxygen comments to struct entry |
| 307 | |
| 308 | //EC LDN9 funtion 83 zone 0 |
| 309 | unsigned char MSGFun83zone0MSGREG0; ///<Thermal zone |
| 310 | unsigned char MSGFun83zone0MSGREG1; ///<Thermal zone |
| 311 | unsigned char MSGFun83zone0MSGREG2; ///<_AC0 |
| 312 | unsigned char MSGFun83zone0MSGREG3; ///<_AC1 |
| 313 | unsigned char MSGFun83zone0MSGREG4; ///<_AC2 |
| 314 | unsigned char MSGFun83zone0MSGREG5; ///<_AC3 |
| 315 | unsigned char MSGFun83zone0MSGREG6; ///<_AC4 |
| 316 | unsigned char MSGFun83zone0MSGREG7; ///<_AC5 |
| 317 | unsigned char MSGFun83zone0MSGREG8; ///<_AC6 |
| 318 | unsigned char MSGFun83zone0MSGREG9; ///<_AC7 |
| 319 | unsigned char MSGFun83zone0MSGREGA; ///<_CRT |
| 320 | unsigned char MSGFun83zone0MSGREGB; ///<_PSV |
| 321 | |
| 322 | //EC LDN9 funtion 83 zone 1 |
| 323 | unsigned char MSGFun83zone1MSGREG0; ///<Thermal zone |
| 324 | unsigned char MSGFun83zone1MSGREG1; ///<Thermal zone |
| 325 | unsigned char MSGFun83zone1MSGREG2; ///<_AC0 |
| 326 | unsigned char MSGFun83zone1MSGREG3; ///<_AC1 |
| 327 | unsigned char MSGFun83zone1MSGREG4; ///<_AC2 |
| 328 | unsigned char MSGFun83zone1MSGREG5; ///<_AC3 |
| 329 | unsigned char MSGFun83zone1MSGREG6; ///<_AC4 |
| 330 | unsigned char MSGFun83zone1MSGREG7; ///<_AC5 |
| 331 | unsigned char MSGFun83zone1MSGREG8; ///<_AC6 |
| 332 | unsigned char MSGFun83zone1MSGREG9; ///<_AC7 |
| 333 | unsigned char MSGFun83zone1MSGREGA; ///<_CRT |
| 334 | unsigned char MSGFun83zone1MSGREGB; ///<_PSV |
| 335 | |
| 336 | //EC LDN9 funtion 83 zone 2 |
| 337 | unsigned char MSGFun83zone2MSGREG0; ///<Thermal zone |
| 338 | unsigned char MSGFun83zone2MSGREG1; ///<Thermal zone |
| 339 | unsigned char MSGFun83zone2MSGREG2; ///<_AC0 |
| 340 | unsigned char MSGFun83zone2MSGREG3; ///<_AC1 |
| 341 | unsigned char MSGFun83zone2MSGREG4; ///<_AC2 |
| 342 | unsigned char MSGFun83zone2MSGREG5; ///<_AC3 |
| 343 | unsigned char MSGFun83zone2MSGREG6; ///<_AC4 |
| 344 | unsigned char MSGFun83zone2MSGREG7; ///<_AC5 |
| 345 | unsigned char MSGFun83zone2MSGREG8; ///<_AC6 |
| 346 | unsigned char MSGFun83zone2MSGREG9; ///<_AC7 |
| 347 | unsigned char MSGFun83zone2MSGREGA; ///<_CRT |
| 348 | unsigned char MSGFun83zone2MSGREGB; ///<_PSV |
| 349 | |
| 350 | //EC LDN9 funtion 83 zone 3 |
| 351 | unsigned char MSGFun83zone3MSGREG0; ///<Thermal zone |
| 352 | unsigned char MSGFun83zone3MSGREG1; ///<Thermal zone |
| 353 | unsigned char MSGFun83zone3MSGREG2; ///<_AC0 |
| 354 | unsigned char MSGFun83zone3MSGREG3; ///<_AC1 |
| 355 | unsigned char MSGFun83zone3MSGREG4; ///<_AC2 |
| 356 | unsigned char MSGFun83zone3MSGREG5; ///<_AC3 |
| 357 | unsigned char MSGFun83zone3MSGREG6; ///<_AC4 |
| 358 | unsigned char MSGFun83zone3MSGREG7; ///<_AC5 |
| 359 | unsigned char MSGFun83zone3MSGREG8; ///<_AC6 |
| 360 | unsigned char MSGFun83zone3MSGREG9; ///<_AC7 |
| 361 | unsigned char MSGFun83zone3MSGREGA; ///<_CRT |
| 362 | unsigned char MSGFun83zone3MSGREGB; ///<_PSV |
| 363 | |
| 364 | //EC LDN9 funtion 85 zone 0 |
| 365 | unsigned char MSGFun85zone0MSGREG0; ///<Thermal zone |
| 366 | unsigned char MSGFun85zone0MSGREG1; ///<Thermal zone |
| 367 | unsigned char MSGFun85zone0MSGREG2; ///<AL0 PWM level in percentage (0 - 100%) |
| 368 | unsigned char MSGFun85zone0MSGREG3; ///<AL1 PWM level in percentage (0 - 100%) |
| 369 | unsigned char MSGFun85zone0MSGREG4; ///<AL2 PWM level in percentage (0 - 100%) |
| 370 | unsigned char MSGFun85zone0MSGREG5; ///<AL3 PWM level in percentage (0 - 100%) |
| 371 | unsigned char MSGFun85zone0MSGREG6; ///<AL4 PWM level in percentage (0 - 100%) |
| 372 | unsigned char MSGFun85zone0MSGREG7; ///<AL5 PWM level in percentage (0 - 100%) |
| 373 | unsigned char MSGFun85zone0MSGREG8; ///<AL6 PWM level in percentage (0 - 100%) |
| 374 | unsigned char MSGFun85zone0MSGREG9; ///<AL7 PWM level in percentage (0 - 100%) |
| 375 | |
| 376 | //EC LDN9 funtion 85 zone 1 |
| 377 | unsigned char MSGFun85zone1MSGREG0; ///<Thermal zone |
| 378 | unsigned char MSGFun85zone1MSGREG1; ///<Thermal zone |
| 379 | unsigned char MSGFun85zone1MSGREG2; ///<AL0 PWM level in percentage (0 - 100%) |
| 380 | unsigned char MSGFun85zone1MSGREG3; ///<AL1 PWM level in percentage (0 - 100%) |
| 381 | unsigned char MSGFun85zone1MSGREG4; ///<AL2 PWM level in percentage (0 - 100%) |
| 382 | unsigned char MSGFun85zone1MSGREG5; ///<AL3 PWM level in percentage (0 - 100%) |
| 383 | unsigned char MSGFun85zone1MSGREG6; ///<AL4 PWM level in percentage (0 - 100%) |
| 384 | unsigned char MSGFun85zone1MSGREG7; ///<AL5 PWM level in percentage (0 - 100%) |
| 385 | unsigned char MSGFun85zone1MSGREG8; ///<AL6 PWM level in percentage (0 - 100%) |
| 386 | unsigned char MSGFun85zone1MSGREG9; ///<AL7 PWM level in percentage (0 - 100%) |
| 387 | |
| 388 | //EC LDN9 funtion 85 zone 2 |
| 389 | unsigned char MSGFun85zone2MSGREG0; ///<Thermal zone |
| 390 | unsigned char MSGFun85zone2MSGREG1; ///<Thermal zone |
| 391 | unsigned char MSGFun85zone2MSGREG2; ///<AL0 PWM level in percentage (0 - 100%) |
| 392 | unsigned char MSGFun85zone2MSGREG3; ///<AL1 PWM level in percentage (0 - 100%) |
| 393 | unsigned char MSGFun85zone2MSGREG4; ///<AL2 PWM level in percentage (0 - 100%) |
| 394 | unsigned char MSGFun85zone2MSGREG5; ///<AL3 PWM level in percentage (0 - 100%) |
| 395 | unsigned char MSGFun85zone2MSGREG6; ///<AL4 PWM level in percentage (0 - 100%) |
| 396 | unsigned char MSGFun85zone2MSGREG7; ///<AL5 PWM level in percentage (0 - 100%) |
| 397 | unsigned char MSGFun85zone2MSGREG8; ///<AL6 PWM level in percentage (0 - 100%) |
| 398 | unsigned char MSGFun85zone2MSGREG9; ///<AL7 PWM level in percentage (0 - 100%) |
| 399 | |
| 400 | //EC LDN9 funtion 85 zone 3 |
| 401 | unsigned char MSGFun85zone3MSGREG0; ///<Thermal zone |
| 402 | unsigned char MSGFun85zone3MSGREG1; ///<Thermal zone |
| 403 | unsigned char MSGFun85zone3MSGREG2; ///<AL0 PWM level in percentage (0 - 100%) |
| 404 | unsigned char MSGFun85zone3MSGREG3; ///<AL1 PWM level in percentage (0 - 100%) |
| 405 | unsigned char MSGFun85zone3MSGREG4; ///<AL2 PWM level in percentage (0 - 100%) |
| 406 | unsigned char MSGFun85zone3MSGREG5; ///<AL3 PWM level in percentage (0 - 100%) |
| 407 | unsigned char MSGFun85zone3MSGREG6; ///<AL4 PWM level in percentage (0 - 100%) |
| 408 | unsigned char MSGFun85zone3MSGREG7; ///<AL5 PWM level in percentage (0 - 100%) |
| 409 | unsigned char MSGFun85zone3MSGREG8; ///<AL6 PWM level in percentage (0 - 100%) |
| 410 | unsigned char MSGFun85zone3MSGREG9; ///<AL7 PWM level in percentage (0 - 100%) |
| 411 | |
| 412 | //EC LDN9 funtion 89 TEMPIN channel 0 |
| 413 | unsigned char MSGFun89zone0MSGREG0; ///<Thermal zone |
| 414 | unsigned char MSGFun89zone0MSGREG1; ///<Thermal zone |
| 415 | unsigned char MSGFun89zone0MSGREG2; ///<At DWORD bit 0-7 |
| 416 | unsigned char MSGFun89zone0MSGREG3; ///<At DWORD bit 15-8 |
| 417 | unsigned char MSGFun89zone0MSGREG4; ///<At DWORD bit 23-16 |
| 418 | unsigned char MSGFun89zone0MSGREG5; ///<At DWORD bit 31-24 |
| 419 | unsigned char MSGFun89zone0MSGREG6; ///<Ct DWORD bit 0-7 |
| 420 | unsigned char MSGFun89zone0MSGREG7; ///<Ct DWORD bit 15-8 |
| 421 | unsigned char MSGFun89zone0MSGREG8; ///<Ct DWORD bit 23-16 |
| 422 | unsigned char MSGFun89zone0MSGREG9; ///<Ct DWORD bit 31-24 |
| 423 | unsigned char MSGFun89zone0MSGREGA; ///<Mode bit 0-7 |
| 424 | |
| 425 | //EC LDN9 funtion 89 TEMPIN channel 1 |
| 426 | unsigned char MSGFun89zone1MSGREG0; ///<Thermal zone |
| 427 | unsigned char MSGFun89zone1MSGREG1; ///<Thermal zone |
| 428 | unsigned char MSGFun89zone1MSGREG2; ///<At DWORD bit 0-7 |
| 429 | unsigned char MSGFun89zone1MSGREG3; ///<At DWORD bit 15-8 |
| 430 | unsigned char MSGFun89zone1MSGREG4; ///<At DWORD bit 23-16 |
| 431 | unsigned char MSGFun89zone1MSGREG5; ///<At DWORD bit 31-24 |
| 432 | unsigned char MSGFun89zone1MSGREG6; ///<Ct DWORD bit 0-7 |
| 433 | unsigned char MSGFun89zone1MSGREG7; ///<Ct DWORD bit 15-8 |
| 434 | unsigned char MSGFun89zone1MSGREG8; ///<Ct DWORD bit 23-16 |
| 435 | unsigned char MSGFun89zone1MSGREG9; ///<Ct DWORD bit 31-24 |
| 436 | unsigned char MSGFun89zone1MSGREGA; ///<Mode bit 0-7 |
| 437 | |
| 438 | //EC LDN9 funtion 89 TEMPIN channel 2 |
| 439 | unsigned char MSGFun89zone2MSGREG0; ///<Thermal zone |
| 440 | unsigned char MSGFun89zone2MSGREG1; ///<Thermal zone |
| 441 | unsigned char MSGFun89zone2MSGREG2; ///<At DWORD bit 0-7 |
| 442 | unsigned char MSGFun89zone2MSGREG3; ///<At DWORD bit 15-8 |
| 443 | unsigned char MSGFun89zone2MSGREG4; ///<At DWORD bit 23-16 |
| 444 | unsigned char MSGFun89zone2MSGREG5; ///<At DWORD bit 31-24 |
| 445 | unsigned char MSGFun89zone2MSGREG6; ///<Ct DWORD bit 0-7 |
| 446 | unsigned char MSGFun89zone2MSGREG7; ///<Ct DWORD bit 15-8 |
| 447 | unsigned char MSGFun89zone2MSGREG8; ///<Ct DWORD bit 23-16 |
| 448 | unsigned char MSGFun89zone2MSGREG9; ///<Ct DWORD bit 31-24 |
| 449 | unsigned char MSGFun89zone2MSGREGA; ///<Mode bit 0-7 |
| 450 | |
| 451 | //EC LDN9 funtion 89 TEMPIN channel 3 |
| 452 | unsigned char MSGFun89zone3MSGREG0; ///<Thermal zone |
| 453 | unsigned char MSGFun89zone3MSGREG1; ///<Thermal zone |
| 454 | unsigned char MSGFun89zone3MSGREG2; ///<At DWORD bit 0-7 |
| 455 | unsigned char MSGFun89zone3MSGREG3; ///<At DWORD bit 15-8 |
| 456 | unsigned char MSGFun89zone3MSGREG4; ///<At DWORD bit 23-16 |
| 457 | unsigned char MSGFun89zone3MSGREG5; ///<At DWORD bit 31-24 |
| 458 | unsigned char MSGFun89zone3MSGREG6; ///<Ct DWORD bit 0-7 |
| 459 | unsigned char MSGFun89zone3MSGREG7; ///<Ct DWORD bit 15-8 |
| 460 | unsigned char MSGFun89zone3MSGREG8; ///<Ct DWORD bit 23-16 |
| 461 | unsigned char MSGFun89zone3MSGREG9; ///<Ct DWORD bit 31-24 |
| 462 | unsigned char MSGFun89zone3MSGREGA; ///<Mode bit 0-7 |
| 463 | |
| 464 | // FLAG for Fun83/85/89 support |
| 465 | unsigned short IMCFUNSupportBitMap; /// Bit0=81FunZone0 support(1=On;0=Off); bit1-3=81FunZone1-Zone3;Bit4-7=83FunZone0-Zone3;Bit8-11=85FunZone0-Zone3;Bit11-15=89FunZone0-Zone3; |
| 466 | } EC_struct; |
| 467 | /** SBGPPPORTCONFIG - Southbridge GPP port config structure */ |
| 468 | typedef struct { |
| 469 | unsigned int PortPresent:1; /**< Port connection |
| 470 | * @par |
| 471 | * @li <b>0</b> - Port doesn't have slot. No need to train the link |
| 472 | * @li <b>1</b> - Port connection defined and needs to be trained |
| 473 | */ |
| 474 | unsigned int PortDetected:1; /**< Link training status |
| 475 | * @par |
| 476 | * @li <b>0</b> - EP not detected |
| 477 | * @li <b>1</b> - EP detected |
| 478 | */ |
| 479 | unsigned int PortIsGen2:2; /**< Port link speed configuration |
| 480 | * @par |
| 481 | * @li <b>00</b> - Auto |
| 482 | * @li <b>01</b> - Forced GEN1 |
| 483 | * @li <b>10</b> - Forced GEN2 |
| 484 | * @li <b>11</b> - Reserved |
| 485 | */ |
| 486 | |
| 487 | unsigned int PortHotPlug:1; /**< Support hot plug? |
| 488 | * @par |
| 489 | * @li <b>0</b> - No support |
| 490 | * @li <b>1</b> - support |
| 491 | */ |
| 492 | /** PortMisc - Reserved */ |
| 493 | unsigned int PortMisc:27; |
| 494 | } SBGPPPORTCONFIG; |
| 495 | |
| 496 | /** CODECENTRY - Southbridge HD Audio OEM Codec structure */ |
| 497 | typedef struct _CODECENTRY { |
| 498 | /** Nid - Reserved ?? */ |
| 499 | unsigned char Nid; |
| 500 | /** Byte40 - Reserved ?? */ |
| 501 | unsigned int Byte40; |
| 502 | } CODECENTRY; |
| 503 | |
| 504 | /** CODECTBLLIST - Southbridge HD Audio Codec table list */ |
| 505 | typedef struct _CODECTBLLIST { |
| 506 | /** CodecID - Codec ID */ |
| 507 | unsigned int CodecID; |
| 508 | /** CodecTablePtr - Codec table pointer */ |
| 509 | CODECENTRY* CodecTablePtr; |
| 510 | } CODECTBLLIST; |
| 511 | |
| 512 | /** Sata Controller structure */ |
| 513 | typedef struct _SATAST { |
| 514 | unsigned char SataController:1; /**< SataController |
| 515 | * @par |
| 516 | * Sata Controller |
| 517 | * @li <b>0</b> - disable |
| 518 | * @li <b>1</b> - enable |
| 519 | */ |
| 520 | unsigned char SataIdeCombMdPriSecOpt:1; /**< SataIdeCombMdPriSecOpt - Reserved */ |
| 521 | unsigned char SataSetMaxGen2:1; /**< SataSetMaxGen2 |
| 522 | * @par |
| 523 | * Sata Controller Set to Max Gen2 mode |
| 524 | * @li <b>0</b> - disable |
| 525 | * @li <b>1</b> - enable |
| 526 | */ |
| 527 | unsigned char SataIdeCombinedMode:1; /**< SataIdeCombinedMode |
| 528 | * @par |
| 529 | * Sata IDE Controller set to Combined Mode |
| 530 | * @li <b>0</b> - enable |
| 531 | * @li <b>1</b> - disable |
| 532 | */ |
| 533 | /** SATARefClkSel - Reserved */ |
| 534 | unsigned char SATARefClkSel:2; // 4:5 |
| 535 | /** SATARefDivSel - Reserved */ |
| 536 | unsigned char SATARefDivSel:2; // 6:7 |
| 537 | } SATAST; |
| 538 | |
| 539 | /** _USBST Controller structure |
| 540 | * |
Paul Menzel | 30935b6 | 2020-10-06 08:53:57 +0200 | [diff] [blame^] | 541 | * Usb Ohci1 Contoller is defined at BIT0 |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 542 | * - 0:disable 1:enable |
| 543 | * (Bus 0 Dev 18 Func0) * |
Paul Menzel | 30935b6 | 2020-10-06 08:53:57 +0200 | [diff] [blame^] | 544 | * Usb Ehci1 Contoller is defined at BIT1 |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 545 | * - 0:disable 1:enable |
| 546 | * (Bus 0 Dev 18 Func2) * |
Paul Menzel | 30935b6 | 2020-10-06 08:53:57 +0200 | [diff] [blame^] | 547 | * Usb Ohci2 Contoller is defined at BIT2 |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 548 | * - 0:disable 1:enable |
| 549 | * (Bus 0 Dev 19 Func0) * |
Paul Menzel | 30935b6 | 2020-10-06 08:53:57 +0200 | [diff] [blame^] | 550 | * Usb Ehci2 Contoller is defined at BIT3 |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 551 | * - 0:disable 1:enable |
| 552 | * (Bus 0 Dev 19 Func2) * |
Paul Menzel | 30935b6 | 2020-10-06 08:53:57 +0200 | [diff] [blame^] | 553 | * Usb Ohci3 Contoller is defined at BIT4 |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 554 | * - 0:disable 1:enable |
| 555 | * (Bus 0 Dev 22 Func0) * |
Paul Menzel | 30935b6 | 2020-10-06 08:53:57 +0200 | [diff] [blame^] | 556 | * Usb Ehci3 Contoller is defined at BIT5 |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 557 | * - 0:disable 1:enable |
| 558 | * (Bus 0 Dev 22 Func2) * |
Paul Menzel | 30935b6 | 2020-10-06 08:53:57 +0200 | [diff] [blame^] | 559 | * Usb Ohci4 Contoller is defined at BIT6 |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 560 | * - 0:disable 1:enable |
| 561 | * (Bus 0 Dev 20 Func5) * |
| 562 | */ |
| 563 | typedef struct _USBST { |
| 564 | unsigned char Ohci1:1; ///< Ohci0 controller - 0:disable, 1:enable |
| 565 | unsigned char Ehci1:1; ///< Ehci1 controller - 0:disable, 1:enable |
| 566 | unsigned char Ohci2:1; ///< Ohci2 controller - 0:disable, 1:enable |
| 567 | unsigned char Ehci2:1; ///< Ehci2 controller - 0:disable, 1:enable |
| 568 | unsigned char Ohci3:1; ///< Ohci3 controller - 0:disable, 1:enable |
| 569 | unsigned char Ehci3:1; ///< Ehci3 controller - 0:disable, 1:enable |
| 570 | unsigned char Ohci4:1; ///< Ohci4 controller - 0:disable, 1:enable |
| 571 | unsigned char UTemp:1; ///< Reserved |
| 572 | } USBST; |
| 573 | |
| 574 | /** |
| 575 | * _AZALIAPIN - HID Azalia or GPIO define structure. |
| 576 | * |
| 577 | */ |
| 578 | typedef struct _AZALIAPIN { |
| 579 | unsigned char AzaliaSdin0:2; /**< AzaliaSdin0 |
| 580 | * @par |
Paul Menzel | 30935b6 | 2020-10-06 08:53:57 +0200 | [diff] [blame^] | 581 | * SDIN0 is defined at BIT0 & BIT1 |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 582 | * @li <b>00</b> - GPIO PIN |
| 583 | * @li <b>10</b> - As a Azalia SDIN pin |
| 584 | */ |
| 585 | unsigned char AzaliaSdin1:2; /**< AzaliaSdin1 |
| 586 | * @par |
Paul Menzel | 30935b6 | 2020-10-06 08:53:57 +0200 | [diff] [blame^] | 587 | * SDIN0 is defined at BIT2 & BIT3 |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 588 | * @li <b>00</b> - GPIO PIN |
| 589 | * @li <b>10</b> - As a Azalia SDIN pin |
| 590 | */ |
| 591 | unsigned char AzaliaSdin2:2; /**< AzaliaSdin2 |
| 592 | * @par |
Paul Menzel | 30935b6 | 2020-10-06 08:53:57 +0200 | [diff] [blame^] | 593 | * SDIN0 is defined at BIT4 & BIT5 |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 594 | * @li <b>00</b> - GPIO PIN |
| 595 | * @li <b>10</b> - As a Azalia SDIN pin |
| 596 | */ |
| 597 | unsigned char AzaliaSdin3:2; /**< AzaliaSdin3 |
| 598 | * @par |
Paul Menzel | 30935b6 | 2020-10-06 08:53:57 +0200 | [diff] [blame^] | 599 | * SDIN0 is defined at BIT6 & BIT7 |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 600 | * @li <b>00</b> - GPIO PIN |
| 601 | * @li <b>10</b> - As a Azalia SDIN pin |
| 602 | */ |
| 603 | } AZALIAPIN; |
| 604 | |
| 605 | /** AMDSBCFG - Southbridge CIMx configuration structure (Main) */ |
| 606 | typedef struct _AMDSBCFG { |
| 607 | /** StdHeader - Standard header for all AGESA/CIMx services. */ |
| 608 | AMD_CONFIG_PARAMS StdHeader; |
| 609 | |
| 610 | /** BuildParameters - The STATIC platform information for CIMx Module. */ |
| 611 | BUILDPARAM BuildParameters; |
| 612 | //offset 90 bytes (32-121) |
| 613 | //MsgXchgBiosCimx //offset 4 bytes (122-125) |
| 614 | // SATA Configuration |
| 615 | |
| 616 | union /**< union - Reserved */ |
| 617 | { /**< SATAMODE - Sata Controller structure */ |
| 618 | /** SataModeReg - Reserved */ |
| 619 | unsigned char SataModeReg; |
| 620 | /** SataMode - Reserved */ |
| 621 | SATAST SataMode; |
| 622 | } SATAMODE; |
| 623 | /** S3Resume - Flag of ACPI S3 Resume. */ |
| 624 | unsigned char S3Resume:1; // 8 |
| 625 | /** RebootRequired - Flag of Reboot system is required. */ |
| 626 | unsigned char RebootRequired:1; // 9 |
| 627 | /** SbSpiSpeedSupport - Reserved */ |
| 628 | unsigned char SbSpiSpeedSupport:1; // 10 |
| 629 | /**< SpreadSpectrum |
| 630 | * @par |
| 631 | * Spread Spectrum function |
| 632 | * @li <b>0</b> - disable |
| 633 | * @li <b>1</b> - enable |
| 634 | */ |
| 635 | unsigned char SpreadSpectrum:1; // 11 |
| 636 | /** NbSbGen2 - Reserved */ |
| 637 | unsigned char NbSbGen2:1; // 12 |
| 638 | unsigned char GppGen2:1; // 13 |
| 639 | unsigned char GppMemWrImprove:1; // 14 |
| 640 | /** MsgXchgBiosCimxReserved - Reserved */ |
| 641 | unsigned char MsgXchgBiosCimxReserved:1; // 15 (BB USED) |
| 642 | /**< SataClass - SATA Controller mode [16:18] |
| 643 | * @par |
| 644 | * @li <b>000</b> - Native IDE mode |
| 645 | * @li <b>001</b> - RAID mode |
| 646 | * @li <b>010</b> - AHCI mode |
| 647 | * @li <b>011</b> - Legacy IDE mode |
| 648 | * @li <b>100</b> - IDE->AHCI mode |
| 649 | * @li <b>101</b> - AHCI mode as 4394 ID (AMD driver) |
| 650 | * @li <b>110</b> - IDE->AHCI mode as 4394 ID (AMD driver) |
| 651 | */ |
| 652 | unsigned short SataClass:3; // 16:18 |
| 653 | /**< Sata IDE Controller mode |
| 654 | * @par |
| 655 | * @li <b>0</b> - Legacy IDE mode |
| 656 | * @li <b>1</b> - Native IDE mode |
| 657 | */ |
| 658 | unsigned short SataIdeMode:1; // 19 |
| 659 | /**< SataEspPort - SATA port is external accessible on a signal only connector (eSATA:) |
| 660 | * @par |
| 661 | * @li <b> BIT0 </b> - PORT0 set as ESP port |
| 662 | * @li <b> BIT1 </b> - PORT1 set as ESP port |
| 663 | * @li <b> BIT2 </b> - PORT2 set as ESP port |
| 664 | * @li <b> BIT3 </b> - PORT3 set as ESP port |
| 665 | * @li <b> BIT4 </b> - PORT4 set as ESP port |
| 666 | * @li <b> BIT5 </b> - PORT5 set as ESP port |
| 667 | */ |
| 668 | unsigned short SataEspPort:6; // 20:25 |
| 669 | /** SataPortPower - Reserved */ |
| 670 | unsigned short SataPortPower:6; // 31:26 |
| 671 | |
| 672 | // SATA Debug Option //offset 4 bytes (126-129) |
| 673 | |
| 674 | /**< SataPortMode - Force Each PORT to GEN1/GEN2 mode |
| 675 | * @par |
| 676 | * @li <b> 0 </b> Auto for each PORTs |
| 677 | * @li <b> BIT0 = 1</b> - PORT0 set to GEN1 |
| 678 | * @li <b> BIT1 = 1</b> - PORT0 set to GEN2 |
| 679 | * @li <b> BIT2 = 1</b> - PORT1 set to GEN1 |
| 680 | * @li <b> BIT3 = 1</b> - PORT1 set to GEN2 |
| 681 | * @li <b> BIT4 = 1</b> - PORT2 set to GEN1 |
| 682 | * @li <b> BIT5 = 1</b> - PORT2 set to GEN2 |
| 683 | * @li <b> BIT6 = 1</b> - PORT3 set to GEN1 |
| 684 | * @li <b> BIT7 = 1</b> - PORT3 set to GEN2 |
| 685 | * @li <b> BIT8 = 1</b> - PORT4 set to GEN1 |
| 686 | * @li <b> BIT9 = 1</b> - PORT4 set to GEN2 |
| 687 | * @li <b> BIT10 = 1</b> - PORT5 set to GEN1 |
| 688 | * @li <b> BIT11 = 1</b> - PORT5 set to GEN2 |
| 689 | */ |
| 690 | unsigned int SataPortMode:12; //11:0 |
| 691 | /** SATAClkSelOpt - Reserved */ |
| 692 | unsigned int SATAClkSelOpt:4; // Removed from coding side |
| 693 | /** SataAggrLinkPmCap - Reserved */ |
| 694 | unsigned int SataAggrLinkPmCap:1; //16, 0:OFF 1:ON |
| 695 | /** SataPortMultCap - Reserved */ |
| 696 | unsigned int SataPortMultCap:1; //17, 0:OFF 1:ON |
| 697 | /** SataClkAutoOff - Reserved */ |
| 698 | unsigned int SataClkAutoOff:1; //18, AutoClockOff 0:Disabled, 1:Enabled |
| 699 | /** SataPscCap - Reserved */ |
| 700 | unsigned int SataPscCap:1; //19, 0:Enable PSC capability, 1:Disable PSC capability |
| 701 | /** BIOSOSHandoff - Reserved */ |
| 702 | unsigned int BIOSOSHandoff:1; //20 |
| 703 | /** SataFisBasedSwitching - Reserved */ |
| 704 | unsigned int SataFisBasedSwitching:1; //21 |
| 705 | /** SataCccSupport - Reserved */ |
| 706 | unsigned int SataCccSupport:1; //22 |
| 707 | /** SataSscCap - Reserved */ |
| 708 | unsigned int SataSscCap:1; //23, 0:Enable SSC capability, 1:Disable SSC capability |
| 709 | /** SataMsiCapability - Reserved */ |
| 710 | unsigned int SataMsiCapability:1; //24 0:Hidden 1:Visible. This feature is disabled per RPR, but remains the interface. |
| 711 | /** SataForceRaid - Reserved */ |
| 712 | unsigned int SataForceRaid:1; //25 0:No function 1:Force RAID |
| 713 | /** SataDebugDummy - Reserved */ |
| 714 | unsigned int SataDebugDummy:6; //31:26 |
| 715 | // |
| 716 | // USB Configuration //offset 4 bytes (130-133) |
| 717 | // |
| 718 | |
| 719 | /** USBDeviceConfig - USB Controller Configuration |
| 720 | * |
Paul Menzel | 30935b6 | 2020-10-06 08:53:57 +0200 | [diff] [blame^] | 721 | * - Usb Ohci1 Contoller is defined at BIT0 |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 722 | * - 0:disable 1:enable |
| 723 | * (Bus 0 Dev 18 Func0) * |
Paul Menzel | 30935b6 | 2020-10-06 08:53:57 +0200 | [diff] [blame^] | 724 | * - Usb Ehci1 Contoller is defined at BIT1 |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 725 | * - 0:disable 1:enable |
| 726 | * (Bus 0 Dev 18 Func2) * |
Paul Menzel | 30935b6 | 2020-10-06 08:53:57 +0200 | [diff] [blame^] | 727 | * - Usb Ohci2 Contoller is defined at BIT2 |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 728 | * - 0:disable 1:enable |
| 729 | * (Bus 0 Dev 19 Func0) * |
Paul Menzel | 30935b6 | 2020-10-06 08:53:57 +0200 | [diff] [blame^] | 730 | * - Usb Ehci2 Contoller is defined at BIT3 |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 731 | * - 0:disable 1:enable |
| 732 | * (Bus 0 Dev 19 Func2) * |
Paul Menzel | 30935b6 | 2020-10-06 08:53:57 +0200 | [diff] [blame^] | 733 | * - Usb Ohci3 Contoller is defined at BIT4 |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 734 | * - 0:disable 1:enable |
| 735 | * (Bus 0 Dev 22 Func0) * |
Paul Menzel | 30935b6 | 2020-10-06 08:53:57 +0200 | [diff] [blame^] | 736 | * - Usb Ehci3 Contoller is defined at BIT5 |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 737 | * - 0:disable 1:enable |
| 738 | * (Bus 0 Dev 22 Func2) * |
Paul Menzel | 30935b6 | 2020-10-06 08:53:57 +0200 | [diff] [blame^] | 739 | * - Usb Ohci4 Contoller is defined at BIT6 |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 740 | * - 0:disable 1:enable |
| 741 | * (Bus 0 Dev 20 Func5) * |
| 742 | */ |
| 743 | union /**< union - Reserved */ |
| 744 | { /**< USBMODE - USB Controller structure */ |
| 745 | /** SataModeReg - Reserved */ |
| 746 | unsigned char UsbModeReg; |
| 747 | /** SataMode - Reserved */ |
| 748 | USBST UsbMode; |
| 749 | } USBMODE; |
| 750 | /*! |
| 751 | */ |
| 752 | |
| 753 | /**< GecConfig |
| 754 | * @par |
| 755 | * InChip Gbit NIC |
| 756 | * @li <b>1</b> - disable |
| 757 | * @li <b>0</b> - enable |
| 758 | */ |
| 759 | unsigned char GecConfig:1; //8 |
| 760 | |
| 761 | /**< IrConfig |
| 762 | * @par |
| 763 | * Ir Controller setting |
| 764 | * @li <b>00 </b> - disable |
| 765 | * @li <b>01 </b> - Rx and Tx0 |
| 766 | * @li <b>10 </b> - Rx and Tx1 |
| 767 | * @li <b>11 </b> - Rx and both Tx0,Tx1 |
| 768 | */ |
| 769 | unsigned char IrConfig:2; //9:10 |
| 770 | |
| 771 | /** GecDummy - Reserved */ |
| 772 | unsigned char GecDummy:5; //15:11 |
| 773 | |
| 774 | //Azalia Configuration |
| 775 | |
| 776 | /**< AzaliaController - Azalia Controller Configuration |
| 777 | * @par |
| 778 | * Azalia Controller [0-1] |
| 779 | * @li <b>0</b> - Auto : Detect Azalia controller automatically. |
| 780 | * @li <b>1</b> - Diable : Disable Azalia controller. |
| 781 | * @li <b>2</b> - Enable : Enable Azalia controller. |
| 782 | */ |
| 783 | unsigned char AzaliaController:2; //17:16 |
| 784 | /**< AzaliaPinCfg - Azalia Controller SDIN pin Configuration |
| 785 | * @par |
| 786 | * @li <b>0</b> - disable |
| 787 | * @li <b>1</b> - enable |
| 788 | */ |
| 789 | unsigned char AzaliaPinCfg:1; //18 |
| 790 | /**< AzaliaFrontPanel - Azalia Controller Front Panel Configuration |
| 791 | * @par |
| 792 | * Support Front Panel configuration |
| 793 | * @li <b>0</b> - Auto |
| 794 | * @li <b>1</b> - disable |
| 795 | * @li <b>2</b> - enable |
| 796 | */ |
| 797 | unsigned char AzaliaFrontPanel:2; //20:19 |
| 798 | /**< FrontPanelDetected - Force Azalia Controller Front Panel Configuration |
| 799 | * @par |
| 800 | * Force Front Panel configuration |
| 801 | * @li <b>0</b> - Not Detected |
| 802 | * @li <b>1</b> - Detected |
| 803 | */ |
| 804 | unsigned char FrontPanelDetected:1; //21 |
| 805 | /**< AzaliaSnoop - Azalia Controller Snoop feature Configuration |
| 806 | * @par |
| 807 | * Azalia Controller Snoop feature Configuration |
| 808 | * @li <b>0</b> - disable |
| 809 | * @li <b>1</b> - enable |
| 810 | */ |
| 811 | unsigned char AzaliaSnoop:1; //22 |
| 812 | /** AzaliaDummy - Reserved */ |
| 813 | unsigned char AzaliaDummy:1; //23 |
| 814 | |
| 815 | union |
| 816 | { |
| 817 | /**< AzaliaSdinPin - Azalia Controller SDIN pin Configuration |
| 818 | * |
Paul Menzel | 30935b6 | 2020-10-06 08:53:57 +0200 | [diff] [blame^] | 819 | * SDIN0 is defined at BIT0 & BIT1 |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 820 | * - 00: GPIO PIN |
| 821 | * - 01: Reserved |
| 822 | * - 10: As a Azalia SDIN pin |
| 823 | * |
Paul Menzel | 30935b6 | 2020-10-06 08:53:57 +0200 | [diff] [blame^] | 824 | * SDIN1 is defined at BIT2 & BIT3 |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 825 | * * Config same as SDIN0 |
Paul Menzel | 30935b6 | 2020-10-06 08:53:57 +0200 | [diff] [blame^] | 826 | * SDIN2 is defined at BIT4 & BIT5 |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 827 | * * Config same as SDIN0 |
Paul Menzel | 30935b6 | 2020-10-06 08:53:57 +0200 | [diff] [blame^] | 828 | * SDIN3 is defined at BIT6 & BIT7 |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 829 | * * Config same as SDIN0 |
| 830 | */ |
| 831 | unsigned char AzaliaSdinPin; |
| 832 | AZALIAPIN AzaliaConfig; |
| 833 | } AZALIACONFIG; |
| 834 | |
| 835 | /** AZOEMTBL - Azalia Controller OEM Codec Table Pointer |
| 836 | * |
| 837 | */ |
| 838 | union |
| 839 | { |
| 840 | PLACEHOLDER PlaceHolder; |
| 841 | CODECTBLLIST* pAzaliaOemCodecTablePtr; //offset 4 bytes (134-137) |
| 842 | } AZOEMTBL; |
| 843 | |
| 844 | /** AZOEMFPTBL - Azalia Controller Front Panel OEM Table Pointer |
| 845 | * |
| 846 | */ |
| 847 | union |
| 848 | { |
| 849 | PLACEHOLDER PlaceHolder; |
| 850 | void* pAzaliaOemFpCodecTablePtr; //offset 4 bytes (138-141) |
| 851 | } AZOEMFPTBL; |
| 852 | |
| 853 | //Miscellaneous Configuration //offset 4 bytes (142-145) |
| 854 | /** AnyHT200MhzLink - Reserved */ |
| 855 | unsigned int AnyHT200MhzLink:1; //0 |
| 856 | /**< HpetTimer - South Bridge Hpet Timer Configuration |
| 857 | * @par |
| 858 | * @li <b>0</b> - disable |
| 859 | * @li <b>1</b> - enable |
| 860 | */ |
| 861 | unsigned int HpetTimer:1; //1 |
| 862 | /**< PciClks - PCI Slot Clock Control |
| 863 | * @par |
| 864 | * PCI SLOT 0 define at BIT0 |
| 865 | * - 00: disable |
| 866 | * - 01: enable |
| 867 | * |
| 868 | * PCI SLOT 1 define at BIT1 |
| 869 | * * Config same as PCI SLOT0 |
| 870 | * PCI SLOT 2 define at BIT2 |
| 871 | * * Config same as PCI SLOT0 |
| 872 | * PCI SLOT 3 define at BIT3 |
| 873 | * * Config same as PCI SLOT0 |
| 874 | * PCI SLOT 4 define at BIT4 |
| 875 | * * Config same as PCI SLOT0 |
| 876 | */ |
| 877 | unsigned int PciClks:5; //2:6 |
| 878 | /** MiscReserved1 - Reserved */ |
| 879 | unsigned int MiscReserved1:4; //9:7, Reserved |
| 880 | /** MobilePowerSavings - Debug function Reserved */ |
| 881 | unsigned int MobilePowerSavings:1; //11, 0:Disable, 1:Enable Power saving features especially for Mobile platform |
| 882 | /** MiscDummy1 - Debug function Reserved */ |
| 883 | unsigned int MiscDummy1:1; |
| 884 | /** NativePcieSupport - Debug function Reserved */ |
| 885 | unsigned int NativePcieSupport:1; //13, 0:Enable, 1:Disabled |
| 886 | /** FlashPinConfig - Debug function Reserved */ |
| 887 | unsigned int FlashPinConfig:1; //14, 0:desktop mode 1:mobile mode |
| 888 | /** UsbPhyPowerDown - Debug function Reserved */ |
| 889 | unsigned int UsbPhyPowerDown:1; //15 |
| 890 | /** PcibClkStopOverride - Debug function Reserved */ |
| 891 | unsigned int PcibClkStopOverride:10; //25:16 |
| 892 | /**< HpetMsiDis - South Bridge HPET MSI Configuration |
| 893 | * @par |
| 894 | * @li <b>1</b> - disable |
| 895 | * @li <b>0</b> - enable |
| 896 | */ |
| 897 | unsigned int HpetMsiDis:1; //26 |
| 898 | /**< ResetCpuOnSyncFlood - Rest CPU on Sync Flood |
| 899 | * @par |
| 900 | * @li <b>0</b> - disable |
| 901 | * @li <b>1</b> - enable |
| 902 | */ |
| 903 | unsigned int ResetCpuOnSyncFlood:1; //27 |
| 904 | /**< LdtStpDisable - LdtStp# output disable |
| 905 | * @par |
| 906 | * @li <b>0</b> - LdtStp# output enable |
| 907 | * @li <b>1</b> - LdtStp# output disable |
| 908 | */ |
| 909 | unsigned int LdtStpDisable:1; //28 |
| 910 | /**< MTC1e - Message Triggered C1e |
| 911 | * @par |
| 912 | * @li <b>0</b> - disable |
| 913 | * @li <b>1</b> - enable |
| 914 | */ |
| 915 | unsigned int MTC1e:1; //29 |
| 916 | /** MiscDummy - Reserved */ |
| 917 | unsigned int MiscDummy:2; //31:30 |
Kerry She | 6209c82 | 2011-08-18 18:44:00 +0800 | [diff] [blame] | 918 | unsigned int SioHwmPortEnable:1; // Enable SuperIO HWM access via LPC |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 919 | |
| 920 | //DebugOptions //offset 4 bytes (146-149) |
| 921 | /** PcibAutoClkCtrlLow - Debug function Reserved */ |
| 922 | unsigned int PcibAutoClkCtrlLow:16; |
| 923 | /** PcibAutoClkCtrlHigh - Debug function Reserved */ |
| 924 | unsigned int PcibAutoClkCtrlHigh:16; |
| 925 | |
| 926 | /**< OEMPROGTBL - ACPI MMIO register setting table OEM override |
| 927 | * @par |
| 928 | * OEM table for customer override ACPI MMIO register in their code. |
| 929 | */ |
| 930 | union |
| 931 | { |
| 932 | PLACEHOLDER OemProgrammingTablePtr; //offset 4 bytes (150-153) |
| 933 | void *OemProgrammingTablePtr_Ptr; |
| 934 | } OEMPROGTBL; |
| 935 | |
| 936 | //Gpp Configuration //offset 24 bytes total (154-177) |
| 937 | union { |
| 938 | unsigned int PORTCFG32; |
| 939 | SBGPPPORTCONFIG PortCfg; |
| 940 | } PORTCONFIG[MAX_GPP_PORTS]; //offset 16 bytes |
| 941 | |
| 942 | unsigned int GppLinkConfig; // GPP_LINK_CONFIG = PCIE_GPP_Enable[3:0] |
| 943 | // 0000 - Port ABCD -> 4:0:0:0 |
| 944 | // 0001 - N/A |
| 945 | // 0010 - Port ABCD -> 2:2:0:0 |
| 946 | // 0011 - Port ABCD -> 2:1:1:0 |
| 947 | // 0100 - Port ABCD -> 1:1:1:1 |
| 948 | // |
| 949 | unsigned int GppFoundGfxDev:4; //3:0 If port A-D (mapped to bit [3:0]) has GFX EP detected |
| 950 | unsigned int CoreGen2Enable:1; //4 |
| 951 | unsigned int GppFunctionEnable:1; //5 |
| 952 | unsigned int GppUnhidePorts:1; //6 |
| 953 | unsigned int AlinkPhyPllPowerDown:1; //7 |
| 954 | unsigned int GppConfigDummy1:2; //9:8 |
| 955 | unsigned int GppLaneReversal:1; //10 |
| 956 | unsigned int GppPhyPllPowerDown:1; //11 |
| 957 | unsigned int GppCompliance :1; //12 |
| 958 | unsigned int GppPortAspm:8; //20:13 ASPM state for GPP ports, 14:13 for port0, ..., 20:19 for port3 |
| 959 | // 00 - Disabled |
| 960 | // 01 - L0s |
| 961 | // 10 - L1 |
| 962 | // 11 - L0s + L1 |
| 963 | // |
| 964 | unsigned int GppConfigDummy:11; //31:21 |
| 965 | |
| 966 | //TempMMIO //offset 4 bytes (178-181) |
| 967 | unsigned int TempMMIO; |
| 968 | |
| 969 | // DebugOption2 |
| 970 | unsigned int GecPhyStatus:1; |
| 971 | unsigned int GecDebugOptionDummy:7; |
| 972 | unsigned int SBGecPwr:2; |
| 973 | unsigned int SBGecDebugBus:1; |
| 974 | unsigned int DebugOption2Dummy1:1; |
| 975 | unsigned int DebugOption2Dummy2:1; |
| 976 | unsigned int SbPcieOrderRule:1; |
| 977 | unsigned int SbUsbPll:1; |
| 978 | unsigned int AcDcMsg:1; |
| 979 | unsigned int TimerTickTrack:1; |
| 980 | unsigned int ClockInterruptTag:1; |
| 981 | unsigned int OhciTrafficHanding:1; |
| 982 | unsigned int EhciTrafficHanding:1; |
| 983 | unsigned int FusionMsgCMultiCore:1; |
| 984 | unsigned int FusionMsgCStage:1; |
| 985 | /**< UsbRxMode - CG PLL multiplier for USB Rx 1.1 mode |
| 986 | * @par |
| 987 | * @li <b>0</b> - disable |
| 988 | * @li <b>1</b> - enable |
| 989 | */ |
| 990 | unsigned int UsbRxMode:1; |
| 991 | unsigned int DebugOption2Dummy3:9; // |
| 992 | |
| 993 | union |
| 994 | { |
| 995 | PLACEHOLDER DynamicGecRomAddressPtr; //offset 4 bytes (182-185) |
| 996 | void *DynamicGecRomAddress_Ptr; |
| 997 | } DYNAMICGECROM; |
| 998 | EC_struct Pecstruct; |
| 999 | } AMDSBCFG; |
| 1000 | |
| 1001 | /** SMMSERVICESTRUC- Southbridge SMI service structure */ |
| 1002 | typedef struct _SMMSERVICESTRUC { |
| 1003 | /** enableRegNum - Reserved */ |
| 1004 | unsigned char enableRegNum; |
| 1005 | /** enableBit - Reserved */ |
| 1006 | unsigned char enableBit; |
| 1007 | /** statusRegNum - Reserved */ |
| 1008 | unsigned char statusRegNum; |
| 1009 | /** statusBit - Reserved */ |
| 1010 | unsigned char statusBit; |
| 1011 | /** *debugMessage- Reserved */ |
| 1012 | signed char *debugMessage; |
| 1013 | /** serviceRoutine - Reserved */ |
| 1014 | SMM_SERVICE_ROUTINE serviceRoutine; |
| 1015 | } SMMSERVICESTRUC; |
| 1016 | |
| 1017 | #ifndef _NB_REG8MASK_ |
| 1018 | |
| 1019 | /** |
| 1020 | * - Byte Register R/W structure |
| 1021 | * |
| 1022 | */ |
| 1023 | typedef struct _Reg8Mask { |
| 1024 | /** bRegIndex - Reserved */ |
| 1025 | unsigned char bRegIndex; |
| 1026 | /** bANDMask - Reserved */ |
| 1027 | unsigned char bANDMask; |
| 1028 | /** bORMask - Reserved */ |
| 1029 | unsigned char bORMask; |
| 1030 | } REG8MASK; |
| 1031 | #endif |
| 1032 | |
| 1033 | /** |
| 1034 | * - SATA Phy setting structure |
| 1035 | * |
| 1036 | */ |
| 1037 | typedef struct _SATAPHYSETTING { |
| 1038 | /** wPhyCoreControl - Reserved */ |
| 1039 | unsigned short wPhyCoreControl; |
| 1040 | /** dwPhyFineTune - Reserved */ |
| 1041 | unsigned int dwPhyFineTune; |
| 1042 | } SATAPHYSETTING; |
| 1043 | |
| 1044 | /** |
| 1045 | * _ABTblEntry - AB link register table R/W structure |
| 1046 | * |
| 1047 | */ |
| 1048 | typedef struct _ABTblEntry { |
| 1049 | /** regType : AB Register Type (ABCFG, AXCFG and so on) */ |
| 1050 | unsigned char regType; |
| 1051 | /** regIndex : AB Register Index */ |
| 1052 | unsigned int regIndex; |
| 1053 | /** regMask : AB Register Mask */ |
| 1054 | unsigned int regMask; |
| 1055 | /** regData : AB Register Data */ |
| 1056 | unsigned int regData; |
| 1057 | } ABTBLENTRY; |
| 1058 | |
| 1059 | /** |
| 1060 | * _AcpiRegWrite - ACPI MMIO register R/W structure |
| 1061 | * |
| 1062 | */ |
| 1063 | typedef struct _AcpiRegWrite { |
| 1064 | /** MmioBase : Index of Soubridge block (For instence GPIO_BASE:0x01 SMI_BASE:0x02) */ |
| 1065 | unsigned char MmioBase; |
| 1066 | /** MmioReg : Register index */ |
| 1067 | unsigned char MmioReg; |
| 1068 | /** DataANDMask : AND Register Data */ |
| 1069 | unsigned char DataANDMask; |
| 1070 | /** DataOrMask : Or Register Data */ |
| 1071 | unsigned char DataOrMask; |
| 1072 | } AcpiRegWrite; |
| 1073 | |
| 1074 | /** |
| 1075 | * PCI_ADDRESS - PCI access structure |
| 1076 | * |
| 1077 | */ |
| 1078 | #define PCI_ADDRESS(bus, dev, func, reg) \ |
| 1079 | (unsigned int) ( (((unsigned int)bus) << 24) + (((unsigned int)dev) << 19) + (((unsigned int)func) << 16) + ((unsigned int)reg) ) |
| 1080 | |
| 1081 | /** |
| 1082 | * CIM_STATUS - CIMx module function return code |
| 1083 | */ |
| 1084 | typedef unsigned int CIM_STATUS; |
| 1085 | /** |
| 1086 | * CIM_SUCCESS - Executed without error |
| 1087 | */ |
| 1088 | #define CIM_SUCCESS 0x00000000 |
| 1089 | /** |
| 1090 | * CIM_ERROR - call error |
| 1091 | */ |
| 1092 | #define CIM_ERROR 0x80000000 |
| 1093 | /** |
| 1094 | * CIM_UNSUPPORTED - function does not support |
| 1095 | */ |
| 1096 | #define CIM_UNSUPPORTED 0x80000001 |
| 1097 | |
| 1098 | #pragma pack (pop) |
| 1099 | |
| 1100 | /** |
Kerry She | 991f880 | 2011-06-01 01:56:49 +0000 | [diff] [blame] | 1101 | * CIMX_OPTION_DISABLED - Define disable in module |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 1102 | */ |
Kerry She | 991f880 | 2011-06-01 01:56:49 +0000 | [diff] [blame] | 1103 | #define CIMX_OPTION_DISABLED 0 |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 1104 | /** |
Kerry She | 991f880 | 2011-06-01 01:56:49 +0000 | [diff] [blame] | 1105 | * CIMX_OPTION_ENABLED - Define enable in module |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 1106 | */ |
Kerry She | 991f880 | 2011-06-01 01:56:49 +0000 | [diff] [blame] | 1107 | #define CIMX_OPTION_ENABLED 1 |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 1108 | |
Kerry Sheh | 4e9c4c8 | 2011-10-10 18:23:49 +0800 | [diff] [blame] | 1109 | /** |
| 1110 | * SATA_IDE_COMBINE_ENABLE -Define Enable Combined Mode |
| 1111 | */ |
| 1112 | #define SATA_IDE_COMBINE_ENABLE 0 |
| 1113 | |
| 1114 | /** |
| 1115 | * SATA_IDE_COMBINE_DISABLE -Define Disable Combined Mode |
| 1116 | */ |
| 1117 | #define SATA_IDE_COMBINE_DISABLE 1 |
| 1118 | |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 1119 | // mov al, code |
| 1120 | // out 80h, al |
| 1121 | // jmp $ |
| 1122 | |
| 1123 | /** |
| 1124 | * DBG_STOP - define a debug point |
| 1125 | */ |
| 1126 | #define DBG_STOP __asm _emit 0xEB __asm _emit 0xFE |
| 1127 | |
| 1128 | /** |
| 1129 | * STOP_CODE - define a debug point |
| 1130 | * Warning: AL gets destroyed! |
| 1131 | */ |
| 1132 | #define STOP_CODE (code) __asm __emit 0xB0 __asm __emit code __asm __emit 0xE6 \ |
| 1133 | __asm __emit 0x80 __asm _emit 0xEB __asm _emit 0xFE |
| 1134 | |
| 1135 | #endif // _AMD_SBTYPE_H_ |