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review.coreboot.org / coreboot / 2b4c831b4d16b55a7abdea20bce82cccd168232c / . / src / vendorcode / amd / cimx / sb800 / SBTYPE.h
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Frank Vibrans2b4c8312011-02-14 18:30:54 +0000[diff] [blame^]1
2/**
3 * @file
4 *
5 * Southbridge CIMx configuration structure define
6 *
7 *
8 *
9 * @xrefitem bom "File Content Label" "Release Content"
10 * @e project: CIMx-SB
11 * @e sub-project:
12 * @e \$Revision:$ @e \$Date:$
13 *
14 */
15/*
16 *****************************************************************************
17 *
18 * Copyright (c) 2011, Advanced Micro Devices, Inc.
19 * All rights reserved.
20 *
21 * Redistribution and use in source and binary forms, with or without
22 * modification, are permitted provided that the following conditions are met:
23 * * Redistributions of source code must retain the above copyright
24 * notice, this list of conditions and the following disclaimer.
25 * * Redistributions in binary form must reproduce the above copyright
26 * notice, this list of conditions and the following disclaimer in the
27 * documentation and/or other materials provided with the distribution.
28 * * Neither the name of Advanced Micro Devices, Inc. nor the names of
29 * its contributors may be used to endorse or promote products derived
30 * from this software without specific prior written permission.
31 *
32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
33 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
34 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
35 * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
36 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
37 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
38 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
39 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
41 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42 *
43 * ***************************************************************************
44 *
45 */
46
47#ifndef _AMD_SBTYPE_H_
48#define _AMD_SBTYPE_H_
49
50#pragma pack (push, 1)
51
52/**
53 * Entry point of Southbridge CIMx
54 *
55 *
56 * @param[in] Param1 Southbridge CIMx Function ID.
57 * @param[in] Param2 Southbridge Input Data.
58 * @param[in] pConfig Southbridge configuration structure pointer.
59 *
60 */
61typedef unsigned int (*SBCIM_HOOK_ENTRY) (unsigned int Param1, unsigned int Param2, void* pConfig);
62/**
63 * SMM_SERVICE_ROUTINE - Southbridge SMI service routine
64 *
65 */
66typedef void (*SMM_SERVICE_ROUTINE) (void);
67
68
69/**
70 * The STATIC platform information for CIMx Module.
71 *
72 */
73typedef struct _BUILDPARAM {
74 unsigned int BiosSize:3; /**< BiosSize
75 * @par
76 * BIOSSize [2.0] - BIOS Image Size
77 * @li <b>0</b> - 1M
78 * @li <b>1</b> - 2M
79 * @li <b>3</b> - 4M
80 * @li <b>7</b> - 8M
81 * In SB800, default ROM size is 1M Bytes, if your platform ROM bigger then 1M
82 * you have to set the ROM size outside CIMx module and before AGESA module get call
83 *
84 */
85 unsigned int LegacyFree:1; /**< LegacyFree
86 * @par
87 * Config Southbridge CIMx module for Legacy Free Mode
88 */
89 unsigned int SpiSpeed:2; /**< SpiSpeed
90 * @par
91 * SPI Speed [1.0] - the clock speed for non-fast read command
92 * @li <b>00</b> - 66Mhz
93 * @li <b>01</b> - 33Mhz
94 * @li <b>10</b> - 22Mhz
95 * @li <b>11</b> - 16.5Mhz
96 *
97 */
98 unsigned int ImcEnableOverWrite:2; /**< ImcEnableOverWrite
99 * @par
100 * Imc Enable OverWrite
101 * @li <b>00</b> - by default strapping
102 * @li <b>01</b> - On
103 * @li <b>10</b> - Off
104 *
105 */
106 unsigned int SpiFastReadEnable:1; /**< SpiFastReadEnable
107 * @par
108 * @li <b>00</b> - Disable SPI Fast Read Function
109 * @li <b>01</b> - Enable SPI Fast Read Function
110 */
111 unsigned int SpiFastReadSpeed:2; /**< SpiFastReadSpeed
112 * @par
113 * @li <b>00</b> - 66Mhz
114 * @li <b>01</b> - 33Mhz
115 * @li <b>10</b> - 22Mhz
116 * @li <b>11</b> - 16.5Mhz
117 */
118 unsigned int SpreadSpectrumType:1; /**< SpreadSpectrumType
119 * @par
120 * @li <b>0</b> - Spread Spectrum for normal platform
121 * @li <b>1</b> - Spread Spectrum for Ontario platform
122 */
123/** Dummy0 - Reserved */
124 unsigned int Dummy0:4;
125 unsigned int EcKbd:1; /**< EcKbd
126 * @par
127 * EcKbd [16] - Platform use EC (as SIO) or SIO chip for PS/2 Keyboard and Mouse
128 * @li <b>0</b> - Use SIO PS/2 function.
129 * @li <b>1</b> - Use EC PS/2 function instead of SIO PS/2 function. **
130 * @li <b>**</b> When set 1, EC function have to enable, otherwise, CIMx treat as legacy-free system.
131 */
132/** EcChannel0 - Reserved */
133 unsigned int EcChannel0:1;
134/** UsbMsi - Reserved */
135 unsigned int UsbMsi:1;
136/** HdAudioMsi - Reserved */
137 unsigned int HdAudioMsi:1;
138/** LpcMsi - Reserved */
139 unsigned int LpcMsi:1;
140/** PcibMsi - Reserved */
141 unsigned int PcibMsi:1;
142/** AbMsi - Reserved */
143 unsigned int AbMsi:1;
144/** Dummy1 - Reserved */
145 unsigned int Dummy1:9;
146
147 unsigned int Smbus0BaseAddress; /**< Smbus0BaseAddress
148 * @par
149 * Smbus BASE Address
150 */
151 unsigned int Smbus1BaseAddress; /**< Smbus1BaseAddress
152 * @par
153 * Smbus1 (ASF) BASE Address
154 */
155 unsigned int SioPmeBaseAddress; /**< SioPmeBaseAddress
156 * @par
157 * SIO PME BASE Address
158 */
159 unsigned int WatchDogTimerBase; /**< WatchDogTimerBase
160 * @par
161 * Watch Dog Timer Address
162 */
163 unsigned int GecShadowRomBase; /**< GecShadowRomBase
164 * @par
165 * GEC (NIC) SHADOWROM BASE Address
166 */
167 unsigned int SpiRomBaseAddress; /**< SpiRomBaseAddress
168 * @par
169 * SPI ROM BASE Address
170 */
171 unsigned short AcpiPm1EvtBlkAddr; /**< AcpiPm1EvtBlkAddr
172 * @par
173 * ACPI PM1 event block Address
174 */
175 unsigned short AcpiPm1CntBlkAddr; /**< AcpiPm1CntBlkAddr
176 * @par
177 * ACPI PM1 Control block Address
178 */
179 unsigned short AcpiPmTmrBlkAddr; /**< AcpiPmTmrBlkAddr
180 * @par
181 * ACPI PM timer block Address
182 */
183 unsigned short CpuControlBlkAddr; /**< CpuControlBlkAddr
184 * @par
185 * ACPI CPU control block Address
186 */
187 unsigned short AcpiGpe0BlkAddr; /**< AcpiGpe0BlkAddr
188 * @par
189 * ACPI GPE0 block Address
190 */
191 unsigned short SmiCmdPortAddr; /**< SmiCmdPortAddr
192 * @par
193 * SMI command port Address
194 */
195 unsigned short AcpiPmaCntBlkAddr; /**< AcpiPmaCntBlkAddr
196 * @par
197 * ACPI PMA Control block Address
198 */
199 unsigned int HpetBase; /**< HpetBase
200 * @par
201 * HPET Base address
202 */
203 unsigned int SataIDESsid; /**< SataIDESsid
204 * @par
205 * SATA IDE mode SSID
206 */
207 unsigned int SataRAIDSsid; /**< SataRAIDSsid
208 * @par
209 * SATA RAID mode SSID
210 */
211 unsigned int SataRAID5Ssid; /**< SataRAID5Ssid
212 * @par
213 * SATA RAID5 mode SSID
214 */
215 unsigned int SataAHCISsid; /**< SataAHCISsid
216 * @par
217 * SATA AHCI mode SSID
218 */
219 unsigned int OhciSsid; /**< OhciSsid
220 * @par
221 * OHCI Controller SSID
222 */
223 unsigned int EhciSsid; /**< EhciSsid
224 * @par
225 * EHCI Controller SSID
226 */
227 unsigned int Ohci4Ssid; /**< Ohci4Ssid
228 * @par
229 * OHCI4 Controller SSID (Force USB 1.1 mode)
230 */
231 unsigned int SmbusSsid; /**< SmbusSsid
232 * @par
233 * SMBUS controller SSID
234 */
235 unsigned int IdeSsid; /**< IdeSsid
236 * @par
237 * IDE (Sata) controller SSID
238 */
239 unsigned int AzaliaSsid; /**< AzaliaSsid
240 * @par
241 * HD Audio controller SSID
242 */
243 unsigned int LpcSsid; /**< LpcSsid
244 * @par
245 * LPC controller SSID
246 */
247 unsigned int PCIBSsid; /**< PCIBSsid
248 * @par
249 * PCIB controller SSID
250 */
251} BUILDPARAM;
252
253/**
254 * The EC fan MSGREG struct for CIMx Module. *
255 */
256typedef struct _EC_struct {
257 unsigned char MSGFun81zone0MSGREG0; ///<Thermal zone
258 unsigned char MSGFun81zone0MSGREG1; ///<Thermal zone
259 unsigned char MSGFun81zone0MSGREG2; ///<Thermal zone control byte 1
260 unsigned char MSGFun81zone0MSGREG3; ///<Thermal zone control byte 2
261 unsigned char MSGFun81zone0MSGREG4; ///<Bit[3:0] - Thermal diode offset adjustment in degrees Celsius.
262 unsigned char MSGFun81zone0MSGREG5; ///<Hysteresis inforamtion
263 unsigned char MSGFun81zone0MSGREG6; ///<SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032
264 unsigned char MSGFun81zone0MSGREG7; ///<Bit[1:0]: 0 - 2, SMBUS bus number where the SMBUS based temperature sensor is located.
265 unsigned char MSGFun81zone0MSGREG8; ///< @todo Style_Analyzer: Add Doxygen comments to struct entry
266 unsigned char MSGFun81zone0MSGREG9; ///< @todo Style_Analyzer: Add Doxygen comments to struct entry
267
268 //EC LDN9 funtion 81 zone 1
269 unsigned char MSGFun81zone1MSGREG0; ///<Thermal zone
270 unsigned char MSGFun81zone1MSGREG1; ///<Thermal zone
271 unsigned char MSGFun81zone1MSGREG2; ///<Thermal zone control byte 1
272 unsigned char MSGFun81zone1MSGREG3; ///<Thermal zone control byte 2
273 unsigned char MSGFun81zone1MSGREG4; ///<Bit[3:0] - Thermal diode offset adjustment in degrees Celsius.
274 unsigned char MSGFun81zone1MSGREG5; ///<Hysteresis inforamtion
275 unsigned char MSGFun81zone1MSGREG6; ///<SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032
276 unsigned char MSGFun81zone1MSGREG7; ///<Bit[1:0]: 0 - 2, SMBUS bus number where the SMBUS based temperature sensor is located.
277 unsigned char MSGFun81zone1MSGREG8; ///< @todo Style_Analyzer: Add Doxygen comments to struct entry
278 unsigned char MSGFun81zone1MSGREG9; ///< @todo Style_Analyzer: Add Doxygen comments to struct entry
279
280 //EC LDN9 funtion 81 zone 2
281 unsigned char MSGFun81zone2MSGREG0; ///<Thermal zone
282 unsigned char MSGFun81zone2MSGREG1; ///<Thermal zone
283 unsigned char MSGFun81zone2MSGREG2; ///<Thermal zone control byte 1
284 unsigned char MSGFun81zone2MSGREG3; ///<Thermal zone control byte 2
285 unsigned char MSGFun81zone2MSGREG4; ///<Bit[3:0] - Thermal diode offset adjustment in degrees Celsius.
286 unsigned char MSGFun81zone2MSGREG5; ///<Hysteresis inforamtion
287 unsigned char MSGFun81zone2MSGREG6; ///<SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032
288 unsigned char MSGFun81zone2MSGREG7; ///<Bit[1:0]: 0 - 2, SMBUS bus number where the SMBUS based temperature sensor is located.
289 unsigned char MSGFun81zone2MSGREG8; ///< @todo Style_Analyzer: Add Doxygen comments to struct entry
290 unsigned char MSGFun81zone2MSGREG9; ///< @todo Style_Analyzer: Add Doxygen comments to struct entry
291
292 //EC LDN9 funtion 81 zone 3
293 unsigned char MSGFun81zone3MSGREG0; ///<Thermal zone
294 unsigned char MSGFun81zone3MSGREG1; ///<Thermal zone
295 unsigned char MSGFun81zone3MSGREG2; ///<Thermal zone control byte 1
296 unsigned char MSGFun81zone3MSGREG3; ///<Thermal zone control byte 2
297 unsigned char MSGFun81zone3MSGREG4; ///<Bit[3:0] - Thermal diode offset adjustment in degrees Celsius.
298 unsigned char MSGFun81zone3MSGREG5; ///<Hysteresis inforamtion
299 unsigned char MSGFun81zone3MSGREG6; ///<SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032
300 unsigned char MSGFun81zone3MSGREG7; ///<Bit[1:0]: 0 - 2, SMBUS bus number where the SMBUS based temperature sensor is located.
301 unsigned char MSGFun81zone3MSGREG8; ///< @todo Style_Analyzer: Add Doxygen comments to struct entry
302 unsigned char MSGFun81zone3MSGREG9; ///< @todo Style_Analyzer: Add Doxygen comments to struct entry
303
304 //EC LDN9 funtion 83 zone 0
305 unsigned char MSGFun83zone0MSGREG0; ///<Thermal zone
306 unsigned char MSGFun83zone0MSGREG1; ///<Thermal zone
307 unsigned char MSGFun83zone0MSGREG2; ///<_AC0
308 unsigned char MSGFun83zone0MSGREG3; ///<_AC1
309 unsigned char MSGFun83zone0MSGREG4; ///<_AC2
310 unsigned char MSGFun83zone0MSGREG5; ///<_AC3
311 unsigned char MSGFun83zone0MSGREG6; ///<_AC4
312 unsigned char MSGFun83zone0MSGREG7; ///<_AC5
313 unsigned char MSGFun83zone0MSGREG8; ///<_AC6
314 unsigned char MSGFun83zone0MSGREG9; ///<_AC7
315 unsigned char MSGFun83zone0MSGREGA; ///<_CRT
316 unsigned char MSGFun83zone0MSGREGB; ///<_PSV
317
318 //EC LDN9 funtion 83 zone 1
319 unsigned char MSGFun83zone1MSGREG0; ///<Thermal zone
320 unsigned char MSGFun83zone1MSGREG1; ///<Thermal zone
321 unsigned char MSGFun83zone1MSGREG2; ///<_AC0
322 unsigned char MSGFun83zone1MSGREG3; ///<_AC1
323 unsigned char MSGFun83zone1MSGREG4; ///<_AC2
324 unsigned char MSGFun83zone1MSGREG5; ///<_AC3
325 unsigned char MSGFun83zone1MSGREG6; ///<_AC4
326 unsigned char MSGFun83zone1MSGREG7; ///<_AC5
327 unsigned char MSGFun83zone1MSGREG8; ///<_AC6
328 unsigned char MSGFun83zone1MSGREG9; ///<_AC7
329 unsigned char MSGFun83zone1MSGREGA; ///<_CRT
330 unsigned char MSGFun83zone1MSGREGB; ///<_PSV
331
332 //EC LDN9 funtion 83 zone 2
333 unsigned char MSGFun83zone2MSGREG0; ///<Thermal zone
334 unsigned char MSGFun83zone2MSGREG1; ///<Thermal zone
335 unsigned char MSGFun83zone2MSGREG2; ///<_AC0
336 unsigned char MSGFun83zone2MSGREG3; ///<_AC1
337 unsigned char MSGFun83zone2MSGREG4; ///<_AC2
338 unsigned char MSGFun83zone2MSGREG5; ///<_AC3
339 unsigned char MSGFun83zone2MSGREG6; ///<_AC4
340 unsigned char MSGFun83zone2MSGREG7; ///<_AC5
341 unsigned char MSGFun83zone2MSGREG8; ///<_AC6
342 unsigned char MSGFun83zone2MSGREG9; ///<_AC7
343 unsigned char MSGFun83zone2MSGREGA; ///<_CRT
344 unsigned char MSGFun83zone2MSGREGB; ///<_PSV
345
346 //EC LDN9 funtion 83 zone 3
347 unsigned char MSGFun83zone3MSGREG0; ///<Thermal zone
348 unsigned char MSGFun83zone3MSGREG1; ///<Thermal zone
349 unsigned char MSGFun83zone3MSGREG2; ///<_AC0
350 unsigned char MSGFun83zone3MSGREG3; ///<_AC1
351 unsigned char MSGFun83zone3MSGREG4; ///<_AC2
352 unsigned char MSGFun83zone3MSGREG5; ///<_AC3
353 unsigned char MSGFun83zone3MSGREG6; ///<_AC4
354 unsigned char MSGFun83zone3MSGREG7; ///<_AC5
355 unsigned char MSGFun83zone3MSGREG8; ///<_AC6
356 unsigned char MSGFun83zone3MSGREG9; ///<_AC7
357 unsigned char MSGFun83zone3MSGREGA; ///<_CRT
358 unsigned char MSGFun83zone3MSGREGB; ///<_PSV
359
360 //EC LDN9 funtion 85 zone 0
361 unsigned char MSGFun85zone0MSGREG0; ///<Thermal zone
362 unsigned char MSGFun85zone0MSGREG1; ///<Thermal zone
363 unsigned char MSGFun85zone0MSGREG2; ///<AL0 PWM level in percentage (0 - 100%)
364 unsigned char MSGFun85zone0MSGREG3; ///<AL1 PWM level in percentage (0 - 100%)
365 unsigned char MSGFun85zone0MSGREG4; ///<AL2 PWM level in percentage (0 - 100%)
366 unsigned char MSGFun85zone0MSGREG5; ///<AL3 PWM level in percentage (0 - 100%)
367 unsigned char MSGFun85zone0MSGREG6; ///<AL4 PWM level in percentage (0 - 100%)
368 unsigned char MSGFun85zone0MSGREG7; ///<AL5 PWM level in percentage (0 - 100%)
369 unsigned char MSGFun85zone0MSGREG8; ///<AL6 PWM level in percentage (0 - 100%)
370 unsigned char MSGFun85zone0MSGREG9; ///<AL7 PWM level in percentage (0 - 100%)
371
372 //EC LDN9 funtion 85 zone 1
373 unsigned char MSGFun85zone1MSGREG0; ///<Thermal zone
374 unsigned char MSGFun85zone1MSGREG1; ///<Thermal zone
375 unsigned char MSGFun85zone1MSGREG2; ///<AL0 PWM level in percentage (0 - 100%)
376 unsigned char MSGFun85zone1MSGREG3; ///<AL1 PWM level in percentage (0 - 100%)
377 unsigned char MSGFun85zone1MSGREG4; ///<AL2 PWM level in percentage (0 - 100%)
378 unsigned char MSGFun85zone1MSGREG5; ///<AL3 PWM level in percentage (0 - 100%)
379 unsigned char MSGFun85zone1MSGREG6; ///<AL4 PWM level in percentage (0 - 100%)
380 unsigned char MSGFun85zone1MSGREG7; ///<AL5 PWM level in percentage (0 - 100%)
381 unsigned char MSGFun85zone1MSGREG8; ///<AL6 PWM level in percentage (0 - 100%)
382 unsigned char MSGFun85zone1MSGREG9; ///<AL7 PWM level in percentage (0 - 100%)
383
384 //EC LDN9 funtion 85 zone 2
385 unsigned char MSGFun85zone2MSGREG0; ///<Thermal zone
386 unsigned char MSGFun85zone2MSGREG1; ///<Thermal zone
387 unsigned char MSGFun85zone2MSGREG2; ///<AL0 PWM level in percentage (0 - 100%)
388 unsigned char MSGFun85zone2MSGREG3; ///<AL1 PWM level in percentage (0 - 100%)
389 unsigned char MSGFun85zone2MSGREG4; ///<AL2 PWM level in percentage (0 - 100%)
390 unsigned char MSGFun85zone2MSGREG5; ///<AL3 PWM level in percentage (0 - 100%)
391 unsigned char MSGFun85zone2MSGREG6; ///<AL4 PWM level in percentage (0 - 100%)
392 unsigned char MSGFun85zone2MSGREG7; ///<AL5 PWM level in percentage (0 - 100%)
393 unsigned char MSGFun85zone2MSGREG8; ///<AL6 PWM level in percentage (0 - 100%)
394 unsigned char MSGFun85zone2MSGREG9; ///<AL7 PWM level in percentage (0 - 100%)
395
396 //EC LDN9 funtion 85 zone 3
397 unsigned char MSGFun85zone3MSGREG0; ///<Thermal zone
398 unsigned char MSGFun85zone3MSGREG1; ///<Thermal zone
399 unsigned char MSGFun85zone3MSGREG2; ///<AL0 PWM level in percentage (0 - 100%)
400 unsigned char MSGFun85zone3MSGREG3; ///<AL1 PWM level in percentage (0 - 100%)
401 unsigned char MSGFun85zone3MSGREG4; ///<AL2 PWM level in percentage (0 - 100%)
402 unsigned char MSGFun85zone3MSGREG5; ///<AL3 PWM level in percentage (0 - 100%)
403 unsigned char MSGFun85zone3MSGREG6; ///<AL4 PWM level in percentage (0 - 100%)
404 unsigned char MSGFun85zone3MSGREG7; ///<AL5 PWM level in percentage (0 - 100%)
405 unsigned char MSGFun85zone3MSGREG8; ///<AL6 PWM level in percentage (0 - 100%)
406 unsigned char MSGFun85zone3MSGREG9; ///<AL7 PWM level in percentage (0 - 100%)
407
408 //EC LDN9 funtion 89 TEMPIN channel 0
409 unsigned char MSGFun89zone0MSGREG0; ///<Thermal zone
410 unsigned char MSGFun89zone0MSGREG1; ///<Thermal zone
411 unsigned char MSGFun89zone0MSGREG2; ///<At DWORD bit 0-7
412 unsigned char MSGFun89zone0MSGREG3; ///<At DWORD bit 15-8
413 unsigned char MSGFun89zone0MSGREG4; ///<At DWORD bit 23-16
414 unsigned char MSGFun89zone0MSGREG5; ///<At DWORD bit 31-24
415 unsigned char MSGFun89zone0MSGREG6; ///<Ct DWORD bit 0-7
416 unsigned char MSGFun89zone0MSGREG7; ///<Ct DWORD bit 15-8
417 unsigned char MSGFun89zone0MSGREG8; ///<Ct DWORD bit 23-16
418 unsigned char MSGFun89zone0MSGREG9; ///<Ct DWORD bit 31-24
419 unsigned char MSGFun89zone0MSGREGA; ///<Mode bit 0-7
420
421 //EC LDN9 funtion 89 TEMPIN channel 1
422 unsigned char MSGFun89zone1MSGREG0; ///<Thermal zone
423 unsigned char MSGFun89zone1MSGREG1; ///<Thermal zone
424 unsigned char MSGFun89zone1MSGREG2; ///<At DWORD bit 0-7
425 unsigned char MSGFun89zone1MSGREG3; ///<At DWORD bit 15-8
426 unsigned char MSGFun89zone1MSGREG4; ///<At DWORD bit 23-16
427 unsigned char MSGFun89zone1MSGREG5; ///<At DWORD bit 31-24
428 unsigned char MSGFun89zone1MSGREG6; ///<Ct DWORD bit 0-7
429 unsigned char MSGFun89zone1MSGREG7; ///<Ct DWORD bit 15-8
430 unsigned char MSGFun89zone1MSGREG8; ///<Ct DWORD bit 23-16
431 unsigned char MSGFun89zone1MSGREG9; ///<Ct DWORD bit 31-24
432 unsigned char MSGFun89zone1MSGREGA; ///<Mode bit 0-7
433
434 //EC LDN9 funtion 89 TEMPIN channel 2
435 unsigned char MSGFun89zone2MSGREG0; ///<Thermal zone
436 unsigned char MSGFun89zone2MSGREG1; ///<Thermal zone
437 unsigned char MSGFun89zone2MSGREG2; ///<At DWORD bit 0-7
438 unsigned char MSGFun89zone2MSGREG3; ///<At DWORD bit 15-8
439 unsigned char MSGFun89zone2MSGREG4; ///<At DWORD bit 23-16
440 unsigned char MSGFun89zone2MSGREG5; ///<At DWORD bit 31-24
441 unsigned char MSGFun89zone2MSGREG6; ///<Ct DWORD bit 0-7
442 unsigned char MSGFun89zone2MSGREG7; ///<Ct DWORD bit 15-8
443 unsigned char MSGFun89zone2MSGREG8; ///<Ct DWORD bit 23-16
444 unsigned char MSGFun89zone2MSGREG9; ///<Ct DWORD bit 31-24
445 unsigned char MSGFun89zone2MSGREGA; ///<Mode bit 0-7
446
447 //EC LDN9 funtion 89 TEMPIN channel 3
448 unsigned char MSGFun89zone3MSGREG0; ///<Thermal zone
449 unsigned char MSGFun89zone3MSGREG1; ///<Thermal zone
450 unsigned char MSGFun89zone3MSGREG2; ///<At DWORD bit 0-7
451 unsigned char MSGFun89zone3MSGREG3; ///<At DWORD bit 15-8
452 unsigned char MSGFun89zone3MSGREG4; ///<At DWORD bit 23-16
453 unsigned char MSGFun89zone3MSGREG5; ///<At DWORD bit 31-24
454 unsigned char MSGFun89zone3MSGREG6; ///<Ct DWORD bit 0-7
455 unsigned char MSGFun89zone3MSGREG7; ///<Ct DWORD bit 15-8
456 unsigned char MSGFun89zone3MSGREG8; ///<Ct DWORD bit 23-16
457 unsigned char MSGFun89zone3MSGREG9; ///<Ct DWORD bit 31-24
458 unsigned char MSGFun89zone3MSGREGA; ///<Mode bit 0-7
459
460 // FLAG for Fun83/85/89 support
461 unsigned short IMCFUNSupportBitMap; /// Bit0=81FunZone0 support(1=On;0=Off); bit1-3=81FunZone1-Zone3;Bit4-7=83FunZone0-Zone3;Bit8-11=85FunZone0-Zone3;Bit11-15=89FunZone0-Zone3;
462} EC_struct;
463/** SBGPPPORTCONFIG - Southbridge GPP port config structure */
464typedef struct {
465 unsigned int PortPresent:1; /**< Port connection
466 * @par
467 * @li <b>0</b> - Port doesn't have slot. No need to train the link
468 * @li <b>1</b> - Port connection defined and needs to be trained
469 */
470 unsigned int PortDetected:1; /**< Link training status
471 * @par
472 * @li <b>0</b> - EP not detected
473 * @li <b>1</b> - EP detected
474 */
475 unsigned int PortIsGen2:2; /**< Port link speed configuration
476 * @par
477 * @li <b>00</b> - Auto
478 * @li <b>01</b> - Forced GEN1
479 * @li <b>10</b> - Forced GEN2
480 * @li <b>11</b> - Reserved
481 */
482
483 unsigned int PortHotPlug:1; /**< Support hot plug?
484 * @par
485 * @li <b>0</b> - No support
486 * @li <b>1</b> - support
487 */
488/** PortMisc - Reserved */
489 unsigned int PortMisc:27;
490} SBGPPPORTCONFIG;
491
492/** CODECENTRY - Southbridge HD Audio OEM Codec structure */
493typedef struct _CODECENTRY {
494/** Nid - Reserved ?? */
495 unsigned char Nid;
496/** Byte40 - Reserved ?? */
497 unsigned int Byte40;
498} CODECENTRY;
499
500/** CODECTBLLIST - Southbridge HD Audio Codec table list */
501typedef struct _CODECTBLLIST {
502/** CodecID - Codec ID */
503 unsigned int CodecID;
504/** CodecTablePtr - Codec table pointer */
505 CODECENTRY* CodecTablePtr;
506} CODECTBLLIST;
507
508/** Sata Controller structure */
509typedef struct _SATAST {
510 unsigned char SataController:1; /**< SataController
511 * @par
512 * Sata Controller
513 * @li <b>0</b> - disable
514 * @li <b>1</b> - enable
515 */
516 unsigned char SataIdeCombMdPriSecOpt:1; /**< SataIdeCombMdPriSecOpt - Reserved */
517 unsigned char SataSetMaxGen2:1; /**< SataSetMaxGen2
518 * @par
519 * Sata Controller Set to Max Gen2 mode
520 * @li <b>0</b> - disable
521 * @li <b>1</b> - enable
522 */
523 unsigned char SataIdeCombinedMode:1; /**< SataIdeCombinedMode
524 * @par
525 * Sata IDE Controller set to Combined Mode
526 * @li <b>0</b> - enable
527 * @li <b>1</b> - disable
528 */
529/** SATARefClkSel - Reserved */
530 unsigned char SATARefClkSel:2; // 4:5
531/** SATARefDivSel - Reserved */
532 unsigned char SATARefDivSel:2; // 6:7
533} SATAST;
534
535/** _USBST Controller structure
536 *
537 * Usb Ohci1 Contoller is define at BIT0
538 * - 0:disable 1:enable
539 * (Bus 0 Dev 18 Func0) *
540 * Usb Ehci1 Contoller is define at BIT1
541 * - 0:disable 1:enable
542 * (Bus 0 Dev 18 Func2) *
543 * Usb Ohci2 Contoller is define at BIT2
544 * - 0:disable 1:enable
545 * (Bus 0 Dev 19 Func0) *
546 * Usb Ehci2 Contoller is define at BIT3
547 * - 0:disable 1:enable
548 * (Bus 0 Dev 19 Func2) *
549 * Usb Ohci3 Contoller is define at BIT4
550 * - 0:disable 1:enable
551 * (Bus 0 Dev 22 Func0) *
552 * Usb Ehci3 Contoller is define at BIT5
553 * - 0:disable 1:enable
554 * (Bus 0 Dev 22 Func2) *
555 * Usb Ohci4 Contoller is define at BIT6
556 * - 0:disable 1:enable
557 * (Bus 0 Dev 20 Func5) *
558 */
559typedef struct _USBST {
560 unsigned char Ohci1:1; ///< Ohci0 controller - 0:disable, 1:enable
561 unsigned char Ehci1:1; ///< Ehci1 controller - 0:disable, 1:enable
562 unsigned char Ohci2:1; ///< Ohci2 controller - 0:disable, 1:enable
563 unsigned char Ehci2:1; ///< Ehci2 controller - 0:disable, 1:enable
564 unsigned char Ohci3:1; ///< Ohci3 controller - 0:disable, 1:enable
565 unsigned char Ehci3:1; ///< Ehci3 controller - 0:disable, 1:enable
566 unsigned char Ohci4:1; ///< Ohci4 controller - 0:disable, 1:enable
567 unsigned char UTemp:1; ///< Reserved
568} USBST;
569
570/**
571 * _AZALIAPIN - HID Azalia or GPIO define structure.
572 *
573 */
574typedef struct _AZALIAPIN {
575 unsigned char AzaliaSdin0:2; /**< AzaliaSdin0
576 * @par
577 * SDIN0 is define at BIT0 & BIT1
578 * @li <b>00</b> - GPIO PIN
579 * @li <b>10</b> - As a Azalia SDIN pin
580 */
581 unsigned char AzaliaSdin1:2; /**< AzaliaSdin1
582 * @par
583 * SDIN0 is define at BIT2 & BIT3
584 * @li <b>00</b> - GPIO PIN
585 * @li <b>10</b> - As a Azalia SDIN pin
586 */
587 unsigned char AzaliaSdin2:2; /**< AzaliaSdin2
588 * @par
589 * SDIN0 is define at BIT4 & BIT5
590 * @li <b>00</b> - GPIO PIN
591 * @li <b>10</b> - As a Azalia SDIN pin
592 */
593 unsigned char AzaliaSdin3:2; /**< AzaliaSdin3
594 * @par
595 * SDIN0 is define at BIT6 & BIT7
596 * @li <b>00</b> - GPIO PIN
597 * @li <b>10</b> - As a Azalia SDIN pin
598 */
599} AZALIAPIN;
600
601/** AMDSBCFG - Southbridge CIMx configuration structure (Main) */
602typedef struct _AMDSBCFG {
603/** StdHeader - Standard header for all AGESA/CIMx services. */
604 AMD_CONFIG_PARAMS StdHeader;
605
606/** BuildParameters - The STATIC platform information for CIMx Module. */
607 BUILDPARAM BuildParameters;
608 //offset 90 bytes (32-121)
609 //MsgXchgBiosCimx //offset 4 bytes (122-125)
610 // SATA Configuration
611
612 union /**< union - Reserved */
613 { /**< SATAMODE - Sata Controller structure */
614/** SataModeReg - Reserved */
615 unsigned char SataModeReg;
616/** SataMode - Reserved */
617 SATAST SataMode;
618 } SATAMODE;
619/** S3Resume - Flag of ACPI S3 Resume. */
620 unsigned char S3Resume:1; // 8
621/** RebootRequired - Flag of Reboot system is required. */
622 unsigned char RebootRequired:1; // 9
623/** SbSpiSpeedSupport - Reserved */
624 unsigned char SbSpiSpeedSupport:1; // 10
625/**< SpreadSpectrum
626 * @par
627 * Spread Spectrum function
628 * @li <b>0</b> - disable
629 * @li <b>1</b> - enable
630 */
631 unsigned char SpreadSpectrum:1; // 11
632/** NbSbGen2 - Reserved */
633 unsigned char NbSbGen2:1; // 12
634 unsigned char GppGen2:1; // 13
635 unsigned char GppMemWrImprove:1; // 14
636/** MsgXchgBiosCimxReserved - Reserved */
637 unsigned char MsgXchgBiosCimxReserved:1; // 15 (BB USED)
638/**< SataClass - SATA Controller mode [16:18]
639 * @par
640 * @li <b>000</b> - Native IDE mode
641 * @li <b>001</b> - RAID mode
642 * @li <b>010</b> - AHCI mode
643 * @li <b>011</b> - Legacy IDE mode
644 * @li <b>100</b> - IDE->AHCI mode
645 * @li <b>101</b> - AHCI mode as 4394 ID (AMD driver)
646 * @li <b>110</b> - IDE->AHCI mode as 4394 ID (AMD driver)
647 */
648 unsigned short SataClass:3; // 16:18
649/**< Sata IDE Controller mode
650 * @par
651 * @li <b>0</b> - Legacy IDE mode
652 * @li <b>1</b> - Native IDE mode
653 */
654 unsigned short SataIdeMode:1; // 19
655/**< SataEspPort - SATA port is external accessible on a signal only connector (eSATA:)
656 * @par
657 * @li <b> BIT0 </b> - PORT0 set as ESP port
658 * @li <b> BIT1 </b> - PORT1 set as ESP port
659 * @li <b> BIT2 </b> - PORT2 set as ESP port
660 * @li <b> BIT3 </b> - PORT3 set as ESP port
661 * @li <b> BIT4 </b> - PORT4 set as ESP port
662 * @li <b> BIT5 </b> - PORT5 set as ESP port
663 */
664 unsigned short SataEspPort:6; // 20:25
665/** SataPortPower - Reserved */
666 unsigned short SataPortPower:6; // 31:26
667
668 // SATA Debug Option //offset 4 bytes (126-129)
669
670/**< SataPortMode - Force Each PORT to GEN1/GEN2 mode
671 * @par
672 * @li <b> 0 </b> Auto for each PORTs
673 * @li <b> BIT0 = 1</b> - PORT0 set to GEN1
674 * @li <b> BIT1 = 1</b> - PORT0 set to GEN2
675 * @li <b> BIT2 = 1</b> - PORT1 set to GEN1
676 * @li <b> BIT3 = 1</b> - PORT1 set to GEN2
677 * @li <b> BIT4 = 1</b> - PORT2 set to GEN1
678 * @li <b> BIT5 = 1</b> - PORT2 set to GEN2
679 * @li <b> BIT6 = 1</b> - PORT3 set to GEN1
680 * @li <b> BIT7 = 1</b> - PORT3 set to GEN2
681 * @li <b> BIT8 = 1</b> - PORT4 set to GEN1
682 * @li <b> BIT9 = 1</b> - PORT4 set to GEN2
683 * @li <b> BIT10 = 1</b> - PORT5 set to GEN1
684 * @li <b> BIT11 = 1</b> - PORT5 set to GEN2
685 */
686 unsigned int SataPortMode:12; //11:0
687/** SATAClkSelOpt - Reserved */
688 unsigned int SATAClkSelOpt:4; // Removed from coding side
689/** SataAggrLinkPmCap - Reserved */
690 unsigned int SataAggrLinkPmCap:1; //16, 0:OFF 1:ON
691/** SataPortMultCap - Reserved */
692 unsigned int SataPortMultCap:1; //17, 0:OFF 1:ON
693/** SataClkAutoOff - Reserved */
694 unsigned int SataClkAutoOff:1; //18, AutoClockOff 0:Disabled, 1:Enabled
695/** SataPscCap - Reserved */
696 unsigned int SataPscCap:1; //19, 0:Enable PSC capability, 1:Disable PSC capability
697/** BIOSOSHandoff - Reserved */
698 unsigned int BIOSOSHandoff:1; //20
699/** SataFisBasedSwitching - Reserved */
700 unsigned int SataFisBasedSwitching:1; //21
701/** SataCccSupport - Reserved */
702 unsigned int SataCccSupport:1; //22
703/** SataSscCap - Reserved */
704 unsigned int SataSscCap:1; //23, 0:Enable SSC capability, 1:Disable SSC capability
705/** SataMsiCapability - Reserved */
706 unsigned int SataMsiCapability:1; //24 0:Hidden 1:Visible. This feature is disabled per RPR, but remains the interface.
707/** SataForceRaid - Reserved */
708 unsigned int SataForceRaid:1; //25 0:No function 1:Force RAID
709/** SataDebugDummy - Reserved */
710 unsigned int SataDebugDummy:6; //31:26
711//
712// USB Configuration //offset 4 bytes (130-133)
713//
714
715/** USBDeviceConfig - USB Controller Configuration
716 *
717 * - Usb Ohci1 Contoller is define at BIT0
718 * - 0:disable 1:enable
719 * (Bus 0 Dev 18 Func0) *
720 * - Usb Ehci1 Contoller is define at BIT1
721 * - 0:disable 1:enable
722 * (Bus 0 Dev 18 Func2) *
723 * - Usb Ohci2 Contoller is define at BIT2
724 * - 0:disable 1:enable
725 * (Bus 0 Dev 19 Func0) *
726 * - Usb Ehci2 Contoller is define at BIT3
727 * - 0:disable 1:enable
728 * (Bus 0 Dev 19 Func2) *
729 * - Usb Ohci3 Contoller is define at BIT4
730 * - 0:disable 1:enable
731 * (Bus 0 Dev 22 Func0) *
732 * - Usb Ehci3 Contoller is define at BIT5
733 * - 0:disable 1:enable
734 * (Bus 0 Dev 22 Func2) *
735 * - Usb Ohci4 Contoller is define at BIT6
736 * - 0:disable 1:enable
737 * (Bus 0 Dev 20 Func5) *
738 */
739 union /**< union - Reserved */
740 { /**< USBMODE - USB Controller structure */
741/** SataModeReg - Reserved */
742 unsigned char UsbModeReg;
743/** SataMode - Reserved */
744 USBST UsbMode;
745 } USBMODE;
746/*!
747 */
748
749/**< GecConfig
750 * @par
751 * InChip Gbit NIC
752 * @li <b>1</b> - disable
753 * @li <b>0</b> - enable
754 */
755 unsigned char GecConfig:1; //8
756
757/**< IrConfig
758 * @par
759 * Ir Controller setting
760 * @li <b>00 </b> - disable
761 * @li <b>01 </b> - Rx and Tx0
762 * @li <b>10 </b> - Rx and Tx1
763 * @li <b>11 </b> - Rx and both Tx0,Tx1
764 */
765 unsigned char IrConfig:2; //9:10
766
767/** GecDummy - Reserved */
768 unsigned char GecDummy:5; //15:11
769
770 //Azalia Configuration
771
772/**< AzaliaController - Azalia Controller Configuration
773 * @par
774 * Azalia Controller [0-1]
775 * @li <b>0</b> - Auto : Detect Azalia controller automatically.
776 * @li <b>1</b> - Diable : Disable Azalia controller.
777 * @li <b>2</b> - Enable : Enable Azalia controller.
778 */
779 unsigned char AzaliaController:2; //17:16
780/**< AzaliaPinCfg - Azalia Controller SDIN pin Configuration
781 * @par
782 * @li <b>0</b> - disable
783 * @li <b>1</b> - enable
784 */
785 unsigned char AzaliaPinCfg:1; //18
786/**< AzaliaFrontPanel - Azalia Controller Front Panel Configuration
787 * @par
788 * Support Front Panel configuration
789 * @li <b>0</b> - Auto
790 * @li <b>1</b> - disable
791 * @li <b>2</b> - enable
792 */
793 unsigned char AzaliaFrontPanel:2; //20:19
794/**< FrontPanelDetected - Force Azalia Controller Front Panel Configuration
795 * @par
796 * Force Front Panel configuration
797 * @li <b>0</b> - Not Detected
798 * @li <b>1</b> - Detected
799 */
800 unsigned char FrontPanelDetected:1; //21
801/**< AzaliaSnoop - Azalia Controller Snoop feature Configuration
802 * @par
803 * Azalia Controller Snoop feature Configuration
804 * @li <b>0</b> - disable
805 * @li <b>1</b> - enable
806 */
807 unsigned char AzaliaSnoop:1; //22
808/** AzaliaDummy - Reserved */
809 unsigned char AzaliaDummy:1; //23
810
811 union
812 {
813/**< AzaliaSdinPin - Azalia Controller SDIN pin Configuration
814 *
815 * SDIN0 is define at BIT0 & BIT1
816 * - 00: GPIO PIN
817 * - 01: Reserved
818 * - 10: As a Azalia SDIN pin
819 *
820 * SDIN1 is define at BIT2 & BIT3
821 * * Config same as SDIN0
822 * SDIN2 is define at BIT4 & BIT5
823 * * Config same as SDIN0
824 * SDIN3 is define at BIT6 & BIT7
825 * * Config same as SDIN0
826 */
827 unsigned char AzaliaSdinPin;
828 AZALIAPIN AzaliaConfig;
829 } AZALIACONFIG;
830
831/** AZOEMTBL - Azalia Controller OEM Codec Table Pointer
832 *
833 */
834 union
835 {
836 PLACEHOLDER PlaceHolder;
837 CODECTBLLIST* pAzaliaOemCodecTablePtr; //offset 4 bytes (134-137)
838 } AZOEMTBL;
839
840/** AZOEMFPTBL - Azalia Controller Front Panel OEM Table Pointer
841 *
842 */
843 union
844 {
845 PLACEHOLDER PlaceHolder;
846 void* pAzaliaOemFpCodecTablePtr; //offset 4 bytes (138-141)
847 } AZOEMFPTBL;
848
849 //Miscellaneous Configuration //offset 4 bytes (142-145)
850/** AnyHT200MhzLink - Reserved */
851 unsigned int AnyHT200MhzLink:1; //0
852/**< HpetTimer - South Bridge Hpet Timer Configuration
853 * @par
854 * @li <b>0</b> - disable
855 * @li <b>1</b> - enable
856 */
857 unsigned int HpetTimer:1; //1
858/**< PciClks - PCI Slot Clock Control
859 * @par
860 * PCI SLOT 0 define at BIT0
861 * - 00: disable
862 * - 01: enable
863 *
864 * PCI SLOT 1 define at BIT1
865 * * Config same as PCI SLOT0
866 * PCI SLOT 2 define at BIT2
867 * * Config same as PCI SLOT0
868 * PCI SLOT 3 define at BIT3
869 * * Config same as PCI SLOT0
870 * PCI SLOT 4 define at BIT4
871 * * Config same as PCI SLOT0
872 */
873 unsigned int PciClks:5; //2:6
874/** MiscReserved1 - Reserved */
875 unsigned int MiscReserved1:4; //9:7, Reserved
876/** MobilePowerSavings - Debug function Reserved */
877 unsigned int MobilePowerSavings:1; //11, 0:Disable, 1:Enable Power saving features especially for Mobile platform
878/** MiscDummy1 - Debug function Reserved */
879 unsigned int MiscDummy1:1;
880/** NativePcieSupport - Debug function Reserved */
881 unsigned int NativePcieSupport:1; //13, 0:Enable, 1:Disabled
882/** FlashPinConfig - Debug function Reserved */
883 unsigned int FlashPinConfig:1; //14, 0:desktop mode 1:mobile mode
884/** UsbPhyPowerDown - Debug function Reserved */
885 unsigned int UsbPhyPowerDown:1; //15
886/** PcibClkStopOverride - Debug function Reserved */
887 unsigned int PcibClkStopOverride:10; //25:16
888/**< HpetMsiDis - South Bridge HPET MSI Configuration
889 * @par
890 * @li <b>1</b> - disable
891 * @li <b>0</b> - enable
892 */
893 unsigned int HpetMsiDis:1; //26
894/**< ResetCpuOnSyncFlood - Rest CPU on Sync Flood
895 * @par
896 * @li <b>0</b> - disable
897 * @li <b>1</b> - enable
898 */
899 unsigned int ResetCpuOnSyncFlood:1; //27
900/**< LdtStpDisable - LdtStp# output disable
901 * @par
902 * @li <b>0</b> - LdtStp# output enable
903 * @li <b>1</b> - LdtStp# output disable
904 */
905 unsigned int LdtStpDisable:1; //28
906/**< MTC1e - Message Triggered C1e
907 * @par
908 * @li <b>0</b> - disable
909 * @li <b>1</b> - enable
910 */
911 unsigned int MTC1e:1; //29
912/** MiscDummy - Reserved */
913 unsigned int MiscDummy:2; //31:30
914
915 //DebugOptions //offset 4 bytes (146-149)
916/** PcibAutoClkCtrlLow - Debug function Reserved */
917 unsigned int PcibAutoClkCtrlLow:16;
918/** PcibAutoClkCtrlHigh - Debug function Reserved */
919 unsigned int PcibAutoClkCtrlHigh:16;
920
921/**< OEMPROGTBL - ACPI MMIO register setting table OEM override
922 * @par
923 * OEM table for customer override ACPI MMIO register in their code.
924 */
925 union
926 {
927 PLACEHOLDER OemProgrammingTablePtr; //offset 4 bytes (150-153)
928 void *OemProgrammingTablePtr_Ptr;
929 } OEMPROGTBL;
930
931 //Gpp Configuration //offset 24 bytes total (154-177)
932 union {
933 unsigned int PORTCFG32;
934 SBGPPPORTCONFIG PortCfg;
935 } PORTCONFIG[MAX_GPP_PORTS]; //offset 16 bytes
936
937 unsigned int GppLinkConfig; // GPP_LINK_CONFIG = PCIE_GPP_Enable[3:0]
938 // 0000 - Port ABCD -> 4:0:0:0
939 // 0001 - N/A
940 // 0010 - Port ABCD -> 2:2:0:0
941 // 0011 - Port ABCD -> 2:1:1:0
942 // 0100 - Port ABCD -> 1:1:1:1
943 //
944 unsigned int GppFoundGfxDev:4; //3:0 If port A-D (mapped to bit [3:0]) has GFX EP detected
945 unsigned int CoreGen2Enable:1; //4
946 unsigned int GppFunctionEnable:1; //5
947 unsigned int GppUnhidePorts:1; //6
948 unsigned int AlinkPhyPllPowerDown:1; //7
949 unsigned int GppConfigDummy1:2; //9:8
950 unsigned int GppLaneReversal:1; //10
951 unsigned int GppPhyPllPowerDown:1; //11
952 unsigned int GppCompliance :1; //12
953 unsigned int GppPortAspm:8; //20:13 ASPM state for GPP ports, 14:13 for port0, ..., 20:19 for port3
954 // 00 - Disabled
955 // 01 - L0s
956 // 10 - L1
957 // 11 - L0s + L1
958 //
959 unsigned int GppConfigDummy:11; //31:21
960
961 //TempMMIO //offset 4 bytes (178-181)
962 unsigned int TempMMIO;
963
964 // DebugOption2
965 unsigned int GecPhyStatus:1;
966 unsigned int GecDebugOptionDummy:7;
967 unsigned int SBGecPwr:2;
968 unsigned int SBGecDebugBus:1;
969 unsigned int DebugOption2Dummy1:1;
970 unsigned int DebugOption2Dummy2:1;
971 unsigned int SbPcieOrderRule:1;
972 unsigned int SbUsbPll:1;
973 unsigned int AcDcMsg:1;
974 unsigned int TimerTickTrack:1;
975 unsigned int ClockInterruptTag:1;
976 unsigned int OhciTrafficHanding:1;
977 unsigned int EhciTrafficHanding:1;
978 unsigned int FusionMsgCMultiCore:1;
979 unsigned int FusionMsgCStage:1;
980/**< UsbRxMode - CG PLL multiplier for USB Rx 1.1 mode
981 * @par
982 * @li <b>0</b> - disable
983 * @li <b>1</b> - enable
984 */
985 unsigned int UsbRxMode:1;
986 unsigned int DebugOption2Dummy3:9; //
987
988 union
989 {
990 PLACEHOLDER DynamicGecRomAddressPtr; //offset 4 bytes (182-185)
991 void *DynamicGecRomAddress_Ptr;
992 } DYNAMICGECROM;
993 EC_struct Pecstruct;
994} AMDSBCFG;
995
996/** SMMSERVICESTRUC- Southbridge SMI service structure */
997typedef struct _SMMSERVICESTRUC {
998/** enableRegNum - Reserved */
999 unsigned char enableRegNum;
1000/** enableBit - Reserved */
1001 unsigned char enableBit;
1002/** statusRegNum - Reserved */
1003 unsigned char statusRegNum;
1004/** statusBit - Reserved */
1005 unsigned char statusBit;
1006/** *debugMessage- Reserved */
1007 signed char *debugMessage;
1008/** serviceRoutine - Reserved */
1009 SMM_SERVICE_ROUTINE serviceRoutine;
1010} SMMSERVICESTRUC;
1011
1012#ifndef _NB_REG8MASK_
1013
1014/**
1015 * - Byte Register R/W structure
1016 *
1017 */
1018 typedef struct _Reg8Mask {
1019/** bRegIndex - Reserved */
1020 unsigned char bRegIndex;
1021/** bANDMask - Reserved */
1022 unsigned char bANDMask;
1023/** bORMask - Reserved */
1024 unsigned char bORMask;
1025 } REG8MASK;
1026#endif
1027
1028/**
1029 * - SATA Phy setting structure
1030 *
1031 */
1032typedef struct _SATAPHYSETTING {
1033/** wPhyCoreControl - Reserved */
1034 unsigned short wPhyCoreControl;
1035/** dwPhyFineTune - Reserved */
1036 unsigned int dwPhyFineTune;
1037} SATAPHYSETTING;
1038
1039/**
1040 * _ABTblEntry - AB link register table R/W structure
1041 *
1042 */
1043typedef struct _ABTblEntry {
1044 /** regType : AB Register Type (ABCFG, AXCFG and so on) */
1045 unsigned char regType;
1046 /** regIndex : AB Register Index */
1047 unsigned int regIndex;
1048 /** regMask : AB Register Mask */
1049 unsigned int regMask;
1050 /** regData : AB Register Data */
1051 unsigned int regData;
1052} ABTBLENTRY;
1053
1054/**
1055 * _AcpiRegWrite - ACPI MMIO register R/W structure
1056 *
1057 */
1058typedef struct _AcpiRegWrite {
1059 /** MmioBase : Index of Soubridge block (For instence GPIO_BASE:0x01 SMI_BASE:0x02) */
1060 unsigned char MmioBase;
1061 /** MmioReg : Register index */
1062 unsigned char MmioReg;
1063 /** DataANDMask : AND Register Data */
1064 unsigned char DataANDMask;
1065 /** DataOrMask : Or Register Data */
1066 unsigned char DataOrMask;
1067} AcpiRegWrite;
1068
1069/**
1070 * PCI_ADDRESS - PCI access structure
1071 *
1072 */
1073#define PCI_ADDRESS(bus, dev, func, reg) \
1074(unsigned int) ( (((unsigned int)bus) << 24) + (((unsigned int)dev) << 19) + (((unsigned int)func) << 16) + ((unsigned int)reg) )
1075
1076/**
1077 * CIM_STATUS - CIMx module function return code
1078 */
1079typedef unsigned int CIM_STATUS;
1080/**
1081 * CIM_SUCCESS - Executed without error
1082 */
1083#define CIM_SUCCESS 0x00000000
1084/**
1085 * CIM_ERROR - call error
1086 */
1087#define CIM_ERROR 0x80000000
1088/**
1089 * CIM_UNSUPPORTED - function does not support
1090 */
1091#define CIM_UNSUPPORTED 0x80000001
1092
1093#pragma pack (pop)
1094
1095/**
1096 * DISABLED - Define disable in module
1097 */
1098#define DISABLED 0
1099/**
1100 * ENABLED - Define enable in module
1101 */
1102#define ENABLED 1
1103
1104// mov al, code
1105// out 80h, al
1106// jmp $
1107
1108/**
1109 * DBG_STOP - define a debug point
1110 */
1111#define DBG_STOP __asm _emit 0xEB __asm _emit 0xFE
1112
1113/**
1114 * STOP_CODE - define a debug point
1115 * Warning: AL gets destroyed!
1116 */
1117#define STOP_CODE (code) __asm __emit 0xB0 __asm __emit code __asm __emit 0xE6 \
1118 __asm __emit 0x80 __asm _emit 0xEB __asm _emit 0xFE
1119
1120#endif // _AMD_SBTYPE_H_