AMD SB800 southbridge update
This patch enables access to the registers of the hardware monitor
logical device in the superio via isa ports 0x295/0x296.
Previously this was not enabled in the SB8xx LPC device.
This is required for initialisation in init_hwm() in
src/superio/winbond/w83627hf/superio.c and also by OS-level
sensor monitoring such as lm-sensors to access temperature,
fan monitoring and control and voltage registers.
asrock/e350m1 and advansus/a785e-i mainboard changes are included herein.
Change-Id: I2176885549277b335c0c41b48457d09b9b76b703
Signed-off-by: Per Hansen <perh52@runbox.com>
Signed-off-by: Kerry She <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/159
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
diff --git a/src/vendorcode/amd/cimx/sb800/SBTYPE.h b/src/vendorcode/amd/cimx/sb800/SBTYPE.h
index ea3e6f6..b8278cf 100644
--- a/src/vendorcode/amd/cimx/sb800/SBTYPE.h
+++ b/src/vendorcode/amd/cimx/sb800/SBTYPE.h
@@ -156,6 +156,10 @@
* @par
* SIO PME BASE Address
*/
+ unsigned int SioHwmBaseAddress; /**< SioHwmBaseAddress
+ * @par
+ * SIO HWM BASE Address
+ */
unsigned int WatchDogTimerBase; /**< WatchDogTimerBase
* @par
* Watch Dog Timer Address
@@ -911,6 +915,7 @@
unsigned int MTC1e:1; //29
/** MiscDummy - Reserved */
unsigned int MiscDummy:2; //31:30
+ unsigned int SioHwmPortEnable:1; // Enable SuperIO HWM access via LPC
//DebugOptions //offset 4 bytes (146-149)
/** PcibAutoClkCtrlLow - Debug function Reserved */