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Angel Pons0612b272020-04-05 15:46:56 +02001/* SPDX-License-Identifier: GPL-2.0-only */
Aamir Bohra52f29742017-04-19 18:19:14 +05302
3#include <device/device.h>
4#include <device/path.h>
5#include <device/smbus.h>
6#include <device/pci.h>
7#include <device/pci_ids.h>
Aamir Bohra52f29742017-04-19 18:19:14 +05308#include <soc/smbus.h>
Kyösti Mälkki1cae4542020-01-06 12:31:34 +02009#include <device/smbus_host.h>
Subrata Banikf48b8432022-04-14 19:05:52 +053010#include <intelblocks/tco.h>
Angel Ponsc2461a12022-05-17 20:29:46 +020011#include <southbridge/intel/common/smbus_ops.h>
Aamir Bohra52f29742017-04-19 18:19:14 +053012#include "smbuslib.h"
13
Elyes HAOUAS4a131262018-09-16 17:35:48 +020014static void pch_smbus_init(struct device *dev)
Aamir Bohra52f29742017-04-19 18:19:14 +053015{
16 struct resource *res;
Aamir Bohra52f29742017-04-19 18:19:14 +053017
18 /* Enable clock gating */
Nico Huber62788672017-08-17 16:08:00 +020019 pci_update_config32(dev, 0x80,
20 ~((1 << 8) | (1 << 10) | (1 << 12) | (1 << 14)), 0);
Aamir Bohra52f29742017-04-19 18:19:14 +053021
22 /* Set Receive Slave Address */
Angel Ponsc1bfbe02021-11-03 13:18:53 +010023 res = probe_resource(dev, PCI_BASE_ADDRESS_4);
Aamir Bohra52f29742017-04-19 18:19:14 +053024 if (res)
Kyösti Mälkki73451fd2020-01-06 19:00:31 +020025 smbus_set_slave_addr(res->base, SMBUS_SLAVE_ADDR);
Aamir Bohra52f29742017-04-19 18:19:14 +053026}
27
Subrata Banikf48b8432022-04-14 19:05:52 +053028/*
29 * `finalize_smbus` function is native implementation of equivalent events
30 * performed by each FSP NotifyPhase() API invocations.
31 *
32 * Operations are:
33 * 1. TCO Lock.
34 */
35static void finalize_smbus(struct device *dev)
36{
37 if (!CONFIG(USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM))
38 tco_lockdown();
39}
40
Nico Huber57686192022-08-06 19:11:55 +020041struct device_operations smbus_ops = {
Elyes HAOUAS1d191272018-11-27 12:23:48 +010042 .read_resources = smbus_read_resources,
43 .set_resources = pci_dev_set_resources,
44 .enable_resources = pci_dev_enable_resources,
45 .scan_bus = scan_smbus,
46 .init = pch_smbus_init,
Subrata Banik6bbc91a2017-12-07 14:55:51 +053047 .ops_pci = &pci_dev_ops_pci,
Aamir Bohra52f29742017-04-19 18:19:14 +053048 .ops_smbus_bus = &lops_smbus_bus,
Subrata Banikf48b8432022-04-14 19:05:52 +053049 .final = finalize_smbus,
Aamir Bohra52f29742017-04-19 18:19:14 +053050};
51
52static const unsigned short pci_device_ids[] = {
Wonkyu Kim9f401072020-11-13 15:16:32 -080053 PCI_DID_INTEL_MTL_SMBUS,
Bora Guvendika15b25f2022-02-28 14:43:49 -080054 PCI_DID_INTEL_RPP_P_SMBUS,
Felix Singer43b7f412022-03-07 04:34:52 +010055 PCI_DID_INTEL_APL_SMBUS,
Sean Rhodesf2516602022-09-07 13:30:05 +010056 PCI_DID_INTEL_GLK_SMBUS,
Felix Singer43b7f412022-03-07 04:34:52 +010057 PCI_DID_INTEL_CNL_SMBUS,
58 PCI_DID_INTEL_CNP_H_SMBUS,
Tim Chu2ccbcc52022-12-08 11:05:36 +000059 PCI_DID_INTEL_EBG_SMBUS,
Felix Singer43b7f412022-03-07 04:34:52 +010060 PCI_DID_INTEL_LWB_SMBUS_SUPER,
61 PCI_DID_INTEL_LWB_SMBUS,
62 PCI_DID_INTEL_ICP_LP_SMBUS,
63 PCI_DID_INTEL_CMP_SMBUS,
64 PCI_DID_INTEL_CMP_H_SMBUS,
65 PCI_DID_INTEL_TGP_LP_SMBUS,
66 PCI_DID_INTEL_TGP_H_SMBUS,
67 PCI_DID_INTEL_MCC_SMBUS,
68 PCI_DID_INTEL_JSP_SMBUS,
69 PCI_DID_INTEL_ADP_P_SMBUS,
70 PCI_DID_INTEL_ADP_S_SMBUS,
71 PCI_DID_INTEL_ADP_M_N_SMBUS,
72 PCI_DID_INTEL_DNV_SMBUS_LEGACY,
Aamir Bohra52f29742017-04-19 18:19:14 +053073 0
74};
75
76static const struct pci_driver pch_smbus __pci_driver = {
77 .ops = &smbus_ops,
Felix Singer43b7f412022-03-07 04:34:52 +010078 .vendor = PCI_VID_INTEL,
Aamir Bohra52f29742017-04-19 18:19:14 +053079 .devices = pci_device_ids,
80};