| Aamir Bohra | 52f2974 | 2017-04-19 18:19:14 +0530 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2017 Intel Corporation. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| 15 | |
| 16 | #include <device/device.h> |
| 17 | #include <device/path.h> |
| 18 | #include <device/smbus.h> |
| 19 | #include <device/pci.h> |
| 20 | #include <device/pci_ids.h> |
| 21 | #include <device/pci_ops.h> |
| 22 | #include <soc/smbus.h> |
| 23 | #include "smbuslib.h" |
| 24 | |
| 25 | static int lsmbus_read_byte(device_t dev, u8 address) |
| 26 | { |
| 27 | u16 device; |
| 28 | struct resource *res; |
| 29 | struct bus *pbus; |
| 30 | device = dev->path.i2c.device; |
| 31 | pbus = get_pbus_smbus(dev); |
| 32 | res = find_resource(pbus->dev, PCI_BASE_ADDRESS_4); |
| 33 | return smbus_read8(res->base, device, address); |
| 34 | } |
| 35 | |
| 36 | static int lsmbus_write_byte(device_t dev, u8 address, u8 data) |
| 37 | { |
| 38 | u16 device; |
| 39 | struct resource *res; |
| 40 | struct bus *pbus; |
| 41 | |
| 42 | device = dev->path.i2c.device; |
| 43 | pbus = get_pbus_smbus(dev); |
| 44 | res = find_resource(pbus->dev, PCI_BASE_ADDRESS_4); |
| 45 | return smbus_write8(res->base, device, address, data); |
| 46 | } |
| 47 | |
| 48 | static struct smbus_bus_operations lops_smbus_bus = { |
| 49 | .read_byte = lsmbus_read_byte, |
| 50 | .write_byte = lsmbus_write_byte, |
| 51 | }; |
| 52 | |
| 53 | static void pch_smbus_init(device_t dev) |
| 54 | { |
| 55 | struct resource *res; |
| 56 | u16 reg16; |
| 57 | |
| 58 | /* Enable clock gating */ |
| 59 | reg16 = pci_read_config32(dev, 0x80); |
| 60 | reg16 &= ~((1 << 8)|(1 << 10)|(1 << 12)|(1 << 14)); |
| 61 | pci_write_config32(dev, 0x80, reg16); |
| 62 | |
| 63 | /* Set Receive Slave Address */ |
| 64 | res = find_resource(dev, PCI_BASE_ADDRESS_4); |
| 65 | if (res) |
| 66 | outb(SMBUS_SLAVE_ADDR, res->base + SMB_RCV_SLVA); |
| 67 | } |
| 68 | |
| 69 | static void smbus_read_resources(device_t dev) |
| 70 | { |
| 71 | struct resource *res = new_resource(dev, PCI_BASE_ADDRESS_4); |
| 72 | res->base = SMBUS_IO_BASE; |
| 73 | res->size = 32; |
| 74 | res->limit = res->base + res->size - 1; |
| 75 | res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE | |
| 76 | IORESOURCE_STORED | IORESOURCE_ASSIGNED; |
| 77 | |
| 78 | /* Also add MMIO resource */ |
| 79 | res = pci_get_resource(dev, PCI_BASE_ADDRESS_0); |
| 80 | } |
| 81 | |
| 82 | static struct device_operations smbus_ops = { |
| 83 | .read_resources = &smbus_read_resources, |
| 84 | .set_resources = &pci_dev_set_resources, |
| 85 | .enable_resources = &pci_dev_enable_resources, |
| 86 | .scan_bus = &scan_smbus, |
| 87 | .init = &pch_smbus_init, |
| 88 | .ops_smbus_bus = &lops_smbus_bus, |
| 89 | }; |
| 90 | |
| 91 | static const unsigned short pci_device_ids[] = { |
| 92 | PCI_DEVICE_ID_INTEL_SPT_LP_SMBUS, |
| 93 | PCI_DEVICE_ID_INTEL_SPT_H_SMBUS, |
| 94 | 0 |
| 95 | }; |
| 96 | |
| 97 | static const struct pci_driver pch_smbus __pci_driver = { |
| 98 | .ops = &smbus_ops, |
| 99 | .vendor = PCI_VENDOR_ID_INTEL, |
| 100 | .devices = pci_device_ids, |
| 101 | }; |