Angel Pons | f94ac9a | 2020-04-05 15:46:48 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 2 | |
| 3 | #include <console/console.h> |
| 4 | #include <device/device.h> |
Jonathan A. Kollasch | ec505ad2 | 2015-07-07 12:57:46 -0500 | [diff] [blame] | 5 | #include <device/azalia_device.h> |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 6 | #include <device/pci.h> |
| 7 | #include <device/pci_ids.h> |
| 8 | #include <device/pci_ops.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 9 | #include <device/mmio.h> |
Julius Werner | 4ee4bd5 | 2014-10-20 13:46:39 -0700 | [diff] [blame] | 10 | #include <soc/pch.h> |
Julius Werner | 4ee4bd5 | 2014-10-20 13:46:39 -0700 | [diff] [blame] | 11 | #include <soc/rcba.h> |
Angel Pons | b5d56f9 | 2021-06-23 12:47:49 +0200 | [diff] [blame] | 12 | #include <southbridge/intel/lynxpoint/hda_verb.h> |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 13 | |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 14 | static void hda_pch_init(struct device *dev, u8 *base) |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 15 | { |
| 16 | u8 reg8; |
| 17 | u16 reg16; |
| 18 | u32 reg32; |
| 19 | |
| 20 | if (RCBA32(0x2030) & (1 << 31)) { |
| 21 | reg32 = pci_read_config32(dev, 0x120); |
| 22 | reg32 &= 0xf8ffff01; |
| 23 | reg32 |= (1 << 25); |
| 24 | reg32 |= RCBA32(0x2030) & 0xfe; |
| 25 | pci_write_config32(dev, 0x120, reg32); |
| 26 | } else |
| 27 | printk(BIOS_DEBUG, "HDA: V1CTL disabled.\n"); |
| 28 | |
| 29 | reg32 = pci_read_config32(dev, 0x114); |
| 30 | reg32 &= ~0xfe; |
| 31 | pci_write_config32(dev, 0x114, reg32); |
| 32 | |
| 33 | // Set VCi enable bit |
| 34 | if (pci_read_config32(dev, 0x120) & ((1 << 24) | |
| 35 | (1 << 25) | (1 << 26))) { |
| 36 | reg32 = pci_read_config32(dev, 0x120); |
| 37 | reg32 &= ~(1 << 31); |
| 38 | pci_write_config32(dev, 0x120, reg32); |
| 39 | } |
| 40 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 41 | /* Additional programming steps */ |
| 42 | reg32 = pci_read_config32(dev, 0xc4); |
| 43 | reg32 |= (1 << 24); |
| 44 | pci_write_config32(dev, 0xc4, reg32); |
| 45 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 46 | reg8 = pci_read_config8(dev, 0x4d); // Docking Status |
| 47 | reg8 &= ~(1 << 7); // Docking not supported |
| 48 | pci_write_config8(dev, 0x4d, reg8); |
| 49 | |
| 50 | reg16 = read32(base + 0x0012); |
| 51 | reg16 |= (1 << 0); |
| 52 | write32(base + 0x0012, reg16); |
| 53 | |
| 54 | /* disable Auto Voltage Detector */ |
| 55 | reg8 = pci_read_config8(dev, 0x42); |
| 56 | reg8 |= (1 << 2); |
| 57 | pci_write_config8(dev, 0x42, reg8); |
| 58 | } |
| 59 | |
| 60 | static void hda_init(struct device *dev) |
| 61 | { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 62 | u8 *base; |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 63 | struct resource *res; |
| 64 | u32 codec_mask; |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 65 | |
| 66 | /* Find base address */ |
Angel Pons | c1bfbe0 | 2021-11-03 13:18:53 +0100 | [diff] [blame] | 67 | res = probe_resource(dev, PCI_BASE_ADDRESS_0); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 68 | if (!res) |
| 69 | return; |
| 70 | |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 71 | base = res2mmio(res, 0, 0); |
| 72 | printk(BIOS_DEBUG, "HDA: base = %p\n", base); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 73 | |
| 74 | /* Set Bus Master */ |
Elyes HAOUAS | b887adf | 2020-04-29 10:42:34 +0200 | [diff] [blame] | 75 | pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 76 | |
| 77 | hda_pch_init(dev, base); |
| 78 | |
| 79 | codec_mask = hda_codec_detect(base); |
| 80 | |
| 81 | if (codec_mask) { |
| 82 | printk(BIOS_DEBUG, "HDA: codec_mask = %02x\n", codec_mask); |
Angel Pons | 4f8aea0 | 2021-11-10 18:09:04 +0100 | [diff] [blame] | 83 | azalia_codecs_init(base, codec_mask); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 84 | } |
| 85 | } |
| 86 | |
Duncan Laurie | 6168027 | 2014-05-05 12:42:35 -0500 | [diff] [blame] | 87 | static void hda_enable(struct device *dev) |
| 88 | { |
Elyes HAOUAS | b887adf | 2020-04-29 10:42:34 +0200 | [diff] [blame] | 89 | u16 reg16; |
Duncan Laurie | 446fb8e | 2014-08-08 09:59:43 -0700 | [diff] [blame] | 90 | u8 reg8; |
| 91 | |
| 92 | reg8 = pci_read_config8(dev, 0x43); |
| 93 | reg8 |= 0x6f; |
| 94 | pci_write_config8(dev, 0x43, reg8); |
Duncan Laurie | 6168027 | 2014-05-05 12:42:35 -0500 | [diff] [blame] | 95 | |
| 96 | if (!dev->enabled) { |
| 97 | /* Route I/O buffers to ADSP function */ |
Duncan Laurie | 446fb8e | 2014-08-08 09:59:43 -0700 | [diff] [blame] | 98 | reg8 = pci_read_config8(dev, 0x42); |
| 99 | reg8 |= (1 << 7) | (1 << 6); |
| 100 | pci_write_config8(dev, 0x42, reg8); |
Duncan Laurie | 6168027 | 2014-05-05 12:42:35 -0500 | [diff] [blame] | 101 | |
| 102 | printk(BIOS_INFO, "HDA disabled, I/O buffers routed to ADSP\n"); |
| 103 | |
| 104 | /* Ensure memory, io, and bus master are all disabled */ |
Elyes HAOUAS | b887adf | 2020-04-29 10:42:34 +0200 | [diff] [blame] | 105 | reg16 = pci_read_config16(dev, PCI_COMMAND); |
| 106 | reg16 &= ~(PCI_COMMAND_MASTER | |
Duncan Laurie | 6168027 | 2014-05-05 12:42:35 -0500 | [diff] [blame] | 107 | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); |
Elyes HAOUAS | b887adf | 2020-04-29 10:42:34 +0200 | [diff] [blame] | 108 | pci_write_config16(dev, PCI_COMMAND, reg16); |
Duncan Laurie | 6168027 | 2014-05-05 12:42:35 -0500 | [diff] [blame] | 109 | |
| 110 | /* Disable this device */ |
| 111 | pch_disable_devfn(dev); |
| 112 | } |
| 113 | } |
| 114 | |
Angel Pons | c1301dd | 2021-03-18 20:35:19 +0100 | [diff] [blame] | 115 | static void hda_final(struct device *dev) |
| 116 | { |
| 117 | /* Set HDCFG.BCLD */ |
| 118 | pci_or_config16(dev, 0x40, 1 << 1); |
| 119 | } |
| 120 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 121 | static struct device_operations hda_ops = { |
| 122 | .read_resources = &pci_dev_read_resources, |
| 123 | .set_resources = &pci_dev_set_resources, |
| 124 | .enable_resources = &pci_dev_enable_resources, |
| 125 | .init = &hda_init, |
Duncan Laurie | 6168027 | 2014-05-05 12:42:35 -0500 | [diff] [blame] | 126 | .enable = &hda_enable, |
Angel Pons | c1301dd | 2021-03-18 20:35:19 +0100 | [diff] [blame] | 127 | .final = &hda_final, |
Angel Pons | cb2080f | 2020-10-23 15:45:44 +0200 | [diff] [blame] | 128 | .ops_pci = &pci_dev_ops_pci, |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 129 | }; |
| 130 | |
| 131 | static const unsigned short pci_device_ids[] = { |
| 132 | 0x9c20, /* LynxPoint-LP */ |
| 133 | 0x9ca0, /* WildcatPoint */ |
| 134 | 0 |
| 135 | }; |
| 136 | |
| 137 | static const struct pci_driver pch_hda __pci_driver = { |
| 138 | .ops = &hda_ops, |
| 139 | .vendor = PCI_VENDOR_ID_INTEL, |
| 140 | .devices = pci_device_ids, |
| 141 | }; |