Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2008 Advanced Micro Devices, Inc. |
| 5 | * Copyright (C) 2008-2009 coresystems GmbH |
| 6 | * Copyright (C) 2014 Google Inc. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; version 2 of the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
| 19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 20 | */ |
| 21 | |
| 22 | #include <console/console.h> |
| 23 | #include <device/device.h> |
| 24 | #include <device/pci.h> |
| 25 | #include <device/pci_ids.h> |
| 26 | #include <device/pci_ops.h> |
| 27 | #include <arch/io.h> |
| 28 | #include <delay.h> |
| 29 | #include <soc/intel/common/hda_verb.h> |
| 30 | #include <broadwell/ramstage.h> |
| 31 | #include <broadwell/rcba.h> |
| 32 | |
| 33 | const u32 * cim_verb_data = NULL; |
| 34 | u32 cim_verb_data_size = 0; |
| 35 | const u32 * pc_beep_verbs = NULL; |
| 36 | u32 pc_beep_verbs_size = 0; |
| 37 | |
| 38 | static void codecs_init(u32 base, u32 codec_mask) |
| 39 | { |
| 40 | int i; |
| 41 | |
| 42 | /* Can support up to 4 codecs */ |
| 43 | for (i = 3; i >= 0; i--) { |
| 44 | if (codec_mask & (1 << i)) |
| 45 | hda_codec_init(base, i, |
| 46 | cim_verb_data_size, |
| 47 | cim_verb_data); |
| 48 | } |
| 49 | |
| 50 | if (pc_beep_verbs_size && pc_beep_verbs) |
| 51 | hda_codec_write(base, pc_beep_verbs_size, pc_beep_verbs); |
| 52 | } |
| 53 | |
| 54 | static void hda_pch_init(struct device *dev, u32 base) |
| 55 | { |
| 56 | u8 reg8; |
| 57 | u16 reg16; |
| 58 | u32 reg32; |
| 59 | |
| 60 | if (RCBA32(0x2030) & (1 << 31)) { |
| 61 | reg32 = pci_read_config32(dev, 0x120); |
| 62 | reg32 &= 0xf8ffff01; |
| 63 | reg32 |= (1 << 25); |
| 64 | reg32 |= RCBA32(0x2030) & 0xfe; |
| 65 | pci_write_config32(dev, 0x120, reg32); |
| 66 | } else |
| 67 | printk(BIOS_DEBUG, "HDA: V1CTL disabled.\n"); |
| 68 | |
| 69 | reg32 = pci_read_config32(dev, 0x114); |
| 70 | reg32 &= ~0xfe; |
| 71 | pci_write_config32(dev, 0x114, reg32); |
| 72 | |
| 73 | // Set VCi enable bit |
| 74 | if (pci_read_config32(dev, 0x120) & ((1 << 24) | |
| 75 | (1 << 25) | (1 << 26))) { |
| 76 | reg32 = pci_read_config32(dev, 0x120); |
| 77 | reg32 &= ~(1 << 31); |
| 78 | pci_write_config32(dev, 0x120, reg32); |
| 79 | } |
| 80 | |
| 81 | reg8 = pci_read_config8(dev, 0x43); |
| 82 | reg8 &= ~(1 << 6); |
| 83 | pci_write_config8(dev, 0x43, reg8); |
| 84 | |
| 85 | /* Additional programming steps */ |
| 86 | reg32 = pci_read_config32(dev, 0xc4); |
| 87 | reg32 |= (1 << 24); |
| 88 | pci_write_config32(dev, 0xc4, reg32); |
| 89 | |
| 90 | reg8 = pci_read_config8(dev, 0x40); // Audio Control |
| 91 | reg8 |= 1; // Select HDA mode |
| 92 | pci_write_config8(dev, 0x40, reg8); |
| 93 | |
| 94 | reg8 = pci_read_config8(dev, 0x4d); // Docking Status |
| 95 | reg8 &= ~(1 << 7); // Docking not supported |
| 96 | pci_write_config8(dev, 0x4d, reg8); |
| 97 | |
| 98 | reg16 = read32(base + 0x0012); |
| 99 | reg16 |= (1 << 0); |
| 100 | write32(base + 0x0012, reg16); |
| 101 | |
| 102 | /* disable Auto Voltage Detector */ |
| 103 | reg8 = pci_read_config8(dev, 0x42); |
| 104 | reg8 |= (1 << 2); |
| 105 | pci_write_config8(dev, 0x42, reg8); |
| 106 | } |
| 107 | |
| 108 | static void hda_init(struct device *dev) |
| 109 | { |
| 110 | u32 base; |
| 111 | struct resource *res; |
| 112 | u32 codec_mask; |
| 113 | u32 reg32; |
| 114 | |
| 115 | /* Find base address */ |
| 116 | res = find_resource(dev, PCI_BASE_ADDRESS_0); |
| 117 | if (!res) |
| 118 | return; |
| 119 | |
| 120 | base = (u32)res->base; |
| 121 | printk(BIOS_DEBUG, "HDA: base = %08x\n", (u32)base); |
| 122 | |
| 123 | /* Set Bus Master */ |
| 124 | reg32 = pci_read_config32(dev, PCI_COMMAND); |
| 125 | pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER); |
| 126 | |
| 127 | hda_pch_init(dev, base); |
| 128 | |
| 129 | codec_mask = hda_codec_detect(base); |
| 130 | |
| 131 | if (codec_mask) { |
| 132 | printk(BIOS_DEBUG, "HDA: codec_mask = %02x\n", codec_mask); |
| 133 | codecs_init(base, codec_mask); |
| 134 | } |
| 135 | } |
| 136 | |
| 137 | static struct device_operations hda_ops = { |
| 138 | .read_resources = &pci_dev_read_resources, |
| 139 | .set_resources = &pci_dev_set_resources, |
| 140 | .enable_resources = &pci_dev_enable_resources, |
| 141 | .init = &hda_init, |
| 142 | .ops_pci = &broadwell_pci_ops, |
| 143 | }; |
| 144 | |
| 145 | static const unsigned short pci_device_ids[] = { |
| 146 | 0x9c20, /* LynxPoint-LP */ |
| 147 | 0x9ca0, /* WildcatPoint */ |
| 148 | 0 |
| 149 | }; |
| 150 | |
| 151 | static const struct pci_driver pch_hda __pci_driver = { |
| 152 | .ops = &hda_ops, |
| 153 | .vendor = PCI_VENDOR_ID_INTEL, |
| 154 | .devices = pci_device_ids, |
| 155 | }; |