Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; version 2 of |
| 9 | * the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | #include <arch/io.h> |
Duncan Laurie | 04c5bae | 2012-08-13 09:37:42 -0700 | [diff] [blame] | 18 | #include <console/post_codes.h> |
Dennis Wassenberg | 0c04720 | 2015-09-10 12:03:45 +0200 | [diff] [blame] | 19 | #include <cpu/x86/smm.h> |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 20 | #include "pch.h" |
Zheng Bao | 600784e | 2013-02-07 17:30:23 +0800 | [diff] [blame] | 21 | #include <spi-generic.h> |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 22 | |
| 23 | void intel_pch_finalize_smm(void) |
| 24 | { |
Dennis Wassenberg | 0c04720 | 2015-09-10 12:03:45 +0200 | [diff] [blame] | 25 | u16 tco1_cnt; |
| 26 | u16 pmbase; |
| 27 | |
Nico Huber | 2ac149d | 2017-09-01 23:28:14 +0200 | [diff] [blame^] | 28 | if (IS_ENABLED(CONFIG_LOCK_SPI_FLASH_RO) || |
| 29 | IS_ENABLED(CONFIG_LOCK_SPI_FLASH_NO_ACCESS)) { |
Vladimir Serbinenko | d3b194e | 2015-05-12 12:39:53 +0200 | [diff] [blame] | 30 | /* Copy flash regions from FREG0-4 to PR0-4 |
| 31 | and enable write protection bit31 */ |
| 32 | int i; |
| 33 | u32 lockmask = (1 << 31); |
Nico Huber | 2ac149d | 2017-09-01 23:28:14 +0200 | [diff] [blame^] | 34 | if (IS_ENABLED(CONFIG_LOCK_SPI_FLASH_NO_ACCESS)) |
Vladimir Serbinenko | d3b194e | 2015-05-12 12:39:53 +0200 | [diff] [blame] | 35 | lockmask |= (1 << 15); |
| 36 | for (i = 0; i < 20; i += 4) |
| 37 | RCBA32(0x3874 + i) = RCBA32(0x3854 + i) | lockmask; |
| 38 | } |
Nico Huber | d1fb564 | 2013-07-01 16:02:36 +0200 | [diff] [blame] | 39 | |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 40 | /* Set SPI opcode menu */ |
| 41 | RCBA16(0x3894) = SPI_OPPREFIX; |
| 42 | RCBA16(0x3896) = SPI_OPTYPE; |
| 43 | RCBA32(0x3898) = SPI_OPMENU_LOWER; |
| 44 | RCBA32(0x389c) = SPI_OPMENU_UPPER; |
| 45 | |
| 46 | /* Lock SPIBAR */ |
| 47 | RCBA32_OR(0x3804, (1 << 15)); |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 48 | |
Martin Roth | 7a1a3ad | 2017-06-24 21:29:38 -0600 | [diff] [blame] | 49 | #if IS_ENABLED(CONFIG_SPI_FLASH_SMM) |
Duncan Laurie | 312ee0c | 2012-09-09 20:12:32 -0700 | [diff] [blame] | 50 | /* Re-init SPI driver to handle locked BAR */ |
| 51 | spi_init(); |
| 52 | #endif |
| 53 | |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 54 | /* TCLOCKDN: TC Lockdown */ |
| 55 | RCBA32_OR(0x0050, (1 << 31)); |
| 56 | |
| 57 | /* BIOS Interface Lockdown */ |
| 58 | RCBA32_OR(0x3410, (1 << 0)); |
| 59 | |
| 60 | /* Function Disable SUS Well Lockdown */ |
| 61 | RCBA_AND_OR(8, 0x3420, ~0U, (1 << 7)); |
| 62 | |
| 63 | /* Global SMI Lock */ |
Patrick Rudolph | c368620 | 2017-05-03 17:50:00 +0200 | [diff] [blame] | 64 | pci_or_config16(PCH_LPC_DEV, GEN_PMCON_1, 1 << 4); |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 65 | |
| 66 | /* GEN_PMCON Lock */ |
Patrick Rudolph | c368620 | 2017-05-03 17:50:00 +0200 | [diff] [blame] | 67 | pci_or_config8(PCH_LPC_DEV, GEN_PMCON_LOCK, (1 << 1) | (1 << 2)); |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 68 | |
Patrick Rudolph | 7565cf1 | 2017-05-03 18:38:21 +0200 | [diff] [blame] | 69 | /* ETR3: CF9GR Lockdown */ |
| 70 | pci_update_config32(PCH_LPC_DEV, ETR3, ~ETR3_CF9GR, ETR3_CF9LOCK); |
| 71 | |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 72 | /* R/WO registers */ |
| 73 | RCBA32(0x21a4) = RCBA32(0x21a4); |
Kyösti Mälkki | fd98c65 | 2013-07-26 08:50:53 +0300 | [diff] [blame] | 74 | pci_write_config32(PCI_DEV(0, 27, 0), 0x74, |
| 75 | pci_read_config32(PCI_DEV(0, 27, 0), 0x74)); |
Duncan Laurie | 04c5bae | 2012-08-13 09:37:42 -0700 | [diff] [blame] | 76 | |
Dennis Wassenberg | 0c04720 | 2015-09-10 12:03:45 +0200 | [diff] [blame] | 77 | /* TCO_Lock */ |
| 78 | pmbase = smm_get_pmbase(); |
| 79 | tco1_cnt = inw(pmbase + TCO1_CNT); |
| 80 | tco1_cnt |= TCO_LOCK; |
| 81 | outw(tco1_cnt, pmbase + TCO1_CNT); |
| 82 | |
Duncan Laurie | 04c5bae | 2012-08-13 09:37:42 -0700 | [diff] [blame] | 83 | /* Indicate finalize step with post code */ |
| 84 | outb(POST_OS_BOOT, 0x80); |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 85 | } |