blob: 69550ffcfd1833c92d756fe65f5111dcd50bde4e [file] [log] [blame]
Aaron Durbin76c37002012-10-30 09:03:43 -05001##
2## This file is part of the coreboot project.
3##
4## Copyright (C) 2010 Google Inc.
5##
6## This program is free software; you can redistribute it and/or modify
7## it under the terms of the GNU General Public License as published by
8## the Free Software Foundation; version 2 of the License.
9##
10## This program is distributed in the hope that it will be useful,
11## but WITHOUT ANY WARRANTY; without even the implied warranty of
12## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13## GNU General Public License for more details.
14##
Aaron Durbin76c37002012-10-30 09:03:43 -050015
16config NORTHBRIDGE_INTEL_HASWELL
17 bool
Aaron Durbin76c37002012-10-30 09:03:43 -050018 select CPU_INTEL_HASWELL
Kyösti Mälkki15c4ab72013-07-02 11:37:35 +030019 select MMCONF_SUPPORT
Aaron Durbin6d04f0f2012-10-31 22:57:16 -050020 select MMCONF_SUPPORT_DEFAULT
Furquan Shaikh77f48cd2013-08-19 10:16:50 -070021 select INTEL_DDI
22 select INTEL_DP
Vladimir Serbinenkodd2bc3f2014-10-31 09:16:31 +010023 select INTEL_GMA_ACPI
Aaron Durbin76c37002012-10-30 09:03:43 -050024
25if NORTHBRIDGE_INTEL_HASWELL
26
Aaron Durbin6d04f0f2012-10-31 22:57:16 -050027config BOOTBLOCK_NORTHBRIDGE_INIT
28 string
29 default "northbridge/intel/haswell/bootblock.c"
30
Aaron Durbin76c37002012-10-30 09:03:43 -050031config VGA_BIOS_ID
32 string
33 default "8086,0166"
34
Aaron Durbin76c37002012-10-30 09:03:43 -050035config CACHE_MRC_SIZE_KB
36 int
37 default 512
38
Aaron Durbin76c37002012-10-30 09:03:43 -050039config MRC_CACHE_SIZE
40 hex
41 depends on !CHROMEOS
42 default 0x10000
43
44config DCACHE_RAM_BASE
45 hex
Aaron Durbin3d0071b2013-01-18 14:32:50 -060046 default 0xff7c0000
Aaron Durbin76c37002012-10-30 09:03:43 -050047
48config DCACHE_RAM_SIZE
49 hex
Aaron Durbin3d0071b2013-01-18 14:32:50 -060050 default 0x10000
51 help
52 The size of the cache-as-ram region required during bootblock
53 and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE
54 must add up to a power of 2.
Aaron Durbin76c37002012-10-30 09:03:43 -050055
56config DCACHE_RAM_MRC_VAR_SIZE
57 hex
Aaron Durbin3d0071b2013-01-18 14:32:50 -060058 default 0x30000
59 help
60 The amount of cache-as-ram region required by the reference code.
61
62config DCACHE_RAM_ROMSTAGE_STACK_SIZE
63 hex
64 default 0x2000
65 help
66 The amount of anticipated stack usage from the data cache
67 during pre-ram rom stage execution.
Aaron Durbin76c37002012-10-30 09:03:43 -050068
Aaron Durbin76c37002012-10-30 09:03:43 -050069config HAVE_MRC
70 bool "Add a System Agent binary"
71 help
72 Select this option to add a System Agent binary to
73 the resulting coreboot image.
74
75 Note: Without this binary coreboot will not work
76
77config MRC_FILE
78 string "Intel System Agent path and filename"
79 depends on HAVE_MRC
80 default "mrc.bin"
81 help
82 The path and filename of the file to use as System Agent
83 binary.
84
Stefan Reinauerf1aabec2014-01-22 15:16:30 -080085config PRE_GRAPHICS_DELAY
Stefan Reinauer7034b9e2014-02-11 16:18:07 -080086 int "Graphics initialization delay in ms"
Stefan Reinauerf1aabec2014-01-22 15:16:30 -080087 default 0
88 help
89 On some systems, coreboot boots so fast that connected monitors
90 (mostly TVs) won't be able to wake up fast enough to talk to the
91 VBIOS. On those systems we need to wait for a bit before executing
92 the VBIOS.
93
Aaron Durbin76c37002012-10-30 09:03:43 -050094endif