Lijian Zhao | 8109604 | 2017-05-02 18:54:44 -0700 | [diff] [blame] | 1 | config SOC_INTEL_CANNONLAKE |
| 2 | bool |
| 3 | help |
| 4 | Intel Cannonlake support |
| 5 | |
| 6 | if SOC_INTEL_CANNONLAKE |
| 7 | |
| 8 | config CPU_SPECIFIC_OPTIONS |
| 9 | def_bool y |
Lijian Zhao | b3dfcb8 | 2017-08-16 22:18:52 -0700 | [diff] [blame] | 10 | select ACPI_INTEL_HARDWARE_SLEEP_VALUES |
Lijian Zhao | 0e956f2 | 2017-10-22 18:30:39 -0700 | [diff] [blame] | 11 | select ACPI_NHLT |
Lijian Zhao | 8109604 | 2017-05-02 18:54:44 -0700 | [diff] [blame] | 12 | select ARCH_BOOTBLOCK_X86_32 |
Lijian Zhao | 8109604 | 2017-05-02 18:54:44 -0700 | [diff] [blame] | 13 | select ARCH_RAMSTAGE_X86_32 |
| 14 | select ARCH_ROMSTAGE_X86_32 |
Lijian Zhao | dcf99b0 | 2017-07-30 15:40:10 -0700 | [diff] [blame] | 15 | select ARCH_VERSTAGE_X86_32 |
Lijian Zhao | 3211117 | 2017-08-16 11:40:03 -0700 | [diff] [blame] | 16 | select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH |
| 17 | select BOOT_DEVICE_SUPPORTS_WRITES |
Lijian Zhao | 8109604 | 2017-05-02 18:54:44 -0700 | [diff] [blame] | 18 | select C_ENVIRONMENT_BOOTBLOCK |
Lijian Zhao | a06f55b | 2017-10-04 23:08:55 -0700 | [diff] [blame] | 19 | select CACHE_MRC_SETTINGS |
Kyösti Mälkki | 730df3c | 2016-06-18 07:39:31 +0300 | [diff] [blame] | 20 | select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM |
Lijian Zhao | 2b074d9 | 2017-08-17 14:25:24 -0700 | [diff] [blame] | 21 | select COMMON_FADT |
Lijian Zhao | acfc149 | 2017-07-06 15:27:27 -0700 | [diff] [blame] | 22 | select CPU_INTEL_FIRMWARE_INTERFACE_TABLE |
Nick Vaccaro | 69b5cdb | 2017-08-29 19:25:23 -0700 | [diff] [blame] | 23 | select GENERIC_GPIO_LIB |
Abhay kumar | fcf8820 | 2017-09-20 15:17:42 -0700 | [diff] [blame] | 24 | select HAVE_FSP_GOP |
Lijian Zhao | 8109604 | 2017-05-02 18:54:44 -0700 | [diff] [blame] | 25 | select HAVE_HARD_RESET |
| 26 | select HAVE_INTEL_FIRMWARE |
Lijian Zhao | dcf99b0 | 2017-07-30 15:40:10 -0700 | [diff] [blame] | 27 | select HAVE_MONOTONIC_TIMER |
Lijian Zhao | f0eb999 | 2017-09-14 14:51:12 -0700 | [diff] [blame] | 28 | select HAVE_SMI_HANDLER |
Aamir Bohra | e462585 | 2018-05-29 10:52:33 +0530 | [diff] [blame] | 29 | select IDT_IN_EVERY_STAGE |
Abhay Kumar | b0c4cbb | 2017-10-12 11:33:01 -0700 | [diff] [blame] | 30 | select INTEL_GMA_ACPI |
Abhay kumar | fcf8820 | 2017-09-20 15:17:42 -0700 | [diff] [blame] | 31 | select INTEL_GMA_ADD_VBT_DATA_FILE if RUN_FSP_GOP |
Lijian Zhao | a515849 | 2017-08-29 14:37:17 -0700 | [diff] [blame] | 32 | select IOAPIC |
Lijian Zhao | a06f55b | 2017-10-04 23:08:55 -0700 | [diff] [blame] | 33 | select MRC_SETTINGS_PROTECT |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 34 | select PARALLEL_MP |
| 35 | select PARALLEL_MP_AP_WORK |
Lijian Zhao | 8109604 | 2017-05-02 18:54:44 -0700 | [diff] [blame] | 36 | select PLATFORM_USES_FSP2_0 |
Lijian Zhao | 8465a81 | 2017-07-11 12:33:22 -0700 | [diff] [blame] | 37 | select POSTCAR_CONSOLE |
| 38 | select POSTCAR_STAGE |
Lijian Zhao | dcf99b0 | 2017-07-30 15:40:10 -0700 | [diff] [blame] | 39 | select REG_SCRIPT |
Lijian Zhao | f0eb999 | 2017-09-14 14:51:12 -0700 | [diff] [blame] | 40 | select SMM_TSEG |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 41 | select SMP |
Subrata Banik | ac1cd44 | 2018-02-06 15:25:27 +0530 | [diff] [blame] | 42 | select SOC_AHCI_PORT_IMPLEMENTED_INVERT |
Lijian Zhao | 8109604 | 2017-05-02 18:54:44 -0700 | [diff] [blame] | 43 | select SOC_INTEL_COMMON |
Lijian Zhao | 2b074d9 | 2017-08-17 14:25:24 -0700 | [diff] [blame] | 44 | select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE |
Lijian Zhao | 8109604 | 2017-05-02 18:54:44 -0700 | [diff] [blame] | 45 | select SOC_INTEL_COMMON_BLOCK |
Lijian Zhao | 2b074d9 | 2017-08-17 14:25:24 -0700 | [diff] [blame] | 46 | select SOC_INTEL_COMMON_BLOCK_ACPI |
Subrata Banik | c4986eb | 2018-05-09 14:55:09 +0530 | [diff] [blame] | 47 | select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG |
Andrey Petrov | 3e2e050 | 2017-06-05 13:22:24 -0700 | [diff] [blame] | 48 | select SOC_INTEL_COMMON_BLOCK_CPU |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 49 | select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT |
Furquan Shaikh | a5bb716 | 2017-12-20 11:09:04 -0800 | [diff] [blame] | 50 | select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 |
Lijian Zhao | dcf99b0 | 2017-07-30 15:40:10 -0700 | [diff] [blame] | 51 | select SOC_INTEL_COMMON_BLOCK_SA |
Brandon Breitenstein | ae15486 | 2017-08-01 11:32:06 -0700 | [diff] [blame] | 52 | select SOC_INTEL_COMMON_BLOCK_SMM |
| 53 | select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP |
Subrata Banik | f513ceb | 2018-05-17 15:57:43 +0530 | [diff] [blame] | 54 | select SOC_INTEL_COMMON_PCH_BASE |
Lijian Zhao | 0e956f2 | 2017-10-22 18:30:39 -0700 | [diff] [blame] | 55 | select SOC_INTEL_COMMON_NHLT |
Lijian Zhao | dcf99b0 | 2017-07-30 15:40:10 -0700 | [diff] [blame] | 56 | select SOC_INTEL_COMMON_RESET |
Lijian Zhao | f0eb999 | 2017-09-14 14:51:12 -0700 | [diff] [blame] | 57 | select SSE2 |
Lijian Zhao | acfc149 | 2017-07-06 15:27:27 -0700 | [diff] [blame] | 58 | select SUPPORT_CPU_UCODE_IN_CBFS |
Lijian Zhao | dcf99b0 | 2017-07-30 15:40:10 -0700 | [diff] [blame] | 59 | select TSC_CONSTANT_RATE |
| 60 | select TSC_MONOTONIC_TIMER |
| 61 | select UDELAY_TSC |
Subrata Banik | 7455881 | 2018-01-25 11:41:04 +0530 | [diff] [blame] | 62 | select UDK_2017_BINDING |
Subrata Banik | a8733e3 | 2018-01-23 16:40:56 +0530 | [diff] [blame] | 63 | select DISPLAY_FSP_VERSION_INFO |
Lijian Zhao | 8109604 | 2017-05-02 18:54:44 -0700 | [diff] [blame] | 64 | |
| 65 | config UART_DEBUG |
| 66 | bool "Enable UART debug port." |
| 67 | default y |
| 68 | select CONSOLE_SERIAL |
| 69 | select BOOTBLOCK_CONSOLE |
| 70 | select DRIVERS_UART |
Lijian Zhao | d37ebdd | 2017-08-30 20:54:16 -0700 | [diff] [blame] | 71 | select DRIVERS_UART_8250MEM_32 |
| 72 | select NO_UART_ON_SUPERIO |
Lijian Zhao | 8109604 | 2017-05-02 18:54:44 -0700 | [diff] [blame] | 73 | |
Subrata Banik | ce4c9ec | 2017-08-14 13:23:54 +0530 | [diff] [blame] | 74 | config UART_FOR_CONSOLE |
| 75 | int "Index for LPSS UART port to use for console" |
Lijian Zhao | 0c8237a | 2017-09-14 16:25:18 -0700 | [diff] [blame] | 76 | default 2 if DRIVERS_UART_8250MEM_32 |
Subrata Banik | b045d4c | 2017-08-30 11:47:32 +0530 | [diff] [blame] | 77 | default 0 |
Subrata Banik | ce4c9ec | 2017-08-14 13:23:54 +0530 | [diff] [blame] | 78 | help |
| 79 | Index for LPSS UART port to use for console: |
| 80 | 0 = LPSS UART0, 1 = LPSS UART1, 2 = LPSS UART2 |
| 81 | |
Lijian Zhao | 8109604 | 2017-05-02 18:54:44 -0700 | [diff] [blame] | 82 | config DCACHE_RAM_BASE |
| 83 | default 0xfef00000 |
| 84 | |
| 85 | config DCACHE_RAM_SIZE |
| 86 | default 0x40000 |
| 87 | help |
| 88 | The size of the cache-as-ram region required during bootblock |
| 89 | and/or romstage. |
| 90 | |
| 91 | config DCACHE_BSP_STACK_SIZE |
| 92 | hex |
| 93 | default 0x4000 |
| 94 | help |
| 95 | The amount of anticipated stack usage in CAR by bootblock and |
| 96 | other stages. |
| 97 | |
Furquan Shaikh | c0257dd | 2018-05-02 23:29:04 -0700 | [diff] [blame] | 98 | config IFD_CHIPSET |
| 99 | string |
| 100 | default "cnl" |
| 101 | |
Pratik Prajapati | 9027e1b | 2017-08-23 17:37:43 -0700 | [diff] [blame] | 102 | config IED_REGION_SIZE |
| 103 | hex |
| 104 | default 0x400000 |
| 105 | |
John Zhao | 7492bcb | 2018-02-01 15:56:28 -0800 | [diff] [blame] | 106 | config HEAP_SIZE |
| 107 | hex |
| 108 | default 0x8000 |
| 109 | |
Lijian Zhao | 0e956f2 | 2017-10-22 18:30:39 -0700 | [diff] [blame] | 110 | config NHLT_DMIC_1CH_16B |
| 111 | bool |
| 112 | depends on ACPI_NHLT |
| 113 | default n |
| 114 | help |
| 115 | Include DSP firmware settings for 1 channel 16B DMIC array. |
| 116 | |
| 117 | config NHLT_DMIC_2CH_16B |
| 118 | bool |
| 119 | depends on ACPI_NHLT |
| 120 | default n |
| 121 | help |
| 122 | Include DSP firmware settings for 2 channel 16B DMIC array. |
| 123 | |
| 124 | config NHLT_DMIC_4CH_16B |
| 125 | bool |
| 126 | depends on ACPI_NHLT |
| 127 | default n |
| 128 | help |
| 129 | Include DSP firmware settings for 4 channel 16B DMIC array. |
| 130 | |
| 131 | config NHLT_MAX98357 |
| 132 | bool |
| 133 | depends on ACPI_NHLT |
| 134 | default n |
| 135 | help |
| 136 | Include DSP firmware settings for headset codec. |
| 137 | |
N, Harshapriya | 4a1ee4b | 2017-11-28 14:29:26 -0800 | [diff] [blame] | 138 | config NHLT_MAX98373 |
| 139 | bool |
| 140 | depends on ACPI_NHLT |
| 141 | default n |
| 142 | help |
| 143 | Include DSP firmware settings for headset codec. |
| 144 | |
Lijian Zhao | 0e956f2 | 2017-10-22 18:30:39 -0700 | [diff] [blame] | 145 | config NHLT_DA7219 |
| 146 | bool |
| 147 | depends on ACPI_NHLT |
| 148 | default n |
| 149 | help |
| 150 | Include DSP firmware settings for headset codec. |
| 151 | |
Pratik Prajapati | c8c741d | 2017-08-29 11:38:42 -0700 | [diff] [blame] | 152 | config MAX_ROOT_PORTS |
| 153 | int |
Lijian Zhao | c85890d | 2017-10-20 09:19:07 -0700 | [diff] [blame] | 154 | default 16 |
Pratik Prajapati | c8c741d | 2017-08-29 11:38:42 -0700 | [diff] [blame] | 155 | |
Pratik Prajapati | 9027e1b | 2017-08-23 17:37:43 -0700 | [diff] [blame] | 156 | config SMM_TSEG_SIZE |
| 157 | hex |
| 158 | default 0x800000 |
| 159 | |
Subrata Banik | e66600e | 2018-05-10 17:23:56 +0530 | [diff] [blame] | 160 | config SMM_RESERVED_SIZE |
| 161 | hex |
| 162 | default 0x200000 |
| 163 | |
Lijian Zhao | 8109604 | 2017-05-02 18:54:44 -0700 | [diff] [blame] | 164 | config PCR_BASE_ADDRESS |
| 165 | hex |
| 166 | default 0xfd000000 |
| 167 | help |
| 168 | This option allows you to select MMIO Base Address of sideband bus. |
| 169 | |
Andrey Petrov | 3e2e050 | 2017-06-05 13:22:24 -0700 | [diff] [blame] | 170 | config CPU_BCLK_MHZ |
| 171 | int |
| 172 | default 100 |
| 173 | |
Nick Vaccaro | 780a1c4 | 2017-12-22 22:50:57 -0800 | [diff] [blame] | 174 | config SOC_INTEL_CANNONLAKE_LPDDR4_INIT |
| 175 | bool |
| 176 | default n |
| 177 | |
Aaron Durbin | 551e4be | 2018-04-10 09:24:54 -0600 | [diff] [blame] | 178 | config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ |
Lijian Zhao | f388561 | 2017-11-09 15:01:33 -0800 | [diff] [blame] | 179 | int |
| 180 | default 120 |
| 181 | |
Chris Ching | b8dc63b | 2017-12-06 14:26:15 -0700 | [diff] [blame] | 182 | config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ |
| 183 | int |
Lijian Zhao | e09ba47 | 2018-04-10 10:33:05 -0700 | [diff] [blame] | 184 | default 133 |
Chris Ching | b8dc63b | 2017-12-06 14:26:15 -0700 | [diff] [blame] | 185 | |
Lijian Zhao | 3211117 | 2017-08-16 11:40:03 -0700 | [diff] [blame] | 186 | config SOC_INTEL_COMMON_BLOCK_GSPI_MAX |
| 187 | int |
| 188 | default 3 |
| 189 | |
Subrata Banik | c4986eb | 2018-05-09 14:55:09 +0530 | [diff] [blame] | 190 | config SOC_INTEL_I2C_DEV_MAX |
| 191 | int |
| 192 | default 6 |
| 193 | |
Lijian Zhao | 8465a81 | 2017-07-11 12:33:22 -0700 | [diff] [blame] | 194 | # Clock divider parameters for 115200 baud rate |
| 195 | config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL |
| 196 | hex |
| 197 | default 0x30 |
| 198 | |
| 199 | config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL |
| 200 | hex |
| 201 | default 0xc35 |
| 202 | |
Lijian Zhao | 6d7063c | 2017-08-29 17:26:48 -0700 | [diff] [blame] | 203 | config CHROMEOS |
| 204 | select CHROMEOS_RAMOOPS_DYNAMIC |
| 205 | |
| 206 | config VBOOT |
| 207 | select VBOOT_SEPARATE_VERSTAGE |
| 208 | select VBOOT_OPROM_MATTERS |
| 209 | select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT |
| 210 | select VBOOT_STARTS_IN_BOOTBLOCK |
| 211 | select VBOOT_VBNV_CMOS |
| 212 | select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH |
| 213 | |
Aaron Durbin | 4a8f45f | 2017-10-05 17:05:36 -0600 | [diff] [blame] | 214 | config C_ENV_BOOTBLOCK_SIZE |
| 215 | hex |
Lijian Zhao | 031020e | 2017-12-15 12:58:07 -0800 | [diff] [blame] | 216 | default 0x8000 |
Aaron Durbin | 4a8f45f | 2017-10-05 17:05:36 -0600 | [diff] [blame] | 217 | |
Subrata Banik | 9e3ba21 | 2018-01-08 15:28:26 +0530 | [diff] [blame] | 218 | choice |
| 219 | prompt "Cache-as-ram implementation" |
| 220 | default USE_CANNONLAKE_CAR_NEM_ENHANCED if MAINBOARD_HAS_CHROMEOS |
| 221 | default USE_CANNONLAKE_FSP_CAR |
| 222 | help |
| 223 | This option allows you to select how cache-as-ram (CAR) is set up. |
| 224 | |
| 225 | config USE_CANNONLAKE_CAR_NEM_ENHANCED |
| 226 | bool "Enhanced Non-evict mode" |
| 227 | select SOC_INTEL_COMMON_BLOCK_CAR |
| 228 | select INTEL_CAR_NEM_ENHANCED |
| 229 | help |
| 230 | A current limitation of NEM (Non-Evict mode) is that code and data |
| 231 | sizes are derived from the requirement to not write out any modified |
| 232 | cache line. With NEM, if there is no physical memory behind the |
| 233 | cached area, the modified data will be lost and NEM results will be |
| 234 | inconsistent. ENHANCED NEM guarantees that modified data is always |
| 235 | kept in cache while clean data is replaced. |
| 236 | |
| 237 | config USE_CANNONLAKE_FSP_CAR |
| 238 | bool "Use FSP CAR" |
| 239 | select FSP_CAR |
| 240 | help |
| 241 | Use FSP APIs to initialize and tear down the Cache-As-Ram. |
| 242 | |
| 243 | endchoice |
| 244 | |
Lijian Zhao | 8109604 | 2017-05-02 18:54:44 -0700 | [diff] [blame] | 245 | endif |