Angel Pons | 16f6aa8 | 2020-04-05 15:47:21 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 2 | |
| 3 | #ifndef _SOC_CHIP_H_ |
| 4 | #define _SOC_CHIP_H_ |
| 5 | |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 6 | #include <drivers/i2c/designware/dw_i2c.h> |
Tim Crawford | 1724b57 | 2021-09-21 21:50:49 -0600 | [diff] [blame] | 7 | #include <drivers/intel/gma/gma.h> |
Ronak Kanabar | 1c2313d | 2019-12-16 18:43:52 +0530 | [diff] [blame] | 8 | #include <intelblocks/cfg.h> |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 9 | #include <intelblocks/gpio.h> |
| 10 | #include <intelblocks/gspi.h> |
Sean Rhodes | f71d8c9 | 2021-08-25 12:30:55 +0100 | [diff] [blame] | 11 | #include <intelblocks/lpc_lib.h> |
Eric Lai | de2ab41 | 2021-01-11 16:14:14 +0800 | [diff] [blame] | 12 | #include <intelblocks/pcie_rp.h> |
Sumeet R Pawnikar | d213246 | 2020-05-15 15:55:37 +0530 | [diff] [blame] | 13 | #include <intelblocks/power_limit.h> |
Tim Wawrzynczak | 59a621a | 2021-03-22 10:43:42 -0600 | [diff] [blame] | 14 | #include <intelblocks/tcss.h> |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 15 | #include <soc/gpe.h> |
Michael Niewöhner | 8913b78 | 2020-12-11 22:13:44 +0100 | [diff] [blame] | 16 | #include <soc/gpio.h> |
Ronak Kanabar | 1c2313d | 2019-12-16 18:43:52 +0530 | [diff] [blame] | 17 | #include <soc/pch.h> |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 18 | #include <soc/pci_devs.h> |
| 19 | #include <soc/pmc.h> |
| 20 | #include <soc/serialio.h> |
| 21 | #include <soc/usb.h> |
Elyes HAOUAS | 23a60fa | 2020-07-22 11:44:29 +0200 | [diff] [blame] | 22 | #include <types.h> |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 23 | |
Srinidhi N Kaushik | 2f2c7eb | 2020-01-02 16:11:27 -0800 | [diff] [blame] | 24 | #define MAX_HD_AUDIO_DMIC_LINKS 2 |
| 25 | #define MAX_HD_AUDIO_SNDW_LINKS 4 |
| 26 | #define MAX_HD_AUDIO_SSP_LINKS 6 |
| 27 | |
Tim Wawrzynczak | 2dcca0f | 2020-06-16 10:50:47 -0600 | [diff] [blame] | 28 | /* The first two are for TGL-U */ |
Jeremy Soller | 301b09b | 2021-08-12 10:49:58 -0600 | [diff] [blame] | 29 | enum soc_intel_tigerlake_power_limits { |
| 30 | POWER_LIMITS_U_2_CORE, |
| 31 | POWER_LIMITS_U_4_CORE, |
| 32 | POWER_LIMITS_Y_2_CORE, |
| 33 | POWER_LIMITS_Y_4_CORE, |
| 34 | POWER_LIMITS_H_6_CORE, |
| 35 | POWER_LIMITS_H_8_CORE, |
| 36 | POWER_LIMITS_MAX |
| 37 | }; |
Tim Wawrzynczak | 2dcca0f | 2020-06-16 10:50:47 -0600 | [diff] [blame] | 38 | |
Venkata Krishna Nimmagadda | e18f719 | 2020-05-15 00:13:40 -0700 | [diff] [blame] | 39 | /* |
| 40 | * Enable External V1P05 Rail in: BIT0:S0i1/S0i2, |
| 41 | * BIT1:S0i3, BIT2:S3, BIT3:S4, BIT4:S5 |
| 42 | */ |
| 43 | enum fivr_enable_states { |
| 44 | FIVR_ENABLE_S0i1_S0i2 = BIT(0), |
| 45 | FIVR_ENABLE_S0i3 = BIT(1), |
| 46 | FIVR_ENABLE_S3 = BIT(2), |
| 47 | FIVR_ENABLE_S4 = BIT(3), |
| 48 | FIVR_ENABLE_S5 = BIT(4), |
| 49 | }; |
| 50 | |
| 51 | /* |
| 52 | * Enable the following for External V1p05 rail |
| 53 | * BIT1: Normal Active voltage supported |
| 54 | * BIT2: Minimum active voltage supported |
| 55 | * BIT3: Minimum Retention voltage supported |
| 56 | */ |
| 57 | enum fivr_voltage_supported { |
| 58 | FIVR_VOLTAGE_NORMAL = BIT(1), |
| 59 | FIVR_VOLTAGE_MIN_ACTIVE = BIT(2), |
| 60 | FIVR_VOLTAGE_MIN_RETENTION = BIT(3), |
| 61 | }; |
| 62 | |
| 63 | #define FIVR_ENABLE_ALL_SX (FIVR_ENABLE_S0i1_S0i2 | FIVR_ENABLE_S0i3 | \ |
| 64 | FIVR_ENABLE_S3 | FIVR_ENABLE_S4 | FIVR_ENABLE_S5) |
| 65 | |
Jes Klinke | 6fd87ff | 2020-08-10 13:30:40 -0700 | [diff] [blame] | 66 | /* Bit values for use in LpmStateEnableMask. */ |
| 67 | enum lpm_state_mask { |
| 68 | LPM_S0i2_0 = BIT(0), |
| 69 | LPM_S0i2_1 = BIT(1), |
| 70 | LPM_S0i2_2 = BIT(2), |
| 71 | LPM_S0i3_0 = BIT(3), |
| 72 | LPM_S0i3_1 = BIT(4), |
| 73 | LPM_S0i3_2 = BIT(5), |
| 74 | LPM_S0i3_3 = BIT(6), |
| 75 | LPM_S0i3_4 = BIT(7), |
| 76 | LPM_S0iX_ALL = LPM_S0i2_0 | LPM_S0i2_1 | LPM_S0i2_2 |
| 77 | | LPM_S0i3_0 | LPM_S0i3_1 | LPM_S0i3_2 | LPM_S0i3_3 | LPM_S0i3_4, |
| 78 | }; |
| 79 | |
Shaunak Saha | 0d0f43f | 2020-09-02 15:37:00 -0700 | [diff] [blame] | 80 | /* |
Shaunak Saha | 0d0f43f | 2020-09-02 15:37:00 -0700 | [diff] [blame] | 81 | * Slew Rate configuration for Deep Package C States for VR domain. |
| 82 | * They are fast time divided by 2. |
| 83 | * 0 - Fast/2 |
| 84 | * 1 - Fast/4 |
| 85 | * 2 - Fast/8 |
| 86 | * 3 - Fast/16 |
| 87 | */ |
| 88 | enum slew_rate { |
| 89 | SLEW_FAST_2, |
| 90 | SLEW_FAST_4, |
| 91 | SLEW_FAST_8, |
| 92 | SLEW_FAST_16 |
| 93 | }; |
| 94 | |
Angel Pons | da4e1d7 | 2022-05-04 17:08:11 +0200 | [diff] [blame] | 95 | enum ddi_port_config { |
| 96 | DDI_PORT_CFG_NO_LFP = 0, |
| 97 | DDI_PORT_CFG_EDP = 1, |
| 98 | DDI_PORT_CFG_MIPI_DSI = 2, |
| 99 | }; |
| 100 | |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 101 | struct soc_intel_tigerlake_config { |
| 102 | |
| 103 | /* Common struct containing soc config data required by common code */ |
| 104 | struct soc_intel_common_config common_soc_config; |
| 105 | |
Sumeet R Pawnikar | d213246 | 2020-05-15 15:55:37 +0530 | [diff] [blame] | 106 | /* Common struct containing power limits configuration information */ |
Tim Wawrzynczak | 2dcca0f | 2020-06-16 10:50:47 -0600 | [diff] [blame] | 107 | struct soc_power_limits_config power_limits_config[POWER_LIMITS_MAX]; |
Sumeet R Pawnikar | d213246 | 2020-05-15 15:55:37 +0530 | [diff] [blame] | 108 | |
Derek Huang | ed6bda2 | 2021-01-27 17:01:00 +0800 | [diff] [blame] | 109 | /* Configuration for boot TDP selection; */ |
| 110 | uint8_t ConfigTdpLevel; |
| 111 | |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 112 | /* Gpio group routed to each dword of the GPE0 block. Values are |
Ravi Sarawadi | 2fd4972 | 2019-12-16 23:41:36 -0800 | [diff] [blame] | 113 | * of the form PMC_GPP_[A:U] or GPD. */ |
| 114 | uint8_t pmc_gpe0_dw0; /* GPE0_31_0 STS/EN */ |
| 115 | uint8_t pmc_gpe0_dw1; /* GPE0_63_32 STS/EN */ |
| 116 | uint8_t pmc_gpe0_dw2; /* GPE0_95_64 STS/EN */ |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 117 | |
Sean Rhodes | f71d8c9 | 2021-08-25 12:30:55 +0100 | [diff] [blame] | 118 | /* LPC fixed enables and ranges */ |
| 119 | uint32_t lpc_ioe; |
| 120 | |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 121 | /* Generic IO decode ranges */ |
| 122 | uint32_t gen1_dec; |
| 123 | uint32_t gen2_dec; |
| 124 | uint32_t gen3_dec; |
| 125 | uint32_t gen4_dec; |
| 126 | |
| 127 | /* Enable S0iX support */ |
| 128 | int s0ix_enable; |
Jes Klinke | 6fd87ff | 2020-08-10 13:30:40 -0700 | [diff] [blame] | 129 | /* S0iX: Selectively disable individual sub-states, by default all are enabled. */ |
| 130 | enum lpm_state_mask LpmStateDisableMask; |
| 131 | |
John Zhao | 8aac881 | 2020-05-16 13:06:25 -0700 | [diff] [blame] | 132 | /* Support for TCSS xhci, xdci, TBT PCIe root ports and DMA controllers */ |
John Zhao | bd615d6 | 2020-07-27 13:22:11 -0700 | [diff] [blame] | 133 | uint8_t TcssD3HotDisable; |
John Zhao | 8aac881 | 2020-05-16 13:06:25 -0700 | [diff] [blame] | 134 | /* Support for TBT PCIe root ports and DMA controllers with D3Hot->D3Cold */ |
John Zhao | bd615d6 | 2020-07-27 13:22:11 -0700 | [diff] [blame] | 135 | uint8_t TcssD3ColdDisable; |
John Zhao | 8aac881 | 2020-05-16 13:06:25 -0700 | [diff] [blame] | 136 | |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 137 | /* Enable DPTF support */ |
| 138 | int dptf_enable; |
| 139 | |
| 140 | /* Deep SX enable for both AC and DC */ |
| 141 | int deep_s3_enable_ac; |
| 142 | int deep_s3_enable_dc; |
| 143 | int deep_s5_enable_ac; |
| 144 | int deep_s5_enable_dc; |
| 145 | |
| 146 | /* Deep Sx Configuration |
| 147 | * DSX_EN_WAKE_PIN - Enable WAKE# pin |
| 148 | * DSX_EN_LAN_WAKE_PIN - Enable LAN_WAKE# pin |
| 149 | * DSX_DIS_AC_PRESENT_PD - Disable pull-down on AC_PRESENT pin */ |
| 150 | uint32_t deep_sx_config; |
| 151 | |
| 152 | /* TCC activation offset */ |
| 153 | uint32_t tcc_offset; |
| 154 | |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 155 | /* System Agent dynamic frequency support. Only effects ULX/ULT CPUs. |
| 156 | * When enabled memory will be training at two different frequencies. |
Ravi Sarawadi | 2fd4972 | 2019-12-16 23:41:36 -0800 | [diff] [blame] | 157 | * 0:Disabled, 1:FixedPoint0, 2:FixedPoint1, 3:FixedPoint2, |
| 158 | * 4:FixedPoint3, 5:Enabled */ |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 159 | enum { |
| 160 | SaGv_Disabled, |
Ravi Sarawadi | 2fd4972 | 2019-12-16 23:41:36 -0800 | [diff] [blame] | 161 | SaGv_FixedPoint0, |
| 162 | SaGv_FixedPoint1, |
| 163 | SaGv_FixedPoint2, |
| 164 | SaGv_FixedPoint3, |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 165 | SaGv_Enabled, |
| 166 | } SaGv; |
| 167 | |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 168 | /* Rank Margin Tool. 1:Enable, 0:Disable */ |
| 169 | uint8_t RMT; |
| 170 | |
David Wu | 63ce260 | 2020-06-11 14:46:24 +0800 | [diff] [blame] | 171 | /* Command Pins Mirrored */ |
| 172 | uint32_t CmdMirror; |
| 173 | |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 174 | /* USB related */ |
| 175 | struct usb2_port_config usb2_ports[16]; |
| 176 | struct usb3_port_config usb3_ports[10]; |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 177 | /* Wake Enable Bitmap for USB2 ports */ |
| 178 | uint16_t usb2_wake_enable_bitmap; |
| 179 | /* Wake Enable Bitmap for USB3 ports */ |
| 180 | uint16_t usb3_wake_enable_bitmap; |
Derek Huang | 8056187 | 2021-03-15 12:11:19 +0800 | [diff] [blame] | 181 | /* PCH USB2 PHY Power Gating disable */ |
| 182 | uint8_t usb2_phy_sus_pg_disable; |
Nick Vaccaro | 4b3e06e | 2021-05-11 16:39:32 -0700 | [diff] [blame] | 183 | /* Program OC pins for TCSS */ |
| 184 | struct tcss_port_config tcss_ports[MAX_TYPE_C_PORTS]; |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 185 | |
Shaunak Saha | 0d0f43f | 2020-09-02 15:37:00 -0700 | [diff] [blame] | 186 | /* |
| 187 | * Acoustic Noise Mitigation |
| 188 | * 0 - Disable |
| 189 | * 1 - Enable noise mitigation |
| 190 | */ |
| 191 | uint8_t AcousticNoiseMitigation; |
| 192 | |
| 193 | /* |
| 194 | * Offset 0x054B - Disable Fast Slew Rate for Deep Package |
Shaunak Saha | 82d5123 | 2021-02-17 23:26:43 -0800 | [diff] [blame] | 195 | * C States for VCCin in VR domain. Disable Fast Slew Rate |
| 196 | * for Deep Package C States based on Acoustic Noise |
| 197 | * Mitigation feature enabled. |
Shaunak Saha | 0d0f43f | 2020-09-02 15:37:00 -0700 | [diff] [blame] | 198 | * 0 - False |
| 199 | * 1 - True |
| 200 | */ |
Shaunak Saha | 82d5123 | 2021-02-17 23:26:43 -0800 | [diff] [blame] | 201 | uint8_t FastPkgCRampDisable; |
Shaunak Saha | 0d0f43f | 2020-09-02 15:37:00 -0700 | [diff] [blame] | 202 | |
| 203 | /* |
| 204 | * Offset 0x0550 - Slew Rate configuration for Deep Package |
Shaunak Saha | 82d5123 | 2021-02-17 23:26:43 -0800 | [diff] [blame] | 205 | * C States for VCCin in VR domain. Slew Rate configuration |
| 206 | * for Deep Package C States for VR domain based on Acoustic |
| 207 | * Noise Mitigation feature enabled. |
Shaunak Saha | 0d0f43f | 2020-09-02 15:37:00 -0700 | [diff] [blame] | 208 | */ |
Shaunak Saha | 82d5123 | 2021-02-17 23:26:43 -0800 | [diff] [blame] | 209 | uint8_t SlowSlewRate; |
Shaunak Saha | 0d0f43f | 2020-09-02 15:37:00 -0700 | [diff] [blame] | 210 | |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 211 | /* SATA related */ |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 212 | uint8_t SataMode; |
| 213 | uint8_t SataSalpSupport; |
| 214 | uint8_t SataPortsEnable[8]; |
| 215 | uint8_t SataPortsDevSlp[8]; |
| 216 | |
Shaunak Saha | 1a8949c | 2020-06-08 18:59:47 -0700 | [diff] [blame] | 217 | /* |
| 218 | * Enable(0)/Disable(1) SATA Power Optimizer on PCH side. |
| 219 | * Default 0. Setting this to 1 disables the SATA Power Optimizer. |
| 220 | */ |
| 221 | uint8_t SataPwrOptimizeDisable; |
| 222 | |
| 223 | /* |
| 224 | * SATA Port Enable Dito Config. |
| 225 | * Enable DEVSLP Idle Timeout settings (DmVal, DitoVal). |
| 226 | */ |
| 227 | uint8_t SataPortsEnableDitoConfig[8]; |
| 228 | |
| 229 | /* SataPortsDmVal is the DITO multiplier. Default is 15. */ |
| 230 | uint8_t SataPortsDmVal[8]; |
| 231 | /* SataPortsDitoVal is the DEVSLP Idle Timeout, default is 625ms */ |
| 232 | uint16_t SataPortsDitoVal[8]; |
| 233 | |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 234 | /* Audio related */ |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 235 | uint8_t PchHdaDspEnable; |
Srinidhi N Kaushik | 2f2c7eb | 2020-01-02 16:11:27 -0800 | [diff] [blame] | 236 | uint8_t PchHdaAudioLinkHdaEnable; |
| 237 | uint8_t PchHdaAudioLinkDmicEnable[MAX_HD_AUDIO_DMIC_LINKS]; |
| 238 | uint8_t PchHdaAudioLinkSspEnable[MAX_HD_AUDIO_SSP_LINKS]; |
| 239 | uint8_t PchHdaAudioLinkSndwEnable[MAX_HD_AUDIO_SNDW_LINKS]; |
Eric Lai | 54b706e | 2020-05-14 13:58:01 +0800 | [diff] [blame] | 240 | uint8_t PchHdaIDispCodecDisconnect; |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 241 | |
| 242 | /* PCIe Root Ports */ |
| 243 | uint8_t PcieRpEnable[CONFIG_MAX_ROOT_PORTS]; |
Wonkyu Kim | c66c153 | 2020-05-27 13:34:04 -0700 | [diff] [blame] | 244 | uint8_t PcieRpHotPlug[CONFIG_MAX_ROOT_PORTS]; |
Michael Niewöhner | 45b6080 | 2022-01-08 20:47:11 +0100 | [diff] [blame] | 245 | /* Implemented as slot or built-in? */ |
| 246 | uint8_t PcieRpSlotImplemented[CONFIG_MAX_ROOT_PORTS]; |
Elyes HAOUAS | 79ccc69 | 2020-02-24 13:43:39 +0100 | [diff] [blame] | 247 | /* PCIe output clocks type to PCIe devices. |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 248 | * 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use, |
| 249 | * 0xFF: not used */ |
Rizwan Qureshi | a979460 | 2021-04-08 20:31:47 +0530 | [diff] [blame] | 250 | uint8_t PcieClkSrcUsage[CONFIG_MAX_PCIE_CLOCK_SRC]; |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 251 | /* PCIe ClkReq-to-ClkSrc mapping, number of clkreq signal assigned to |
| 252 | * clksrc. */ |
Rizwan Qureshi | a979460 | 2021-04-08 20:31:47 +0530 | [diff] [blame] | 253 | uint8_t PcieClkSrcClkReq[CONFIG_MAX_PCIE_CLOCK_SRC]; |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 254 | |
Meera Ravindranath | 0d6cc22 | 2020-04-29 12:19:33 +0530 | [diff] [blame] | 255 | /* Probe CLKREQ# signal before enabling CLKREQ# based power management.*/ |
| 256 | uint8_t PcieRpClkReqDetect[CONFIG_MAX_ROOT_PORTS]; |
| 257 | |
Duncan Laurie | 17e905ac | 2020-10-27 17:57:13 -0700 | [diff] [blame] | 258 | /* Enable PCIe Precision Time Measurement for Root Ports (disabled by default) */ |
| 259 | uint8_t PciePtm[CONFIG_MAX_ROOT_PORTS]; |
| 260 | |
Wonkyu Kim | 84b4882 | 2020-03-09 13:34:38 -0700 | [diff] [blame] | 261 | /* PCIe RP L1 substate */ |
Eric Lai | de2ab41 | 2021-01-11 16:14:14 +0800 | [diff] [blame] | 262 | enum L1_substates_control PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS]; |
Wonkyu Kim | 84b4882 | 2020-03-09 13:34:38 -0700 | [diff] [blame] | 263 | |
Wonkyu Kim | 5943117 | 2020-04-07 20:45:28 -0700 | [diff] [blame] | 264 | /* PCIe LTR: Enable (1) / Disable (0) */ |
| 265 | uint8_t PcieRpLtrEnable[CONFIG_MAX_ROOT_PORTS]; |
| 266 | |
| 267 | /* PCIE RP Advanced Error Report: Enable (1) / Disable (0) */ |
| 268 | uint8_t PcieRpAdvancedErrorReporting[CONFIG_MAX_ROOT_PORTS]; |
| 269 | |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 270 | /* Gfx related */ |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 271 | uint8_t SkipExtGfxScan; |
| 272 | |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 273 | /* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */ |
| 274 | uint8_t eist_enable; |
| 275 | |
| 276 | /* Enable C6 DRAM */ |
| 277 | uint8_t enable_c6dram; |
Michael Niewöhner | d2fadda | 2021-09-27 19:26:20 +0200 | [diff] [blame] | 278 | |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 279 | /* |
| 280 | * SerialIO device mode selection: |
| 281 | * PchSerialIoDisabled, |
| 282 | * PchSerialIoPci, |
| 283 | * PchSerialIoHidden, |
| 284 | * PchSerialIoLegacyUart, |
| 285 | * PchSerialIoSkipInit |
| 286 | */ |
| 287 | uint8_t SerialIoI2cMode[CONFIG_SOC_INTEL_I2C_DEV_MAX]; |
| 288 | uint8_t SerialIoGSpiMode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; |
| 289 | uint8_t SerialIoUartMode[CONFIG_SOC_INTEL_UART_DEV_MAX]; |
| 290 | /* |
| 291 | * GSPIn Default Chip Select Mode: |
| 292 | * 0:Hardware Mode, |
| 293 | * 1:Software Mode |
| 294 | */ |
| 295 | uint8_t SerialIoGSpiCsMode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; |
| 296 | /* |
| 297 | * GSPIn Default Chip Select State: |
| 298 | * 0: Low, |
| 299 | * 1: High |
| 300 | */ |
| 301 | uint8_t SerialIoGSpiCsState[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; |
| 302 | |
Ronak Kanabar | 35d7843 | 2020-03-04 19:03:47 +0530 | [diff] [blame] | 303 | /* |
| 304 | * TraceHubMode config |
| 305 | * 0: Disable, 1: Target Debugger Mode, 2: Host Debugger Mode |
| 306 | */ |
| 307 | uint8_t TraceHubMode; |
| 308 | |
Maulik V Vaghela | dba6c4c | 2020-01-17 18:56:58 +0530 | [diff] [blame] | 309 | /* Debug interface selection */ |
| 310 | enum { |
| 311 | DEBUG_INTERFACE_RAM = (1 << 0), |
Subrata Banik | 7be0df8 | 2020-04-30 12:23:16 +0530 | [diff] [blame] | 312 | DEBUG_INTERFACE_UART_8250IO = (1 << 1), |
Maulik V Vaghela | dba6c4c | 2020-01-17 18:56:58 +0530 | [diff] [blame] | 313 | DEBUG_INTERFACE_USB3 = (1 << 3), |
Subrata Banik | 7be0df8 | 2020-04-30 12:23:16 +0530 | [diff] [blame] | 314 | DEBUG_INTERFACE_LPSS_SERIAL_IO = (1 << 4), |
Maulik V Vaghela | dba6c4c | 2020-01-17 18:56:58 +0530 | [diff] [blame] | 315 | DEBUG_INTERFACE_TRACEHUB = (1 << 5), |
| 316 | } debug_interface_flag; |
| 317 | |
Cliff Huang | b34be4d | 2021-02-04 15:37:24 -0800 | [diff] [blame] | 318 | /* CNVi BT Core Enable/Disable */ |
| 319 | bool CnviBtCore; |
| 320 | |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 321 | /* CNVi BT Audio Offload: Enable/Disable BT Audio Offload. */ |
Angel Pons | 98521c5 | 2021-03-01 21:16:49 +0100 | [diff] [blame] | 322 | bool CnviBtAudioOffload; |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 323 | |
John Zhao | 8aac881 | 2020-05-16 13:06:25 -0700 | [diff] [blame] | 324 | /* TCSS USB */ |
Wonkyu Kim | 1ab6f0c | 2020-01-28 22:06:37 -0800 | [diff] [blame] | 325 | uint8_t TcssXhciEn; |
| 326 | uint8_t TcssXdciEn; |
| 327 | |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 328 | /* |
Brandon Breitenstein | bf50c31 | 2020-12-21 14:55:38 -0800 | [diff] [blame] | 329 | * Specifies which Type-C Ports are enabled on the system |
| 330 | * each bit represents a port starting at 0 |
| 331 | * Example: set value to 0x3 for ports 0 and 1 to be enabled |
| 332 | */ |
| 333 | uint8_t UsbTcPortEn; |
| 334 | |
| 335 | /* |
Tim Wawrzynczak | 59a621a | 2021-03-22 10:43:42 -0600 | [diff] [blame] | 336 | * These GPIOs will be programmed by the IOM to handle biasing of the |
| 337 | * Type-C aux (SBU) signals when certain alternate modes are used. |
| 338 | * `pad_auxn_dc` should be assigned to the GPIO pad providing negative |
| 339 | * bias (name usually contains `AUXN_DC` or `AUX_N`); similarly, |
| 340 | * `pad_auxp_dc` should be assigned to the GPIO providing positive bias |
| 341 | * (name often contains `AUXP_DC` or `_AUX_P`). |
Brandon Breitenstein | 71d365d | 2020-04-06 15:31:34 -0700 | [diff] [blame] | 342 | */ |
Tim Wawrzynczak | 59a621a | 2021-03-22 10:43:42 -0600 | [diff] [blame] | 343 | struct typec_aux_bias_pads typec_aux_bias_pads[MAX_TYPE_C_PORTS]; |
Brandon Breitenstein | 71d365d | 2020-04-06 15:31:34 -0700 | [diff] [blame] | 344 | |
| 345 | /* |
Brandon Breitenstein | fc93237 | 2020-03-11 14:07:23 -0700 | [diff] [blame] | 346 | * SOC Aux orientation override: |
| 347 | * This is a bitfield that corresponds to up to 4 TCSS ports on TGL. |
| 348 | * Even numbered bits (0, 2, 4, 6) control the retimer being handled by SOC. |
| 349 | * Odd numbered bits (1, 3, 5, 7) control the orientation of the physical aux lines |
| 350 | * on the motherboard. |
| 351 | */ |
| 352 | uint16_t TcssAuxOri; |
| 353 | |
John Zhao | 92a3a30 | 2020-06-03 13:06:24 -0700 | [diff] [blame] | 354 | /* Connect Topology Command timeout value */ |
| 355 | uint16_t ITbtConnectTopologyTimeoutInMs; |
| 356 | |
Brandon Breitenstein | fc93237 | 2020-03-11 14:07:23 -0700 | [diff] [blame] | 357 | /* |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 358 | * Override GPIO PM configuration: |
| 359 | * 0: Use FSP default GPIO PM program, |
| 360 | * 1: coreboot to override GPIO PM program |
| 361 | */ |
| 362 | uint8_t gpio_override_pm; |
| 363 | |
| 364 | /* |
| 365 | * GPIO PM configuration: 0 to disable, 1 to enable power gating |
| 366 | * Bit 6-7: Reserved |
| 367 | * Bit 5: MISCCFG_GPSIDEDPCGEN |
| 368 | * Bit 4: MISCCFG_GPRCOMPCDLCGEN |
| 369 | * Bit 3: MISCCFG_GPRTCDLCGEN |
| 370 | * Bit 2: MISCCFG_GSXLCGEN |
| 371 | * Bit 1: MISCCFG_GPDPCGEN |
| 372 | * Bit 0: MISCCFG_GPDLCGEN |
| 373 | */ |
| 374 | uint8_t gpio_pm[TOTAL_GPIO_COMM]; |
Wonkyu Kim | 9f2e3ad | 2020-01-23 00:06:07 -0800 | [diff] [blame] | 375 | |
Angel Pons | da4e1d7 | 2022-05-04 17:08:11 +0200 | [diff] [blame] | 376 | /* DDI port config */ |
| 377 | enum ddi_port_config DdiPortAConfig; |
| 378 | enum ddi_port_config DdiPortBConfig; |
Wonkyu Kim | 9f2e3ad | 2020-01-23 00:06:07 -0800 | [diff] [blame] | 379 | |
| 380 | /* Enable(1)/Disable(0) HPD */ |
| 381 | uint8_t DdiPortAHpd; |
| 382 | uint8_t DdiPortBHpd; |
| 383 | uint8_t DdiPortCHpd; |
| 384 | uint8_t DdiPort1Hpd; |
| 385 | uint8_t DdiPort2Hpd; |
| 386 | uint8_t DdiPort3Hpd; |
| 387 | uint8_t DdiPort4Hpd; |
| 388 | |
| 389 | /* Enable(1)/Disable(0) DDC */ |
| 390 | uint8_t DdiPortADdc; |
| 391 | uint8_t DdiPortBDdc; |
| 392 | uint8_t DdiPortCDdc; |
| 393 | uint8_t DdiPort1Ddc; |
| 394 | uint8_t DdiPort2Ddc; |
| 395 | uint8_t DdiPort3Ddc; |
| 396 | uint8_t DdiPort4Ddc; |
Wonkyu Kim | 2b4ded0 | 2020-03-03 01:43:45 -0800 | [diff] [blame] | 397 | |
| 398 | /* Hybrid storage mode enable (1) / disable (0) |
| 399 | * This mode makes FSP detect Optane and NVME and set PCIe lane mode |
| 400 | * accordingly */ |
| 401 | uint8_t HybridStorageMode; |
Srinidhi N Kaushik | 4b9fa2d | 2020-03-13 00:54:30 -0700 | [diff] [blame] | 402 | |
| 403 | /* |
| 404 | * Override CPU flex ratio value: |
| 405 | * CPU ratio value controls the maximum processor non-turbo ratio. |
| 406 | * Valid Range 0 to 63. |
| 407 | * In general descriptor provides option to set default cpu flex ratio. |
| 408 | * Default cpu flex ratio 0 ensures booting with non-turbo max frequency. |
| 409 | * That's the reason FSP skips cpu_ratio override if cpu_ratio is 0. |
| 410 | * Only override CPU flex ratio to not boot with non-turbo max. |
| 411 | */ |
| 412 | uint8_t cpu_ratio_override; |
| 413 | |
Wonkyu Kim | 3180af7 | 2020-03-19 15:30:06 -0700 | [diff] [blame] | 414 | /* HyperThreadingDisable : Yes (1) / No (0) */ |
| 415 | uint8_t HyperThreadingDisable; |
Shaunak Saha | 32b8a51 | 2020-03-31 22:56:13 -0700 | [diff] [blame] | 416 | |
| 417 | /* |
| 418 | * Enable(0)/Disable(1) DMI Power Optimizer on PCH side. |
| 419 | * Default 0. Setting this to 1 disables the DMI Power Optimizer. |
| 420 | */ |
| 421 | uint8_t DmiPwrOptimizeDisable; |
| 422 | |
Venkata Krishna Nimmagadda | e18f719 | 2020-05-15 00:13:40 -0700 | [diff] [blame] | 423 | /* structure containing various settings for PCH FIVRs */ |
| 424 | struct { |
| 425 | bool configure_ext_fivr; |
| 426 | enum fivr_enable_states v1p05_enable_bitmap; |
| 427 | enum fivr_enable_states vnn_enable_bitmap; |
| 428 | enum fivr_voltage_supported v1p05_supported_voltage_bitmap; |
| 429 | enum fivr_voltage_supported vnn_supported_voltage_bitmap; |
| 430 | /* External Icc Max for V1p05 rail in mA */ |
| 431 | int v1p05_icc_max_ma; |
| 432 | /* External Vnn Voltage in mV */ |
| 433 | int vnn_sx_voltage_mv; |
| 434 | } ext_fivr_settings; |
Jamie Ryu | f8668e9 | 2020-06-24 14:45:13 -0700 | [diff] [blame] | 435 | |
| 436 | /* |
| 437 | * Enable(1)/Disable(0) CPU Replacement check. |
| 438 | * Default 0. Setting this to 1 to check CPU replacement. |
| 439 | */ |
| 440 | uint8_t CpuReplacementCheck; |
Jamie Ryu | 5b7daa2 | 2020-08-18 18:54:49 -0700 | [diff] [blame] | 441 | |
| 442 | /* |
| 443 | * SLP_S3 Minimum Assertion Width Policy |
| 444 | * 1 = 60us |
| 445 | * 2 = 1ms |
| 446 | * 3 = 50ms (default) |
| 447 | * 4 = 2s |
| 448 | */ |
| 449 | uint8_t PchPmSlpS3MinAssert; |
| 450 | |
| 451 | /* |
| 452 | * SLP_S4 Minimum Assertion Width Policy |
| 453 | * 1 = 1s (default) |
| 454 | * 2 = 2s |
| 455 | * 3 = 3s |
| 456 | * 4 = 4s |
| 457 | */ |
| 458 | uint8_t PchPmSlpS4MinAssert; |
| 459 | |
| 460 | /* |
| 461 | * SLP_SUS Minimum Assertion Width Policy |
| 462 | * 1 = 0ms |
| 463 | * 2 = 500ms |
| 464 | * 3 = 1s |
| 465 | * 4 = 4s (default) |
| 466 | */ |
| 467 | uint8_t PchPmSlpSusMinAssert; |
| 468 | |
| 469 | /* |
| 470 | * SLP_A Minimum Assertion Width Policy |
| 471 | * 1 = 0ms |
| 472 | * 2 = 4s |
| 473 | * 3 = 98ms |
| 474 | * 4 = 2s (default) |
| 475 | */ |
| 476 | uint8_t PchPmSlpAMinAssert; |
| 477 | |
| 478 | /* |
| 479 | * PCH PM Reset Power Cycle Duration |
| 480 | * 0 = 4s (default) |
| 481 | * 1 = 1s |
| 482 | * 2 = 2s |
| 483 | * 3 = 3s |
| 484 | * 4 = 4s |
| 485 | * |
| 486 | * NOTE: Duration programmed in the PchPmPwrCycDur should never be smaller than the |
| 487 | * stretch duration programmed in the following registers: |
| 488 | * - GEN_PMCON_A.SLP_S3_MIN_ASST_WDTH (PchPmSlpS3MinAssert) |
| 489 | * - GEN_PMCON_A.S4MAW (PchPmSlpS4MinAssert) |
| 490 | * - PM_CFG.SLP_A_MIN_ASST_WDTH (PchPmSlpAMinAssert) |
| 491 | * - PM_CFG.SLP_LAN_MIN_ASST_WDTH |
| 492 | */ |
| 493 | uint8_t PchPmPwrCycDur; |
Shreesh Chhabbi | fbad99f | 2021-01-20 09:07:25 -0800 | [diff] [blame] | 494 | |
| 495 | /* |
| 496 | * External Clock Gate |
| 497 | * true = Mainboard design uses external clock gating |
| 498 | * false = Mainboard design does not use external clock gating |
| 499 | * |
| 500 | */ |
| 501 | bool external_clk_gated; |
| 502 | |
| 503 | /* |
| 504 | * External PHY Gate |
| 505 | * true = Mainboard design uses external phy gating |
| 506 | * false = Mainboard design does not use external phy gating |
| 507 | * |
| 508 | */ |
| 509 | bool external_phy_gated; |
| 510 | |
| 511 | /* |
| 512 | * External Bypass Enable |
| 513 | * true = Mainboard design uses external bypass rail |
| 514 | * false = Mainboard design does not use external bypass rail |
| 515 | * |
| 516 | */ |
| 517 | bool external_bypass; |
Tim Crawford | 1724b57 | 2021-09-21 21:50:49 -0600 | [diff] [blame] | 518 | |
| 519 | /* i915 struct for GMA backlight control */ |
| 520 | struct i915_gpu_controller_info gfx; |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 521 | }; |
| 522 | |
| 523 | typedef struct soc_intel_tigerlake_config config_t; |
| 524 | |
| 525 | #endif |