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review.coreboot.org / coreboot / 27d6299d51744bda549b7764b8fde909ad812e33 / src / soc / intel / tigerlake / chip.h
  1. da4e1d7 soc/intel/tigerlake: Add enum for `DdiPortXConfig` by Angel Pons · 2 years, 4 months ago
  2. fdc4e8e soc/intel/tgl: drop orphaned VR domains enum by Michael Niewöhner · 2 years, 5 months ago
  3. ad50b40 soc/intel/tgl: Replace dt `HeciEnabled` by `HECI1 disable` config by Subrata Banik · 2 years, 8 months ago
  4. 45b6080 soc/intel/tigerlake: add devicetree option PcieRpSlotImplemented by Michael Niewöhner · 2 years, 7 months ago
  5. 2aa1ff4 soc/intel/tigerlake: Hook up DPTF device to devicetree by Felix Singer · 2 years, 9 months ago
  6. 8474f4d soc/intel/tigerlake: Drop unused SataEnable setting by Felix Singer · 2 years, 9 months ago
  7. 715b787 soc/intel/tigerlake: Hook up SMBus device to devicetree by Felix Singer · 2 years, 9 months ago
  8. d2fadda soc/intel: replace dt option PmTimerDisabled by Kconfig by Michael Niewöhner · 2 years, 11 months ago
  9. 1724b57 soc/intel/tigerlake: Hook up GMA ACPI brightness controls by Tim Crawford · 2 years, 11 months ago
  10. f71d8c9 soc/tigerlake: Make IO decode / enable register configurable by Sean Rhodes · 3 years ago
  11. 301b09b soc/intel/tigerlake: Add TGL-H power limits by Jeremy Soller · 3 years ago
  12. 4b3e06e soc/intel/tigerlake: Allow devicetree to fill UPD related to TCSS OC by Nick Vaccaro · 3 years, 3 months ago
  13. 59a621a soc/intel/tgl,mb/google/volteer: Add API for Type-C aux bias pads by Tim Wawrzynczak · 3 years, 5 months ago
  14. a979460 soc/intel/alderlake: rename CONFIG_MAX_PCIE_CLOCKS to CONFIG_MAX_PCIE_CLOCK_SRC by Rizwan Qureshi · 3 years, 4 months ago
  15. 82d5123 intel/tigerlake: Add Acoustic features by Shaunak Saha · 3 years, 6 months ago
  16. 8056187 soc/intel/tgl: Add configurable value for PmcUsb2PhySusPgEnable by Derek Huang · 3 years, 5 months ago
  17. b34be4d soc/intel/tigerlake: Add CNVi Bluetooth flag at devicetree entry by Cliff Huang · 3 years, 6 months ago
  18. 98521c5 soc/intel: Retype `CnviBtAudioOffload` devicetree option by Angel Pons · 3 years, 6 months ago
  19. fbad99f soc/intel/tgl: Update S0ix enable mask based on SoC and mainboard design by Shreesh Chhabbi · 3 years, 7 months ago
  20. ed6bda2 soc/intel/tgl: Add configurable value for ConfigTdpLevel by Derek Huang · 3 years, 7 months ago
  21. de2ab41 soc/intel/common: Move L1_substates_control to pcie_rp.h by Eric Lai · 3 years, 7 months ago
  22. bf50c31 soc/intel/tgl: Add configurable value for UsbTcPortEn by Brandon Breitenstein · 3 years, 8 months ago
  23. 8913b78 soc/intel: hook up new gpio device in the soc chips by Michael Niewöhner · 3 years, 8 months ago
  24. a3495c0 soc/intel/tigerlake: Drop unreferenced devicetree settings by Angel Pons · 3 years, 8 months ago
  25. 17e905ac soc/intel/tigerlake: Expose UPD to enable Precision Time Measurement by Duncan Laurie · 3 years, 10 months ago
  26. 6e98292 soc/intel/*/chip: Remove unused devicetree entry by Patrick Rudolph · 3 years, 10 months ago
  27. a64b4f4 mb/*,soc/intel: drop the obsolete dt option `speed_shift_enable` by Michael Niewöhner · 3 years, 10 months ago
  28. 0d0f43f soc/intel/tigerlake: Add Acoustic features by Shaunak Saha · 4 years ago
  29. 5b7daa2 soc/intel/tigerlake: Configure FSP UPDs for minimum assertion widths by Jamie Ryu · 4 years ago
  30. 9fec889 soc/intel/{cnl,icl,jsl,tgl}: Clean up chip.h by Subrata Banik · 4 years ago
  31. 6fd87ff soc/intel/tigerlake: Allow fine grained control of S0iX states by Jes Klinke · 4 years ago
  32. bd615d6 soc/intel/tigerlake: Configure TCSS D3Hot and D3Cold by John Zhao · 4 years, 1 month ago
  33. 23a60fa src/soc/intel: Add include <types.h> by Elyes HAOUAS · 4 years, 1 month ago
  34. 1a62150 soc/intel/tigerlake: Set power limits for Tiger Lake Y-SKU by Sumeet R Pawnikar · 4 years, 1 month ago
  35. 1a8949c soc/intel/tigerlake: Hook up SATA Port Enable DITO UPDs by Shaunak Saha · 4 years, 2 months ago
  36. 8104eff mainboard/intel/tglrvp: Remove unused PrmrrSize chip config by Subrata Banik · 4 years, 1 month ago
  37. f8668e9 soc/intel/tigerlake: Add CpuReplacementCheck to chip options by Jamie Ryu · 4 years, 2 months ago
  38. 63ce260 soc/intel/tigerlake: Add CmdMirror option in chip.h by David Wu · 4 years, 2 months ago
  39. 2dcca0f mb/google/volteer: Override power limits with SKU-specific limits by Tim Wawrzynczak · 4 years, 2 months ago
  40. c66c153 soc/soch/intel/tigerlake: Integrate PCIe hot-plug config UPD by Wonkyu Kim · 4 years, 3 months ago
  41. e18f719 soc/intel/tigerlake: Add devicetree support to change PCH VR settings by Venkata Krishna Nimmagadda · 4 years, 3 months ago
  42. 92a3a30 soc/intel/tigerlake: Set FSPS UPD ITbtConnectTopologyTimeoutInMs by John Zhao · 4 years, 3 months ago
  43. 23e8b5b soc/intel/tigerlake: Configure TcssDma0En and TcssDma1En by John Zhao · 4 years, 3 months ago
  44. b30fe36 soc/intel/tigerlake: Remove MIPI clock setting from devicetree by Srinidhi N Kaushik · 4 years, 3 months ago
  45. b4d7116 soc/intel/tigerlake: Delete unused configuration by Wonkyu Kim · 4 years, 3 months ago
  46. 8aac881 soc/intel/tigerlake: Add FSP UPD D3HotEnable and D3ColdEnable by John Zhao · 4 years, 3 months ago
  47. d213246 tigerlake: update processor power limits configuration by Sumeet R Pawnikar · 4 years, 3 months ago
  48. 71d365d soc/tigerlake: Add devicetree configurability for IomTypeCPortPadCfg by Brandon Breitenstein · 4 years, 4 months ago
  49. 7a05e6e soc/intel/tigerlake: Add FSP UPD TcssDma0En and TcssDma1En by John Zhao · 4 years, 3 months ago
  50. 54b706e soc/intel/tigerlake: Add PchHdaIDispCodecDisconnect override by Eric Lai · 4 years, 3 months ago
  51. 32b8a51 soc/intel/tigerlake: Control SATA and DMI power optimization by Shaunak Saha · 4 years, 5 months ago
  52. 6b5bc77 treewide: Remove "this file is part of" lines by Patrick Georgi · 4 years, 3 months ago
  53. 7be0df8 soc/intel/{jsl,tgl}: Rename PcdDebugInterfaceFlags macros for better understanding by Subrata Banik · 4 years, 4 months ago
  54. 0d6cc22 soc/intel/tigerlake: Fill PcieRpClkReqDetect from devicetree by Meera Ravindranath · 4 years, 4 months ago
  55. 04a8cfb soc/intel/tigerlake: Update iDisp Link UPD settings by Srinidhi N Kaushik · 4 years, 4 months ago
  56. 3ed55e5 soc/intel/tigerlake: Remove eMMC/SD support by Duncan Laurie · 4 years, 4 months ago
  57. 5943117 soc/intel/tigerlake: Configure RP setting by Wonkyu Kim · 4 years, 4 months ago
  58. 16f6aa8 soc/intel/tigerlake: Use SPDX for GPL-2.0-only files by Angel Pons · 4 years, 5 months ago
  59. fc93237 soc/intel/tigerlake: Configure IOM_TYPEC_SW_CONFIGURATION_3 by Brandon Breitenstein · 4 years, 5 months ago
  60. 3180af7 soc/intel/tigerlake: Configure Hyperthreading by Wonkyu Kim · 4 years, 5 months ago
  61. 1c6d8a9 soc: Remove copyright notices by Patrick Georgi · 4 years, 5 months ago
  62. a6bff2d soc/intel/tigerlake: Enable CNVi through dev_enabled by Srinidhi N Kaushik · 4 years, 5 months ago
  63. 4b9fa2d soc/intel/tigerlake: Update Cpu Ratio settings by Srinidhi N Kaushik · 4 years, 5 months ago
  64. 84b4882 soc/intel/tigerlake: Configure L1Substates for PCH Root ports by Wonkyu Kim · 4 years, 5 months ago
  65. 35d7843 soc/intel/tigerlake: Correct FSP log interface by Ronak Kanabar · 4 years, 6 months ago
  66. 2b4ded0 soc/intel/tigerlake: Enable Hybrid storage mode by Wonkyu Kim · 4 years, 6 months ago
  67. 8488853 soc/intel/tigerlake: Enable CNVi Mode by Srinidhi N Kaushik · 4 years, 6 months ago
  68. 79ccc69 src: capitalize 'PCIe' by Elyes HAOUAS · 4 years, 6 months ago
  69. 1c2313d soc/intel/tigerlake: Add Jasper lake GPIO support by Ronak Kanabar · 4 years, 8 months ago
  70. 56626cf soc/intel/{icl,jsl,tgl}: Enable PlatformDebugConsent by Kconfig by Subrata Banik · 4 years, 6 months ago
  71. dba6c4c soc/intel/tigerlake: Update FSP params for Jasper Lake by Maulik V Vaghela · 4 years, 7 months ago
  72. 2f2c7eb soc/intel/tigerlake: Enable Audio on TGL by Srinidhi N Kaushik · 4 years, 8 months ago
  73. 1ab6f0c soc/intel/tigerlake: Configure TCSS xHCI and xDCI by Wonkyu Kim · 4 years, 7 months ago
  74. 9f2e3ad soc/intel/tigerlake: Enable DP ports according to board design by Wonkyu Kim · 4 years, 7 months ago
  75. 2fd4972 soc/intel/tigerlake: Update chip files by Ravi Sarawadi · 4 years, 8 months ago
  76. a6eab80 soc/intel/{cnl,icl,skl,tgl}: Remove unused gpe0_en_* from chip.h by Furquan Shaikh · 4 years, 8 months ago
  77. 91e89c5 soc/intel/tigerlake: Do initial SoC commit till ramstage by Subrata Banik · 4 years, 10 months ago