| Barnali Sarkar | 89331cd | 2017-02-16 17:22:37 +0530 | [diff] [blame] | 1 | config SOC_INTEL_COMMON_BLOCK_FAST_SPI |
| 2 | bool |
| Aaron Durbin | bd467d1 | 2020-01-11 10:33:26 -0700 | [diff] [blame] | 3 | select SPI_FLASH_DONT_INCLUDE_ALL_DRIVERS |
| Barnali Sarkar | 89331cd | 2017-02-16 17:22:37 +0530 | [diff] [blame] | 4 | help |
| 5 | Intel Processor common FAST_SPI support |
| Duncan Laurie | dc1e6bc | 2017-08-15 13:32:26 -0700 | [diff] [blame] | 6 | |
| 7 | config FAST_SPI_DISABLE_WRITE_STATUS |
| 8 | bool "Disable write status SPI opcode" |
| 9 | depends on SOC_INTEL_COMMON_BLOCK_FAST_SPI |
| 10 | default n if CHROMEOS |
| 11 | default y |
| 12 | help |
| 13 | Disable the write status SPI opcode in Intel Fast SPI block. |
| Furquan Shaikh | 886f4e8 | 2020-11-22 11:37:44 -0800 | [diff] [blame] | 14 | |
| 15 | config FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW |
| 16 | bool |
| 17 | depends on SOC_INTEL_COMMON_BLOCK_FAST_SPI |
| Raul E Rangel | e92a982 | 2021-06-24 16:54:27 -0600 | [diff] [blame] | 18 | # Enable X86_CUSTOM_BOOTMEDIA because the fast SPI controller |
| 19 | # driver provides a custom boot media device when multiple decode |
| 20 | # windows are used for the BIOS region. |
| 21 | select X86_CUSTOM_BOOTMEDIA |
| Furquan Shaikh | 886f4e8 | 2020-11-22 11:37:44 -0800 | [diff] [blame] | 22 | help |
| 23 | Fast SPI controller on the platform supports additional |
| 24 | window for memory mapping BIOS region (region 1) on the SPI |
| 25 | flash beyond the standard limit of 16MiB. Depending upon the |
| 26 | size of the SPI flash part used by the mainboard, two decode |
| 27 | windows will be enabled: |
| 28 | 1. Fixed decode window up to a maximum size of 16MiB under |
| 29 | 4G boundary. |
| 30 | 2. Extended decode window up to a maximum size provided by |
| 31 | the platform to map the rest of the BIOS region. |
| 32 | SoC selecting this config is expected to provide the base and |
| 33 | maximum size of the extended window in the host address space |
| 34 | using configs EXT_BIOS_WIN_BASE and EXT_BIOS_WIN_SIZE. |
| 35 | |
| 36 | config EXT_BIOS_WIN_BASE |
| 37 | hex |
| 38 | help |
| 39 | If an additional window for mapping BIOS region greater than |
| 40 | 16MiB is supported, then this config is used to provide the |
| 41 | base address reserved for the mapping. Since the mapping is |
| 42 | done at the top of the window, depending upon the size of the |
| 43 | BIOS region, the actual base address configured in the fast |
| 44 | SPI controller can be higher at runtime. |
| 45 | |
| 46 | config EXT_BIOS_WIN_SIZE |
| 47 | hex |
| 48 | help |
| 49 | Maximum size of the extended window reserved for mapping BIOS |
| 50 | region greater than 16MiB. The actual mapped window might be |
| 51 | smaller depending upon the size of the BIOS region. |
| Werner Zeh | 53553e8 | 2022-05-05 11:55:30 +0200 | [diff] [blame] | 52 | |
| 53 | config FAST_SPI_GENERATE_SSDT |
| 54 | bool |
| 55 | default n |
| 56 | help |
| 57 | Select this option if the Fast SPI controller is hidden from the OS. |
| 58 | If this switch is selected, an entry in the SSDT will be generated |
| 59 | for the controller to report the occupied resource which is not |
| 60 | discoverable at OS runtime. |