| commit | 53553e8ee5c55030e3b60e933669f55994cc6ab7 | [log] [tgz] |
|---|---|---|
| author | Werner Zeh <werner.zeh@siemens.com> | Thu May 05 11:55:30 2022 +0200 |
| committer | Felix Held <felix-coreboot@felixheld.de> | Sat May 21 16:20:17 2022 +0000 |
| tree | 245bad7b4f5e8b8ce35227d452b1e12fddf09517 | |
| parent | 3c88dc85f6d50cf294ebc2cadebbadab648b5f02 [diff] |
src/soc/intel/cmn/fast-spi: Add SSDT extension to fast SPI driver If the SPI controller is hidden from the OS (which is default on Apollo Lake) then OS has no chance to probe the device and therefore can not be aware of the resources this PCI device occupies. If the OS needs to move some resources for a reason it can happen that the new allocated window will be shadowed by the hidden PCI device resource and hence causing a conflict. As a result this MMIO window will be inaccessible from the OS which will cause issues in applications. For instance on Apollo Lake this causes flashrom to stop working. This patch adds a SSDT extension for the PCI device if it is hidden from the OS and reports the occupied resource via ACPI to the OS. For the cases where the device is hidden later at coreboot runtime and therefore is not marked as hidden in the PCI device itself a Kconfig switch called 'FAST_SPI_GENERATE_SSDT' is introduced. It defaults to 'no' and can be set from SOC code to override it. Since there is no defined ACPI ID for the fast SPI controller available now, the generic one (PNP0C02) is used. Test: Boot mc_apl4 and make sure flashrom works again. Change-Id: Ia16dfe6e001188aad26418afe0f04c53ecfd56f1 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64076 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Subrata Banik <subratabanik@google.com>
coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.
With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.
coreboot was formerly known as LinuxBIOS.
After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot.
See https://www.coreboot.org/Payloads for a list of supported payloads.
coreboot supports a wide range of chipsets, devices, and mainboards.
For details please consult:
ANY_TOOLCHAIN Kconfig option if you're feeling lucky (no support in this case).Optional:
make menuconfig and make nconfig)Please consult https://www.coreboot.org/Build_HOWTO for details.
If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.
Please see https://www.coreboot.org/QEMU for details.
Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:
You can contact us directly on the coreboot mailing list:
https://www.coreboot.org/Mailinglist
The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.
coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.
This makes the resulting coreboot images licensed under the GPL, version 2.