Angel Pons | f5627e8 | 2020-04-05 15:46:52 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Lijian Zhao | 2b074d9 | 2017-08-17 14:25:24 -0700 | [diff] [blame] | 2 | |
Furquan Shaikh | 76cedd2 | 2020-05-02 10:24:23 -0700 | [diff] [blame] | 3 | #include <acpi/acpi.h> |
Kyösti Mälkki | 0c1dd9c | 2020-06-17 23:37:49 +0300 | [diff] [blame] | 4 | #include <acpi/acpi_gnvs.h> |
Furquan Shaikh | 76cedd2 | 2020-05-02 10:24:23 -0700 | [diff] [blame] | 5 | #include <acpi/acpigen.h> |
Lijian Zhao | 2b074d9 | 2017-08-17 14:25:24 -0700 | [diff] [blame] | 6 | #include <arch/smp/mpspec.h> |
Patrick Georgi | 39c3d39 | 2019-04-23 12:27:22 +0200 | [diff] [blame] | 7 | #include <console/console.h> |
John Zhao | db3f0e3 | 2019-03-15 16:54:27 -0700 | [diff] [blame] | 8 | #include <device/mmio.h> |
| 9 | #include <device/pci_ops.h> |
Lijian Zhao | 2b074d9 | 2017-08-17 14:25:24 -0700 | [diff] [blame] | 10 | #include <intelblocks/cpulib.h> |
| 11 | #include <intelblocks/pmclib.h> |
| 12 | #include <intelblocks/acpi.h> |
John Zhao | db3f0e3 | 2019-03-15 16:54:27 -0700 | [diff] [blame] | 13 | #include <intelblocks/p2sb.h> |
Lijian Zhao | 2b074d9 | 2017-08-17 14:25:24 -0700 | [diff] [blame] | 14 | #include <soc/cpu.h> |
| 15 | #include <soc/iomap.h> |
| 16 | #include <soc/nvs.h> |
| 17 | #include <soc/pci_devs.h> |
| 18 | #include <soc/pm.h> |
John Zhao | db3f0e3 | 2019-03-15 16:54:27 -0700 | [diff] [blame] | 19 | #include <soc/systemagent.h> |
Lijian Zhao | 2b074d9 | 2017-08-17 14:25:24 -0700 | [diff] [blame] | 20 | |
Elyes HAOUAS | c338507 | 2019-03-21 15:38:06 +0100 | [diff] [blame] | 21 | #include "chip.h" |
| 22 | |
Shaunak Saha | 95b6175 | 2017-10-04 23:08:40 -0700 | [diff] [blame] | 23 | /* |
| 24 | * List of supported C-states in this processor. |
| 25 | */ |
| 26 | enum { |
| 27 | C_STATE_C0, /* 0 */ |
| 28 | C_STATE_C1, /* 1 */ |
| 29 | C_STATE_C1E, /* 2 */ |
| 30 | C_STATE_C6_SHORT_LAT, /* 3 */ |
| 31 | C_STATE_C6_LONG_LAT, /* 4 */ |
| 32 | C_STATE_C7_SHORT_LAT, /* 5 */ |
| 33 | C_STATE_C7_LONG_LAT, /* 6 */ |
| 34 | C_STATE_C7S_SHORT_LAT, /* 7 */ |
| 35 | C_STATE_C7S_LONG_LAT, /* 8 */ |
| 36 | C_STATE_C8, /* 9 */ |
| 37 | C_STATE_C9, /* 10 */ |
| 38 | C_STATE_C10, /* 11 */ |
| 39 | NUM_C_STATES |
| 40 | }; |
| 41 | |
Shaunak Saha | 95b6175 | 2017-10-04 23:08:40 -0700 | [diff] [blame] | 42 | static const acpi_cstate_t cstate_map[NUM_C_STATES] = { |
| 43 | [C_STATE_C0] = {}, |
| 44 | [C_STATE_C1] = { |
| 45 | .latency = 0, |
| 46 | .power = C1_POWER, |
| 47 | .resource = MWAIT_RES(0, 0), |
| 48 | }, |
| 49 | [C_STATE_C1E] = { |
| 50 | .latency = 0, |
| 51 | .power = C1_POWER, |
| 52 | .resource = MWAIT_RES(0, 1), |
| 53 | }, |
| 54 | [C_STATE_C6_SHORT_LAT] = { |
| 55 | .latency = C_STATE_LATENCY_FROM_LAT_REG(0), |
| 56 | .power = C6_POWER, |
| 57 | .resource = MWAIT_RES(2, 0), |
| 58 | }, |
| 59 | [C_STATE_C6_LONG_LAT] = { |
| 60 | .latency = C_STATE_LATENCY_FROM_LAT_REG(0), |
| 61 | .power = C6_POWER, |
| 62 | .resource = MWAIT_RES(2, 1), |
| 63 | }, |
| 64 | [C_STATE_C7_SHORT_LAT] = { |
| 65 | .latency = C_STATE_LATENCY_FROM_LAT_REG(0), |
| 66 | .power = C7_POWER, |
| 67 | .resource = MWAIT_RES(3, 0), |
| 68 | }, |
| 69 | [C_STATE_C7_LONG_LAT] = { |
| 70 | .latency = C_STATE_LATENCY_FROM_LAT_REG(0), |
| 71 | .power = C7_POWER, |
| 72 | .resource = MWAIT_RES(3, 1), |
| 73 | }, |
| 74 | [C_STATE_C7S_SHORT_LAT] = { |
| 75 | .latency = C_STATE_LATENCY_FROM_LAT_REG(0), |
| 76 | .power = C7_POWER, |
| 77 | .resource = MWAIT_RES(3, 2), |
| 78 | }, |
| 79 | [C_STATE_C7S_LONG_LAT] = { |
| 80 | .latency = C_STATE_LATENCY_FROM_LAT_REG(0), |
| 81 | .power = C7_POWER, |
| 82 | .resource = MWAIT_RES(3, 3), |
| 83 | }, |
| 84 | [C_STATE_C8] = { |
| 85 | .latency = C_STATE_LATENCY_FROM_LAT_REG(0), |
| 86 | .power = C8_POWER, |
| 87 | .resource = MWAIT_RES(4, 0), |
| 88 | }, |
| 89 | [C_STATE_C9] = { |
| 90 | .latency = C_STATE_LATENCY_FROM_LAT_REG(0), |
| 91 | .power = C9_POWER, |
| 92 | .resource = MWAIT_RES(5, 0), |
| 93 | }, |
| 94 | [C_STATE_C10] = { |
| 95 | .latency = C_STATE_LATENCY_FROM_LAT_REG(0), |
| 96 | .power = C10_POWER, |
| 97 | .resource = MWAIT_RES(6, 0), |
| 98 | }, |
| 99 | }; |
| 100 | |
Ronak Kanabar | c6c4d00 | 2019-01-30 18:53:14 +0530 | [diff] [blame] | 101 | static int cstate_set_non_s0ix[] = { |
Shaunak Saha | 95b6175 | 2017-10-04 23:08:40 -0700 | [diff] [blame] | 102 | C_STATE_C1E, |
| 103 | C_STATE_C6_LONG_LAT, |
| 104 | C_STATE_C7S_LONG_LAT |
| 105 | }; |
| 106 | |
Ronak Kanabar | c6c4d00 | 2019-01-30 18:53:14 +0530 | [diff] [blame] | 107 | static int cstate_set_s0ix[] = { |
Shaunak Saha | 95b6175 | 2017-10-04 23:08:40 -0700 | [diff] [blame] | 108 | C_STATE_C1E, |
| 109 | C_STATE_C7S_LONG_LAT, |
| 110 | C_STATE_C10 |
| 111 | }; |
| 112 | |
Angel Pons | e9f10ff | 2021-10-17 13:28:23 +0200 | [diff] [blame] | 113 | const acpi_cstate_t *soc_get_cstate_map(size_t *entries) |
Shaunak Saha | 95b6175 | 2017-10-04 23:08:40 -0700 | [diff] [blame] | 114 | { |
| 115 | static acpi_cstate_t map[MAX(ARRAY_SIZE(cstate_set_s0ix), |
| 116 | ARRAY_SIZE(cstate_set_non_s0ix))]; |
| 117 | int *set; |
| 118 | int i; |
Kyösti Mälkki | 28dc7dc | 2019-07-12 13:10:19 +0300 | [diff] [blame] | 119 | |
Kyösti Mälkki | d5f645c | 2019-09-28 00:20:27 +0300 | [diff] [blame] | 120 | config_t *config = config_of_soc(); |
Kyösti Mälkki | 28dc7dc | 2019-07-12 13:10:19 +0300 | [diff] [blame] | 121 | |
Shaunak Saha | 95b6175 | 2017-10-04 23:08:40 -0700 | [diff] [blame] | 122 | int is_s0ix_enable = config->s0ix_enable; |
| 123 | |
| 124 | if (is_s0ix_enable) { |
| 125 | *entries = ARRAY_SIZE(cstate_set_s0ix); |
| 126 | set = cstate_set_s0ix; |
| 127 | } else { |
| 128 | *entries = ARRAY_SIZE(cstate_set_non_s0ix); |
| 129 | set = cstate_set_non_s0ix; |
| 130 | } |
| 131 | |
| 132 | for (i = 0; i < *entries; i++) { |
Angel Pons | 14643b3 | 2021-10-17 13:21:05 +0200 | [diff] [blame] | 133 | map[i] = cstate_map[set[i]]; |
Shaunak Saha | 95b6175 | 2017-10-04 23:08:40 -0700 | [diff] [blame] | 134 | map[i].ctype = i + 1; |
| 135 | } |
| 136 | return map; |
| 137 | } |
| 138 | |
| 139 | void soc_power_states_generation(int core_id, int cores_per_package) |
| 140 | { |
Kyösti Mälkki | d5f645c | 2019-09-28 00:20:27 +0300 | [diff] [blame] | 141 | config_t *config = config_of_soc(); |
Kyösti Mälkki | 28dc7dc | 2019-07-12 13:10:19 +0300 | [diff] [blame] | 142 | |
| 143 | /* Generate P-state tables */ |
Shaunak Saha | 95b6175 | 2017-10-04 23:08:40 -0700 | [diff] [blame] | 144 | if (config->eist_enable) |
Shaunak Saha | 95b6175 | 2017-10-04 23:08:40 -0700 | [diff] [blame] | 145 | generate_p_state_entries(core_id, cores_per_package); |
| 146 | } |
| 147 | |
Lijian Zhao | 2b074d9 | 2017-08-17 14:25:24 -0700 | [diff] [blame] | 148 | void soc_fill_fadt(acpi_fadt_t *fadt) |
| 149 | { |
| 150 | const uint16_t pmbase = ACPI_BASE_ADDRESS; |
Kyösti Mälkki | 28dc7dc | 2019-07-12 13:10:19 +0300 | [diff] [blame] | 151 | const struct soc_intel_cannonlake_config *config; |
Kyösti Mälkki | d5f645c | 2019-09-28 00:20:27 +0300 | [diff] [blame] | 152 | config = config_of_soc(); |
Lijian Zhao | 2b074d9 | 2017-08-17 14:25:24 -0700 | [diff] [blame] | 153 | |
Meera Ravindranath | 48c7870 | 2019-12-12 10:37:49 +0530 | [diff] [blame] | 154 | fadt->pm_tmr_blk = pmbase + PM1_TMR; |
| 155 | fadt->pm_tmr_len = 4; |
Elyes HAOUAS | 04071f4 | 2020-07-20 17:05:24 +0200 | [diff] [blame] | 156 | fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
Meera Ravindranath | 48c7870 | 2019-12-12 10:37:49 +0530 | [diff] [blame] | 157 | fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; |
| 158 | fadt->x_pm_tmr_blk.bit_offset = 0; |
Patrick Rudolph | c02bda0 | 2020-02-28 10:19:41 +0100 | [diff] [blame] | 159 | fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; |
Meera Ravindranath | 48c7870 | 2019-12-12 10:37:49 +0530 | [diff] [blame] | 160 | fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR; |
| 161 | fadt->x_pm_tmr_blk.addrh = 0x0; |
Lijian Zhao | 2b074d9 | 2017-08-17 14:25:24 -0700 | [diff] [blame] | 162 | |
Duncan Laurie | 174ca43 | 2018-09-13 16:28:13 +0000 | [diff] [blame] | 163 | if (config->s0ix_enable) |
Vaibhav Shankar | 2da6ec4 | 2018-03-19 18:56:38 -0700 | [diff] [blame] | 164 | fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0; |
Lijian Zhao | 2b074d9 | 2017-08-17 14:25:24 -0700 | [diff] [blame] | 165 | } |
| 166 | uint32_t soc_read_sci_irq_select(void) |
| 167 | { |
Angel Pons | f585c6e | 2021-06-25 10:09:35 +0200 | [diff] [blame] | 168 | return read32p(soc_read_pmc_base() + IRQ_REG); |
Lijian Zhao | 2b074d9 | 2017-08-17 14:25:24 -0700 | [diff] [blame] | 169 | } |
| 170 | |
Kyösti Mälkki | c2b0a4f | 2020-06-28 22:39:59 +0300 | [diff] [blame] | 171 | void soc_fill_gnvs(struct global_nvs *gnvs) |
Lijian Zhao | 2b074d9 | 2017-08-17 14:25:24 -0700 | [diff] [blame] | 172 | { |
Kyösti Mälkki | 28dc7dc | 2019-07-12 13:10:19 +0300 | [diff] [blame] | 173 | const struct soc_intel_cannonlake_config *config; |
Kyösti Mälkki | d5f645c | 2019-09-28 00:20:27 +0300 | [diff] [blame] | 174 | config = config_of_soc(); |
Lijian Zhao | 2b074d9 | 2017-08-17 14:25:24 -0700 | [diff] [blame] | 175 | |
Lijian Zhao | 2b074d9 | 2017-08-17 14:25:24 -0700 | [diff] [blame] | 176 | /* Enable DPTF based on mainboard configuration */ |
| 177 | gnvs->dpte = config->dptf_enable; |
| 178 | |
Lijian Zhao | 2b074d9 | 2017-08-17 14:25:24 -0700 | [diff] [blame] | 179 | /* Set USB2/USB3 wake enable bitmaps. */ |
| 180 | gnvs->u2we = config->usb2_wake_enable_bitmap; |
| 181 | gnvs->u3we = config->usb3_wake_enable_bitmap; |
| 182 | } |
| 183 | |
Lijian Zhao | 2b074d9 | 2017-08-17 14:25:24 -0700 | [diff] [blame] | 184 | int soc_madt_sci_irq_polarity(int sci) |
| 185 | { |
| 186 | return MP_IRQ_POLARITY_HIGH; |
| 187 | } |
Lijian Zhao | 5ff742c | 2018-12-27 17:01:09 -0800 | [diff] [blame] | 188 | |
John Zhao | db3f0e3 | 2019-03-15 16:54:27 -0700 | [diff] [blame] | 189 | static unsigned long soc_fill_dmar(unsigned long current) |
| 190 | { |
Kyösti Mälkki | 903b40a | 2019-07-03 07:25:59 +0300 | [diff] [blame] | 191 | struct device *const igfx_dev = pcidev_path_on_root(SA_DEVFN_IGD); |
John Zhao | db3f0e3 | 2019-03-15 16:54:27 -0700 | [diff] [blame] | 192 | uint64_t gfxvtbar = MCHBAR64(GFXVTBAR) & VTBAR_MASK; |
| 193 | bool gfxvten = MCHBAR32(GFXVTBAR) & VTBAR_ENABLED; |
Patrick Rudolph | a9eec2c | 2020-07-28 12:05:17 +0200 | [diff] [blame] | 194 | const bool emit_igd = igfx_dev && igfx_dev->enabled && gfxvtbar && gfxvten; |
| 195 | if (emit_igd) { |
John Zhao | db3f0e3 | 2019-03-15 16:54:27 -0700 | [diff] [blame] | 196 | unsigned long tmp = current; |
| 197 | |
| 198 | current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar); |
| 199 | current += acpi_create_dmar_ds_pci(current, 0, 2, 0); |
| 200 | |
| 201 | acpi_dmar_drhd_fixup(tmp, current); |
John Zhao | db3f0e3 | 2019-03-15 16:54:27 -0700 | [diff] [blame] | 202 | } |
| 203 | |
Kyösti Mälkki | 903b40a | 2019-07-03 07:25:59 +0300 | [diff] [blame] | 204 | struct device *const ipu_dev = pcidev_path_on_root(SA_DEVFN_IPU); |
John Zhao | db3f0e3 | 2019-03-15 16:54:27 -0700 | [diff] [blame] | 205 | uint64_t ipuvtbar = MCHBAR64(IPUVTBAR) & VTBAR_MASK; |
| 206 | bool ipuvten = MCHBAR32(IPUVTBAR) & VTBAR_ENABLED; |
| 207 | |
| 208 | if (ipu_dev && ipu_dev->enabled && ipuvtbar && ipuvten) { |
| 209 | unsigned long tmp = current; |
| 210 | |
| 211 | current += acpi_create_dmar_drhd(current, 0, 0, ipuvtbar); |
| 212 | current += acpi_create_dmar_ds_pci(current, 0, 5, 0); |
| 213 | |
| 214 | acpi_dmar_drhd_fixup(tmp, current); |
| 215 | } |
| 216 | |
| 217 | uint64_t vtvc0bar = MCHBAR64(VTVC0BAR) & VTBAR_MASK; |
| 218 | bool vtvc0en = MCHBAR32(VTVC0BAR) & VTBAR_ENABLED; |
| 219 | |
| 220 | if (vtvc0bar && vtvc0en) { |
| 221 | const unsigned long tmp = current; |
| 222 | |
| 223 | current += acpi_create_dmar_drhd(current, |
| 224 | DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar); |
| 225 | current += acpi_create_dmar_ds_ioapic(current, |
| 226 | 2, V_P2SB_CFG_IBDF_BUS, V_P2SB_CFG_IBDF_DEV, |
| 227 | V_P2SB_CFG_IBDF_FUNC); |
| 228 | current += acpi_create_dmar_ds_msi_hpet(current, |
| 229 | 0, V_P2SB_CFG_HBDF_BUS, V_P2SB_CFG_HBDF_DEV, |
| 230 | V_P2SB_CFG_HBDF_FUNC); |
| 231 | |
| 232 | acpi_dmar_drhd_fixup(tmp, current); |
| 233 | } |
| 234 | |
Patrick Rudolph | a9eec2c | 2020-07-28 12:05:17 +0200 | [diff] [blame] | 235 | /* Add RMRR entry after all DRHD entries */ |
| 236 | if (emit_igd) { |
| 237 | const unsigned long tmp = current; |
| 238 | |
| 239 | current += acpi_create_dmar_rmrr(current, 0, |
| 240 | sa_get_gsm_base(), sa_get_tolud_base() - 1); |
| 241 | current += acpi_create_dmar_ds_pci(current, 0, 2, 0); |
| 242 | acpi_dmar_rmrr_fixup(tmp, current); |
| 243 | } |
John Zhao | 1159a16 | 2019-04-22 10:45:51 -0700 | [diff] [blame] | 244 | |
John Zhao | db3f0e3 | 2019-03-15 16:54:27 -0700 | [diff] [blame] | 245 | return current; |
| 246 | } |
| 247 | |
Furquan Shaikh | 0f007d8 | 2020-04-24 06:41:18 -0700 | [diff] [blame] | 248 | unsigned long sa_write_acpi_tables(const struct device *dev, unsigned long current, |
John Zhao | db3f0e3 | 2019-03-15 16:54:27 -0700 | [diff] [blame] | 249 | struct acpi_rsdp *rsdp) |
| 250 | { |
| 251 | acpi_dmar_t *const dmar = (acpi_dmar_t *)current; |
| 252 | |
| 253 | /* Create DMAR table only if we have VT-d capability |
| 254 | * and FSP does not override its feature. |
| 255 | */ |
| 256 | if ((pci_read_config32(dev, CAPID0_A) & VTD_DISABLE) || |
| 257 | !(MCHBAR32(VTVC0BAR) & VTBAR_ENABLED)) |
| 258 | return current; |
| 259 | |
| 260 | printk(BIOS_DEBUG, "ACPI: * DMAR\n"); |
| 261 | acpi_create_dmar(dmar, DMAR_INTR_REMAP, soc_fill_dmar); |
John Zhao | 1159a16 | 2019-04-22 10:45:51 -0700 | [diff] [blame] | 262 | |
John Zhao | db3f0e3 | 2019-03-15 16:54:27 -0700 | [diff] [blame] | 263 | current += dmar->header.length; |
| 264 | current = acpi_align_current(current); |
| 265 | acpi_add_table(rsdp, dmar); |
| 266 | |
| 267 | return current; |
| 268 | } |