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Patrick Georgiafd4c872020-05-05 23:43:18 +02001/* Memory information */
Patrick Georgiac959032020-05-05 22:49:26 +02002/* SPDX-License-Identifier: GPL-2.0-only */
Kane Chen33faac62014-07-27 12:54:44 -07003
4#ifndef _MEMORY_INFO_H_
5#define _MEMORY_INFO_H_
6
Barnali Sarkarc16d3892017-02-23 16:56:54 +05307#include <stdint.h>
8
Raul E Rangel99f54a62018-04-11 10:58:14 -06009#define DIMM_INFO_SERIAL_SIZE 4
Aaron Durbin4b6f2622018-10-09 07:31:24 -060010#define DIMM_INFO_PART_NUMBER_SIZE 33
Johnny Lind8740c32022-05-04 15:16:16 +080011#define DIMM_INFO_TOTAL 32
Richard Spiegelbd654802018-02-22 10:03:39 -070012
Raul E Rangel5041e9b2018-03-20 12:37:27 -060013/**
Kane Chen33faac62014-07-27 12:54:44 -070014 * If this table is filled and put in CBMEM,
15 * then these info in CBMEM will be used to generate smbios type 17 table
Raul E Rangel5041e9b2018-03-20 12:37:27 -060016 *
17 * Values are specified according to the JEDEC SPD Standard.
Kane Chen33faac62014-07-27 12:54:44 -070018 */
19struct dimm_info {
Raul E Rangel5041e9b2018-03-20 12:37:27 -060020 /*
21 * Size of the module in MiB.
22 */
Kane Chen33faac62014-07-27 12:54:44 -070023 uint32_t dimm_size;
Raul E Rangel5041e9b2018-03-20 12:37:27 -060024 /*
25 * SMBIOS (not SPD) device type.
26 *
Elyes HAOUAS28114ae2018-11-14 17:51:00 +010027 * See the smbios.h smbios_memory_type enum.
Raul E Rangel5041e9b2018-03-20 12:37:27 -060028 */
Kane Chen33faac62014-07-27 12:54:44 -070029 uint16_t ddr_type;
Rob Barnes327f1052020-09-01 10:26:57 -060030 /*
31 * ddr_frequency is deprecated.
32 * Use max_speed_mts and configured_speed_mts instead.
33 */
Kane Chen33faac62014-07-27 12:54:44 -070034 uint16_t ddr_frequency;
35 uint8_t rank_per_dimm;
36 uint8_t channel_num;
37 uint8_t dimm_num;
38 uint8_t bank_locator;
Raul E Rangel5041e9b2018-03-20 12:37:27 -060039 /*
Raul E Rangel99f54a62018-04-11 10:58:14 -060040 * SPD serial number.
Raul E Rangel5041e9b2018-03-20 12:37:27 -060041 */
Richard Spiegelbd654802018-02-22 10:03:39 -070042 uint8_t serial[DIMM_INFO_SERIAL_SIZE];
Raul E Rangel5041e9b2018-03-20 12:37:27 -060043 /*
44 * The last byte is '\0' for the end of string
45 *
46 * Must contain only printable ASCII.
47 */
Richard Spiegelbd654802018-02-22 10:03:39 -070048 uint8_t module_part_number[DIMM_INFO_PART_NUMBER_SIZE];
Raul E Rangel5041e9b2018-03-20 12:37:27 -060049 /*
50 * SPD Manufacturer ID
51 */
Kane Chen33faac62014-07-27 12:54:44 -070052 uint16_t mod_id;
Raul E Rangel5041e9b2018-03-20 12:37:27 -060053 /*
54 * SPD Module Type.
55 *
56 * See spd.h for valid values.
57 *
58 * e.g., SPD_RDIMM, SPD_SODIMM, SPD_MICRO_DIMM
59 */
Kane Chen33faac62014-07-27 12:54:44 -070060 uint8_t mod_type;
Raul E Rangel5041e9b2018-03-20 12:37:27 -060061 /*
62 * SPD bus width.
63 *
64 * Bits 0 - 2 encode the primary bus width:
65 * 0b000 = 8 bit width
66 * 0b001 = 16 bit width
67 * 0b010 = 32 bit width
68 * 0b011 = 64 bit width
69 *
70 * Bits 3 - 4 encode the extension bits (ECC):
71 * 0b00 = 0 extension bits
72 * 0b01 = 8 bit of ECC
73 *
74 * e.g.,
75 * 64 bit bus with 8 bits of ECC (72 bits total): 0b1011
76 * 64 bit bus with 0 bits of ECC (64 bits total): 0b0011
77 *
78 * See the smbios.h smbios_memory_bus_width enum.
79 */
Kane Chen33faac62014-07-27 12:54:44 -070080 uint8_t bus_width;
Christian Walterf9723222019-05-28 10:37:24 +020081 /*
82 * Voltage Level
83 */
84 uint16_t vdd_voltage;
Rob Barnes327f1052020-09-01 10:26:57 -060085 /*
86 * Max speed in MT/s
87 * If the value is 0, ddr_frequency should be used instead.
88 */
89 uint16_t max_speed_mts;
90 /*
91 * Configured speed in MT/s
92 * If the value is 0, ddr_frequency should be used instead.
93 */
94 uint16_t configured_speed_mts;
Stefan Reinauer6a001132017-07-13 02:20:27 +020095} __packed;
Kane Chen33faac62014-07-27 12:54:44 -070096
97struct memory_info {
Angel Pons6724ba42021-01-31 15:06:59 +010098 /*
99 * SMBIOS error correction type.
100 * See the smbios.h smbios_memory_array_ecc enum.
101 */
102 uint8_t ecc_type;
Patrick Rudolph5e007802020-07-27 15:37:43 +0200103 /* Maximum capacity the DRAM controller/mainboard supports */
104 uint32_t max_capacity_mib;
105 /* Maximum number of DIMMs the DRAM controller/mainboard supports */
106 uint16_t number_of_devices;
107
108 /* active DIMM configuration */
Kane Chen33faac62014-07-27 12:54:44 -0700109 uint8_t dimm_cnt;
Richard Spiegelbd654802018-02-22 10:03:39 -0700110 struct dimm_info dimm[DIMM_INFO_TOTAL];
Stefan Reinauer6a001132017-07-13 02:20:27 +0200111} __packed;
Kane Chen33faac62014-07-27 12:54:44 -0700112
Nick Vaccaro3b24bb62020-09-30 13:05:09 -0700113/*
114 * mainboard_get_dram_part_num returns a DRAM part number override string
115 * return NULL = no part number override provided by mainboard
116 * return non-NULL = pointer to a string terminating in '\0'
117 */
118const char *mainboard_get_dram_part_num(void);
Kane Chen33faac62014-07-27 12:54:44 -0700119#endif