Angel Pons | bbc99cf | 2020-04-04 18:51:23 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
huang lin | a97bd5a | 2014-10-14 10:04:16 -0700 | [diff] [blame] | 2 | |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 3 | #include <device/mmio.h> |
Julius Werner | 7a453eb | 2014-10-20 13:14:55 -0700 | [diff] [blame] | 4 | #include <soc/clock.h> |
| 5 | #include <soc/grf.h> |
| 6 | #include <soc/pmu.h> |
| 7 | #include <soc/tsadc.h> |
huang lin | a97bd5a | 2014-10-14 10:04:16 -0700 | [diff] [blame] | 8 | #include <stdint.h> |
huang lin | a97bd5a | 2014-10-14 10:04:16 -0700 | [diff] [blame] | 9 | |
| 10 | struct rk3288_tsadc_regs { |
| 11 | u32 user_con; |
| 12 | u32 auto_con; |
| 13 | u32 int_en; |
| 14 | u32 int_pd; |
| 15 | u32 reserved0[(0x20 - 0x10) / 4]; |
| 16 | u32 data0; |
| 17 | u32 data1; |
| 18 | u32 data2; |
| 19 | u32 data3; |
| 20 | u32 comp0_int; |
| 21 | u32 comp1_int; |
| 22 | u32 comp2_int; |
| 23 | u32 comp3_int; |
| 24 | u32 comp0_shut; |
| 25 | u32 comp1_shut; |
| 26 | u32 comp2_shut; |
| 27 | u32 comp3_shut; |
| 28 | u32 reserved1[(0x60 - 0x50) / 4]; |
| 29 | u32 hight_int_debounce; |
| 30 | u32 hight_tshut_debounce; |
| 31 | u32 auto_period; |
| 32 | u32 auto_period_ht; |
| 33 | }; |
| 34 | check_member(rk3288_tsadc_regs, auto_period_ht, 0x6c); |
| 35 | |
| 36 | /* auto_con */ |
| 37 | #define LAST_TSHUT (1 << 24) |
| 38 | #define TSHUT_POL_HIGH (1 << 8) |
| 39 | #define SRC3_EN (1 << 7) |
| 40 | #define SRC2_EN (1 << 6) |
| 41 | #define SRC1_EN (1 << 5) |
| 42 | #define SRC0_EN (1 << 4) |
| 43 | #define AUTO_EN (1 << 0) |
| 44 | |
| 45 | /* int_en */ |
| 46 | #define TSHUT_CRU_EN_SRC3 (1 << 11) |
| 47 | #define TSHUT_CRU_EN_SRC2 (1 << 10) |
| 48 | #define TSHUT_CRU_EN_SRC1 (1 << 9) |
| 49 | #define TSHUT_CRU_EN_SRC0 (1 << 8) |
| 50 | #define TSHUT_GPIO_EN_SRC3 (1 << 7) |
| 51 | #define TSHUT_GPIO_EN_SRC2 (1 << 6) |
| 52 | #define TSHUT_GPIO_EN_SRC1 (1 << 5) |
| 53 | #define TSHUT_GPIO_EN_SRC0 (1 << 4) |
| 54 | |
| 55 | #define AUTO_PERIOD 10 |
| 56 | #define AUTO_DEBOUNCE 4 |
| 57 | #define AUTO_PERIOD_HT 10 |
| 58 | #define AUTO_DEBOUNCE_HT 4 |
| 59 | #define TSADC_CLOCK_HZ (8 * KHz) |
| 60 | |
| 61 | /* AD value, correspond to 120 degrees Celsius */ |
| 62 | #define TSADC_SHUT_VALUE 3437 |
| 63 | |
| 64 | struct rk3288_tsadc_regs *rk3288_tsadc = (void *)TSADC_BASE; |
| 65 | |
| 66 | void tsadc_init(void) |
| 67 | { |
| 68 | rkclk_configure_tsadc(TSADC_CLOCK_HZ); |
| 69 | |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 70 | setbits32(&rk3288_tsadc->auto_con, LAST_TSHUT); |
huang lin | a97bd5a | 2014-10-14 10:04:16 -0700 | [diff] [blame] | 71 | |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 72 | setbits32(&rk3288_tsadc->int_en, |
huang lin | a97bd5a | 2014-10-14 10:04:16 -0700 | [diff] [blame] | 73 | TSHUT_CRU_EN_SRC2 | TSHUT_CRU_EN_SRC1 | |
| 74 | TSHUT_GPIO_EN_SRC2 | TSHUT_GPIO_EN_SRC1); |
| 75 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 76 | write32(&rk3288_tsadc->auto_period, AUTO_PERIOD); |
| 77 | write32(&rk3288_tsadc->hight_int_debounce, AUTO_DEBOUNCE); |
| 78 | write32(&rk3288_tsadc->auto_period_ht, AUTO_PERIOD_HT); |
| 79 | write32(&rk3288_tsadc->hight_tshut_debounce, AUTO_DEBOUNCE_HT); |
huang lin | a97bd5a | 2014-10-14 10:04:16 -0700 | [diff] [blame] | 80 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 81 | write32(&rk3288_tsadc->comp1_shut, TSADC_SHUT_VALUE); |
| 82 | write32(&rk3288_tsadc->comp2_shut, TSADC_SHUT_VALUE); |
huang lin | a97bd5a | 2014-10-14 10:04:16 -0700 | [diff] [blame] | 83 | |
| 84 | /* polarity set to high,channel1 for cpu,channel2 for gpu */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 85 | setbits32(&rk3288_tsadc->auto_con, TSHUT_POL_HIGH | SRC2_EN | |
huang lin | a97bd5a | 2014-10-14 10:04:16 -0700 | [diff] [blame] | 86 | SRC1_EN | AUTO_EN); |
| 87 | |
| 88 | /* |
| 89 | tsadc iomux must be set after the tshut polarity setting, |
Elyes HAOUAS | 8d1b0f1 | 2020-02-20 18:20:57 +0100 | [diff] [blame] | 90 | since the tshut polarity default low active, |
huang lin | a97bd5a | 2014-10-14 10:04:16 -0700 | [diff] [blame] | 91 | so if you enable tsadc iomux,it will output high |
| 92 | */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 93 | setbits32(&rk3288_pmu->iomux_tsadc_int, IOMUX_TSADC_INT); |
huang lin | a97bd5a | 2014-10-14 10:04:16 -0700 | [diff] [blame] | 94 | } |