Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 1 | config SOC_INTEL_BROADWELL |
| 2 | bool |
| 3 | help |
| 4 | Intel Broadwell and Haswell ULT support. |
| 5 | |
| 6 | if SOC_INTEL_BROADWELL |
| 7 | |
Angel Pons | a3288b3 | 2020-11-23 13:00:51 +0100 | [diff] [blame] | 8 | config SOC_SPECIFIC_OPTIONS |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 9 | def_bool y |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 10 | select CACHE_MRC_SETTINGS |
Angel Pons | 3f0a95a | 2020-11-23 13:34:56 +0100 | [diff] [blame] | 11 | select CPU_INTEL_HASWELL |
Matt DeVillier | 773488f | 2017-10-18 12:27:25 -0500 | [diff] [blame] | 12 | select INTEL_GMA_ACPI |
Angel Pons | dbdd528 | 2021-06-14 12:14:48 +0200 | [diff] [blame] | 13 | select MRC_SETTINGS_PROTECT |
| 14 | select REG_SCRIPT |
Youness Alaoui | b191c9f | 2017-05-08 15:22:03 -0400 | [diff] [blame] | 15 | |
Arthur Heymans | 4d56a06 | 2018-12-22 16:11:52 +0100 | [diff] [blame] | 16 | config BROADWELL_VBOOT_IN_BOOTBLOCK |
| 17 | depends on VBOOT |
| 18 | bool "Start verstage in bootblock" |
| 19 | default y |
| 20 | select VBOOT_STARTS_IN_BOOTBLOCK |
| 21 | select VBOOT_SEPARATE_VERSTAGE |
| 22 | help |
| 23 | Broadwell can either start verstage in a separate stage |
| 24 | right after the bootblock has run or it can start it |
| 25 | after romstage for compatibility reasons. |
Martin Roth | 26f97f9 | 2021-10-01 14:53:22 -0600 | [diff] [blame^] | 26 | Broadwell however uses a mrc.bin to initialize memory which |
Arthur Heymans | 4d56a06 | 2018-12-22 16:11:52 +0100 | [diff] [blame] | 27 | needs to be located at a fixed offset. Therefore even with |
| 28 | a separate verstage starting after the bootblock that same |
| 29 | binary is used meaning a jump is made from RW to the RO region |
| 30 | and back to the RW region after the binary is done. |
| 31 | |
Julius Werner | 1210b41 | 2017-03-27 19:26:32 -0700 | [diff] [blame] | 32 | config VBOOT |
Joel Kitching | 6672bd8 | 2019-04-10 16:06:21 +0800 | [diff] [blame] | 33 | select VBOOT_MUST_REQUEST_DISPLAY |
Arthur Heymans | 4d56a06 | 2018-12-22 16:11:52 +0100 | [diff] [blame] | 34 | select VBOOT_STARTS_IN_ROMSTAGE if !BROADWELL_VBOOT_IN_BOOTBLOCK |
Julius Werner | 1210b41 | 2017-03-27 19:26:32 -0700 | [diff] [blame] | 35 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 36 | config MMCONF_BASE_ADDRESS |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 37 | default 0xf0000000 |
| 38 | |
Angel Pons | 9debbd6 | 2021-01-28 12:42:53 +0100 | [diff] [blame] | 39 | config MMCONF_BUS_NUMBER |
| 40 | default 64 |
| 41 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 42 | config VGA_BIOS_ID |
| 43 | string |
| 44 | default "8086,0406" |
| 45 | |
Angel Pons | c715dc8 | 2021-01-31 00:33:04 +0100 | [diff] [blame] | 46 | config FIXED_MCHBAR_MMIO_BASE |
| 47 | default 0xfed10000 |
| 48 | |
| 49 | config FIXED_DMIBAR_MMIO_BASE |
| 50 | default 0xfed18000 |
| 51 | |
| 52 | config FIXED_EPBAR_MMIO_BASE |
| 53 | default 0xfed19000 |
| 54 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 55 | config DCACHE_RAM_BASE |
| 56 | hex |
| 57 | default 0xff7c0000 |
| 58 | |
| 59 | config DCACHE_RAM_SIZE |
| 60 | hex |
| 61 | default 0x10000 |
| 62 | help |
| 63 | The size of the cache-as-ram region required during bootblock |
| 64 | and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE |
| 65 | must add up to a power of 2. |
| 66 | |
| 67 | config DCACHE_RAM_MRC_VAR_SIZE |
| 68 | hex |
| 69 | default 0x30000 |
| 70 | help |
| 71 | The amount of cache-as-ram region required by the reference code. |
| 72 | |
Arthur Heymans | 5bb15f1 | 2018-12-22 16:02:25 +0100 | [diff] [blame] | 73 | config DCACHE_BSP_STACK_SIZE |
| 74 | hex |
| 75 | default 0x2000 |
| 76 | help |
| 77 | The amount of anticipated stack usage in CAR by bootblock and |
| 78 | other stages. |
| 79 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 80 | config HAVE_MRC |
| 81 | bool "Add a Memory Reference Code binary" |
| 82 | help |
| 83 | Select this option to add a Memory Reference Code binary to |
| 84 | the resulting coreboot image. |
| 85 | |
| 86 | Note: Without this binary coreboot will not work |
| 87 | |
| 88 | if HAVE_MRC |
| 89 | |
| 90 | config MRC_FILE |
| 91 | string "Intel Memory Reference Code path and filename" |
| 92 | depends on HAVE_MRC |
| 93 | default "mrc.bin" |
| 94 | help |
| 95 | The filename of the file to use as Memory Reference Code binary. |
| 96 | |
| 97 | config MRC_BIN_ADDRESS |
| 98 | hex |
| 99 | default 0xfffa0000 |
| 100 | |
Arthur Heymans | 4d56a06 | 2018-12-22 16:11:52 +0100 | [diff] [blame] | 101 | # The UEFI System Agent binary needs to be at a fixed offset in the flash |
| 102 | # and can therefore only reside in the COREBOOT fmap region |
| 103 | config RO_REGION_ONLY |
| 104 | string |
| 105 | depends on VBOOT |
| 106 | default "mrc.bin" |
| 107 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 108 | endif # HAVE_MRC |
| 109 | |
Patrick Georgi | e6e9493 | 2015-06-22 22:26:45 +0200 | [diff] [blame] | 110 | config HAVE_REFCODE_BLOB |
| 111 | depends on ARCH_X86 |
| 112 | bool "An external reference code blob should be put into cbfs." |
| 113 | default n |
| 114 | help |
| 115 | The reference code blob will be placed into cbfs. |
| 116 | |
| 117 | if HAVE_REFCODE_BLOB |
| 118 | |
| 119 | config REFCODE_BLOB_FILE |
| 120 | string "Path and filename to reference code blob." |
| 121 | default "refcode.elf" |
| 122 | help |
| 123 | The path and filename to the file to be added to cbfs. |
| 124 | |
| 125 | endif # HAVE_REFCODE_BLOB |
| 126 | |
Angel Pons | dbdd528 | 2021-06-14 12:14:48 +0200 | [diff] [blame] | 127 | source "src/soc/intel/broadwell/pch/Kconfig" |
| 128 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 129 | endif |