Lijian Zhao | 2f764f7 | 2017-07-14 11:09:10 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
Lijian Zhao | b269f87 | 2018-07-31 17:23:32 -0700 | [diff] [blame] | 4 | * Copyright (C) 2016-2018 Intel Corporation. |
Lijian Zhao | 2f764f7 | 2017-07-14 11:09:10 -0700 | [diff] [blame] | 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| 15 | |
| 16 | #include <chip.h> |
Pratik Prajapati | 201fa8f | 2017-08-16 11:42:40 -0700 | [diff] [blame] | 17 | #include <device/device.h> |
Lijian Zhao | 2f764f7 | 2017-07-14 11:09:10 -0700 | [diff] [blame] | 18 | #include <device/pci.h> |
| 19 | #include <fsp/api.h> |
Lijian Zhao | 2f764f7 | 2017-07-14 11:09:10 -0700 | [diff] [blame] | 20 | #include <fsp/util.h> |
Subrata Banik | 98376b8 | 2018-05-22 16:18:16 +0530 | [diff] [blame] | 21 | #include <intelblocks/acpi.h> |
Subrata Banik | f699c14 | 2018-06-08 17:57:37 +0530 | [diff] [blame] | 22 | #include <intelblocks/chip.h> |
Subrata Banik | 819b143 | 2018-09-28 19:56:54 +0530 | [diff] [blame] | 23 | #include <intelblocks/itss.h> |
Duncan Laurie | 2410cd9 | 2018-03-26 02:25:07 -0700 | [diff] [blame] | 24 | #include <intelblocks/xdci.h> |
Lijian Zhao | 2f764f7 | 2017-07-14 11:09:10 -0700 | [diff] [blame] | 25 | #include <romstage_handoff.h> |
Abhay kumar | fcf8820 | 2017-09-20 15:17:42 -0700 | [diff] [blame] | 26 | #include <soc/intel/common/vbt.h> |
Subrata Banik | 819b143 | 2018-09-28 19:56:54 +0530 | [diff] [blame] | 27 | #include <soc/itss.h> |
Pratik Prajapati | 9027e1b | 2017-08-23 17:37:43 -0700 | [diff] [blame] | 28 | #include <soc/pci_devs.h> |
Lijian Zhao | 2f764f7 | 2017-07-14 11:09:10 -0700 | [diff] [blame] | 29 | #include <soc/ramstage.h> |
| 30 | #include <string.h> |
| 31 | |
Lijian Zhao | 2b074d9 | 2017-08-17 14:25:24 -0700 | [diff] [blame] | 32 | #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) |
Subrata Banik | 98376b8 | 2018-05-22 16:18:16 +0530 | [diff] [blame] | 33 | const char *soc_acpi_name(const struct device *dev) |
Lijian Zhao | 2b074d9 | 2017-08-17 14:25:24 -0700 | [diff] [blame] | 34 | { |
| 35 | if (dev->path.type == DEVICE_PATH_DOMAIN) |
| 36 | return "PCI0"; |
| 37 | |
| 38 | if (dev->path.type != DEVICE_PATH_PCI) |
| 39 | return NULL; |
| 40 | |
| 41 | switch (dev->path.pci.devfn) { |
| 42 | case SA_DEVFN_ROOT: return "MCHC"; |
| 43 | case SA_DEVFN_IGD: return "GFX0"; |
| 44 | case PCH_DEVFN_ISH: return "ISHB"; |
| 45 | case PCH_DEVFN_XHCI: return "XHCI"; |
| 46 | case PCH_DEVFN_USBOTG: return "XDCI"; |
| 47 | case PCH_DEVFN_THERMAL: return "THRM"; |
| 48 | case PCH_DEVFN_I2C0: return "I2C0"; |
| 49 | case PCH_DEVFN_I2C1: return "I2C1"; |
| 50 | case PCH_DEVFN_I2C2: return "I2C2"; |
| 51 | case PCH_DEVFN_I2C3: return "I2C3"; |
| 52 | case PCH_DEVFN_CSE: return "CSE1"; |
| 53 | case PCH_DEVFN_CSE_2: return "CSE2"; |
| 54 | case PCH_DEVFN_CSE_IDER: return "CSED"; |
| 55 | case PCH_DEVFN_CSE_KT: return "CSKT"; |
| 56 | case PCH_DEVFN_CSE_3: return "CSE3"; |
| 57 | case PCH_DEVFN_SATA: return "SATA"; |
| 58 | case PCH_DEVFN_UART2: return "UAR2"; |
| 59 | case PCH_DEVFN_I2C4: return "I2C4"; |
| 60 | case PCH_DEVFN_I2C5: return "I2C5"; |
| 61 | case PCH_DEVFN_PCIE1: return "RP01"; |
| 62 | case PCH_DEVFN_PCIE2: return "RP02"; |
| 63 | case PCH_DEVFN_PCIE3: return "RP03"; |
| 64 | case PCH_DEVFN_PCIE4: return "RP04"; |
| 65 | case PCH_DEVFN_PCIE5: return "RP05"; |
| 66 | case PCH_DEVFN_PCIE6: return "RP06"; |
| 67 | case PCH_DEVFN_PCIE7: return "RP07"; |
| 68 | case PCH_DEVFN_PCIE8: return "RP08"; |
| 69 | case PCH_DEVFN_PCIE9: return "RP09"; |
| 70 | case PCH_DEVFN_PCIE10: return "RP10"; |
| 71 | case PCH_DEVFN_PCIE11: return "RP11"; |
| 72 | case PCH_DEVFN_PCIE12: return "RP12"; |
Lijian Zhao | 580bc41 | 2017-10-04 13:43:47 -0700 | [diff] [blame] | 73 | case PCH_DEVFN_PCIE13: return "RP13"; |
| 74 | case PCH_DEVFN_PCIE14: return "RP14"; |
| 75 | case PCH_DEVFN_PCIE15: return "RP15"; |
| 76 | case PCH_DEVFN_PCIE16: return "RP16"; |
praveen hodagatta pranesh | e26c4a4 | 2018-09-20 03:49:45 +0800 | [diff] [blame] | 77 | case PCH_DEVFN_PCIE17: return "RP17"; |
| 78 | case PCH_DEVFN_PCIE18: return "RP18"; |
| 79 | case PCH_DEVFN_PCIE19: return "RP19"; |
| 80 | case PCH_DEVFN_PCIE20: return "RP20"; |
| 81 | case PCH_DEVFN_PCIE21: return "RP21"; |
| 82 | case PCH_DEVFN_PCIE22: return "RP22"; |
| 83 | case PCH_DEVFN_PCIE23: return "RP23"; |
| 84 | case PCH_DEVFN_PCIE24: return "RP24"; |
Lijian Zhao | 2b074d9 | 2017-08-17 14:25:24 -0700 | [diff] [blame] | 85 | case PCH_DEVFN_UART0: return "UAR0"; |
| 86 | case PCH_DEVFN_UART1: return "UAR1"; |
| 87 | case PCH_DEVFN_GSPI0: return "SPI0"; |
| 88 | case PCH_DEVFN_GSPI1: return "SPI1"; |
| 89 | case PCH_DEVFN_GSPI2: return "SPI2"; |
| 90 | case PCH_DEVFN_EMMC: return "EMMC"; |
| 91 | case PCH_DEVFN_SDCARD: return "SDXC"; |
| 92 | case PCH_DEVFN_LPC: return "LPCB"; |
| 93 | case PCH_DEVFN_P2SB: return "P2SB"; |
| 94 | case PCH_DEVFN_PMC: return "PMC_"; |
| 95 | case PCH_DEVFN_HDA: return "HDAS"; |
| 96 | case PCH_DEVFN_SMBUS: return "SBUS"; |
| 97 | case PCH_DEVFN_SPI: return "FSPI"; |
| 98 | case PCH_DEVFN_GBE: return "IGBE"; |
| 99 | case PCH_DEVFN_TRACEHUB:return "THUB"; |
| 100 | } |
| 101 | |
| 102 | return NULL; |
| 103 | } |
| 104 | #endif |
| 105 | |
Lijian Zhao | 2f764f7 | 2017-07-14 11:09:10 -0700 | [diff] [blame] | 106 | void soc_init_pre_device(void *chip_info) |
| 107 | { |
Subrata Banik | 819b143 | 2018-09-28 19:56:54 +0530 | [diff] [blame] | 108 | /* Snapshot the current GPIO IRQ polarities. FSP is setting a |
| 109 | * default policy that doesn't honor boards' requirements. */ |
| 110 | itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); |
| 111 | |
Lijian Zhao | 2f764f7 | 2017-07-14 11:09:10 -0700 | [diff] [blame] | 112 | /* Perform silicon specific init. */ |
| 113 | fsp_silicon_init(romstage_handoff_is_resume()); |
Subrata Banik | a8733e3 | 2018-01-23 16:40:56 +0530 | [diff] [blame] | 114 | |
| 115 | /* Display FIRMWARE_VERSION_INFO_HOB */ |
| 116 | fsp_display_fvi_version_hob(); |
Subrata Banik | 819b143 | 2018-09-28 19:56:54 +0530 | [diff] [blame] | 117 | |
| 118 | /* Restore GPIO IRQ polarities back to previous settings. */ |
| 119 | itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); |
Lijian Zhao | 2f764f7 | 2017-07-14 11:09:10 -0700 | [diff] [blame] | 120 | } |
| 121 | |
Elyes HAOUAS | 3c8b5d0 | 2018-05-27 16:57:24 +0200 | [diff] [blame] | 122 | static void pci_domain_set_resources(struct device *dev) |
Pratik Prajapati | 201fa8f | 2017-08-16 11:42:40 -0700 | [diff] [blame] | 123 | { |
| 124 | assign_resources(dev->link_list); |
| 125 | } |
| 126 | |
| 127 | static struct device_operations pci_domain_ops = { |
| 128 | .read_resources = &pci_domain_read_resources, |
| 129 | .set_resources = &pci_domain_set_resources, |
| 130 | .scan_bus = &pci_domain_scan_bus, |
Lijian Zhao | 2b074d9 | 2017-08-17 14:25:24 -0700 | [diff] [blame] | 131 | #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) |
| 132 | .acpi_name = &soc_acpi_name, |
| 133 | #endif |
Pratik Prajapati | 201fa8f | 2017-08-16 11:42:40 -0700 | [diff] [blame] | 134 | }; |
| 135 | |
| 136 | static struct device_operations cpu_bus_ops = { |
| 137 | .read_resources = DEVICE_NOOP, |
| 138 | .set_resources = DEVICE_NOOP, |
| 139 | .enable_resources = DEVICE_NOOP, |
| 140 | .init = DEVICE_NOOP, |
Shaunak Saha | 95b6175 | 2017-10-04 23:08:40 -0700 | [diff] [blame] | 141 | .acpi_fill_ssdt_generator = generate_cpu_entries, |
Pratik Prajapati | 201fa8f | 2017-08-16 11:42:40 -0700 | [diff] [blame] | 142 | }; |
| 143 | |
Elyes HAOUAS | 3c8b5d0 | 2018-05-27 16:57:24 +0200 | [diff] [blame] | 144 | static void soc_enable(struct device *dev) |
Pratik Prajapati | 201fa8f | 2017-08-16 11:42:40 -0700 | [diff] [blame] | 145 | { |
| 146 | /* Set the operations if it is a special bus type */ |
| 147 | if (dev->path.type == DEVICE_PATH_DOMAIN) |
| 148 | dev->ops = &pci_domain_ops; |
| 149 | else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) |
| 150 | dev->ops = &cpu_bus_ops; |
| 151 | } |
| 152 | |
Lijian Zhao | 2f764f7 | 2017-07-14 11:09:10 -0700 | [diff] [blame] | 153 | struct chip_operations soc_intel_cannonlake_ops = { |
| 154 | CHIP_NAME("Intel Cannonlake") |
Pratik Prajapati | 201fa8f | 2017-08-16 11:42:40 -0700 | [diff] [blame] | 155 | .enable_dev = &soc_enable, |
Lijian Zhao | 2f764f7 | 2017-07-14 11:09:10 -0700 | [diff] [blame] | 156 | .init = &soc_init_pre_device, |
| 157 | }; |