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review.coreboot.org / coreboot / 1e24bf3f719f82c16fd577e87900e1aa0fd6605b / . / src / mainboard / intel / galileo / gen1.h
blob: 23b23091d2ee878a19dfa90d0a41fb7f7bc51fc1 [file] [log] [blame]
Lee Leahy274d20a2016-05-15 13:52:36 -0700[diff] [blame]1/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2016 Intel Corp.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
Lee Leahy5ef051a2016-04-29 15:16:54 -0700[diff] [blame]16/* PCIe reset pin */
17#define GEN1_PCI_RESET_RESUMEWELL_GPIO 3
18
Lee Leahy15843bd2016-05-15 15:05:56 -0700[diff] [blame]19/* Jumper J2 determines the slave address of Cypress I/O GPIO expander */
20#define GALILEO_DETERMINE_IOEXP_SLA_RESUMEWELL_GPIO 5
21
Lee Leahy274d20a2016-05-15 13:52:36 -0700[diff] [blame]22static const struct reg_script gen1_gpio_init[] = {
23 /* Initialize the legacy GPIO controller */
24 REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGEN_CORE_WELL, 0x03),
25 REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGIO_CORE_WELL, 0x00),
26 REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGLVL_CORE_WELL, 0x00),
27 REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGTPE_CORE_WELL, 0x00),
28 REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGTNE_CORE_WELL, 0x00),
29 REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGGPE_CORE_WELL, 0x00),
30 REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGSMI_CORE_WELL, 0x00),
31 REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGTS_CORE_WELL, 0x03),
32 REG_LEG_GPIO_WRITE(R_QNC_GPIO_CNMIEN_CORE_WELL, 0x00),
33
34 REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGEN_RESUME_WELL, 0x3f),
35 REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGIO_RESUME_WELL, 0x21),
36 REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGLVL_RESUME_WELL, 0x14),
37 REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGTPE_RESUME_WELL, 0x00),
38 REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGTNE_RESUME_WELL, 0x00),
39 REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGGPE_RESUME_WELL, 0x00),
40 REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGSMI_RESUME_WELL, 0x00),
41 REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGTS_RESUME_WELL, 0x3f),
42 REG_LEG_GPIO_WRITE(R_QNC_GPIO_RNMIEN_RESUME_WELL, 0x00),
43
44 /* Initialize the GPIO controller */
45 REG_GPIO_WRITE(GPIO_INTEN, 0),
46 REG_GPIO_WRITE(GPIO_INTSTATUS, 0),
47 REG_GPIO_WRITE(GPIO_SWPORTA_DR, 5),
48 REG_GPIO_WRITE(GPIO_SWPORTA_DDR, 0x15),
49 REG_GPIO_WRITE(GPIO_INTMASK, 0),
50 REG_GPIO_WRITE(GPIO_INTTYPE_LEVEL, 0),
51 REG_GPIO_WRITE(GPIO_INT_POLARITY, 0),
52 REG_GPIO_WRITE(GPIO_DEBOUNCE, 0),
53 REG_GPIO_WRITE(GPIO_LS_SYNC, 0),
54
55 /* Toggle the Cypress reset line */
56 REG_GPIO_OR(GPIO_SWPORTA_DR, BIT4),
57 REG_GPIO_AND(GPIO_SWPORTA_DR, ~BIT4),
Lee Leahy15843bd2016-05-15 15:05:56 -0700[diff] [blame]58
59 REG_SCRIPT_END
60};
61
Lee Leahybc518d52016-05-30 15:01:06 -0700[diff] [blame]62static const struct reg_script gen1_hsuart0_0x20[] = {
63 /* Route UART0_TXD to LVL_TXD -> IO1 -> DIGITAL 1
64 * Set IO1_MUX (EXP.PORT3_5) output, low
65 * Set LVL_OE (GPIO_SUS2) output, high
66 */
67
68 REG_I2C_WRITE(GEN1_I2C_GPIO_EXP_0x20, GEN1_GPIO_EXP_PORT_SELECT, 3),
69 REG_I2C_AND(GEN1_I2C_GPIO_EXP_0x20, GEN1_GPIO_EXP_PORT_DIR, ~BIT5),
70 REG_I2C_AND(GEN1_I2C_GPIO_EXP_0x20, GEN1_GPIO_EXP_OUTPUT3, ~BIT5),
71
72 /* Route DIGITAL 0 -> IO0 -> LVL_RXD -> UART0_RXD
73 * Set IO0_MUX (EXP.PORT3_4) output, low
74 * Set LVL_OE (GPIO_SUS2) output, high
75 */
76 REG_I2C_WRITE(GEN1_I2C_GPIO_EXP_0x20, GEN1_GPIO_EXP_PORT_SELECT, 3),
77 REG_I2C_AND(GEN1_I2C_GPIO_EXP_0x20, GEN1_GPIO_EXP_PORT_DIR, ~BIT4),
78 REG_I2C_AND(GEN1_I2C_GPIO_EXP_0x20, GEN1_GPIO_EXP_OUTPUT3, ~BIT4),
79
80 REG_LEG_GPIO_OR(R_QNC_GPIO_RGEN_RESUME_WELL, BIT2),
81 REG_LEG_GPIO_AND(R_QNC_GPIO_RGIO_RESUME_WELL, ~BIT2),
82 REG_LEG_GPIO_OR(R_QNC_GPIO_RGLVL_RESUME_WELL, BIT2),
83
84 REG_SCRIPT_END
85};
86
87static const struct reg_script gen1_hsuart0_0x21[] = {
88 /* Route UART0_TXD to LVL_TXD -> IO1 -> DIGITAL 1
89 * Set IO1_MUX (EXP.PORT3_5) output, low
90 * Set LVL_OE (GPIO_SUS2) output, high
91 */
92
93 REG_I2C_WRITE(GEN1_I2C_GPIO_EXP_0x21, GEN1_GPIO_EXP_PORT_SELECT, 3),
94 REG_I2C_AND(GEN1_I2C_GPIO_EXP_0x21, GEN1_GPIO_EXP_PORT_DIR, ~BIT5),
95 REG_I2C_AND(GEN1_I2C_GPIO_EXP_0x21, GEN1_GPIO_EXP_OUTPUT3, ~BIT5),
96
97 /* Route DIGITAL 0 -> IO0 -> LVL_RXD -> UART0_RXD
98 * Set IO0_MUX (EXP.PORT3_4) output, low
99 * Set LVL_OE (GPIO_SUS2) output, high
100 */
101 REG_I2C_WRITE(GEN1_I2C_GPIO_EXP_0x21, GEN1_GPIO_EXP_PORT_SELECT, 3),
102 REG_I2C_AND(GEN1_I2C_GPIO_EXP_0x21, GEN1_GPIO_EXP_PORT_DIR, ~BIT4),
103 REG_I2C_AND(GEN1_I2C_GPIO_EXP_0x21, GEN1_GPIO_EXP_OUTPUT3, ~BIT4),
104
105 REG_LEG_GPIO_OR(R_QNC_GPIO_RGEN_RESUME_WELL, BIT2),
106 REG_LEG_GPIO_AND(R_QNC_GPIO_RGIO_RESUME_WELL, ~BIT2),
107 REG_LEG_GPIO_OR(R_QNC_GPIO_RGLVL_RESUME_WELL, BIT2),
108
109 REG_SCRIPT_END
110};
111
Lee Leahy15843bd2016-05-15 15:05:56 -0700[diff] [blame]112static const struct reg_script gen1_i2c_0x20_init[] = {
113 /* Route I2C pins to Arduino header:
114 * Clear I2C_MUX (GPORT1_BIT5) to route I2C to Arduino Shield connector
115 *
116 * I2C_SDA -> ANALOG_A4
117 * I2C_SCL -> ANALOG_A5
118 */
119 REG_I2C_WRITE(GEN1_I2C_GPIO_EXP_0x20, GEN1_GPIO_EXP_PORT_SELECT, 1),
120 REG_I2C_AND(GEN1_I2C_GPIO_EXP_0x20, GEN1_GPIO_EXP_PORT_DIR, ~BIT5),
121 REG_I2C_WRITE(GEN1_I2C_GPIO_EXP_0x20, GEN1_GPIO_EXP_OUTPUT1, ~BIT5),
122
123 /* Set all GPIO expander pins connected to the Reset Button as inputs
124 * Configure RESET_N_SHLD (GPORT5_BIT0) and SW_RESET_N_SHLD
125 * (GPORT5_BIT1) as inputs
126 */
127 REG_I2C_WRITE(GEN1_I2C_GPIO_EXP_0x20, GEN1_GPIO_EXP_PORT_SELECT, 5),
128 REG_I2C_OR(GEN1_I2C_GPIO_EXP_0x20, GEN1_GPIO_EXP_PORT_DIR, BIT1 | BIT0),
129
130 REG_SCRIPT_END
131};
132
133static const struct reg_script gen1_i2c_0x21_init[] = {
134 /* Route I2C pins to Arduino header:
135 * Clear I2C_MUX (GPORT1_BIT5) to route I2C to Arduino Shield connector
136 *
137 * I2C_SDA -> ANALOG_A4
138 * I2C_SCL -> ANALOG_A5
139 */
140 REG_I2C_WRITE(GEN1_I2C_GPIO_EXP_0x21, GEN1_GPIO_EXP_PORT_SELECT, 1),
141 REG_I2C_AND(GEN1_I2C_GPIO_EXP_0x21, GEN1_GPIO_EXP_PORT_DIR, ~BIT5),
142 REG_I2C_AND(GEN1_I2C_GPIO_EXP_0x21, GEN1_GPIO_EXP_OUTPUT1, ~BIT5),
143
144 /* Set all GPIO expander pins connected to the Reset Button as inputs
145 * Configure RESET_N_SHLD (GPORT5_BIT0) and SW_RESET_N_SHLD
146 * (GPORT5_BIT1) as inputs
147 */
148 REG_I2C_WRITE(GEN1_I2C_GPIO_EXP_0x21, GEN1_GPIO_EXP_PORT_SELECT, 5),
149 REG_I2C_OR(GEN1_I2C_GPIO_EXP_0x21, GEN1_GPIO_EXP_PORT_DIR, BIT1 | BIT0),
150
Lee Leahy274d20a2016-05-15 13:52:36 -0700[diff] [blame]151 REG_SCRIPT_END
152};