Gitiles
Code Review Sign In
review.coreboot.org / coreboot / 15843bdad076149e9d04dcfaa07f4eedda84acfa / . / src / mainboard / intel / galileo / gen1.h
blob: 26335dad6188795b665bafba9f46885cf28ac3cf [file] [log] [blame]
Lee Leahy274d20a2016-05-15 13:52:36 -0700[diff] [blame]1/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2016 Intel Corp.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
Lee Leahy15843bd2016-05-15 15:05:56 -0700[diff] [blame^]16/* Jumper J2 determines the slave address of Cypress I/O GPIO expander */
17#define GALILEO_DETERMINE_IOEXP_SLA_RESUMEWELL_GPIO 5
18
Lee Leahy274d20a2016-05-15 13:52:36 -0700[diff] [blame]19static const struct reg_script gen1_gpio_init[] = {
20 /* Initialize the legacy GPIO controller */
21 REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGEN_CORE_WELL, 0x03),
22 REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGIO_CORE_WELL, 0x00),
23 REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGLVL_CORE_WELL, 0x00),
24 REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGTPE_CORE_WELL, 0x00),
25 REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGTNE_CORE_WELL, 0x00),
26 REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGGPE_CORE_WELL, 0x00),
27 REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGSMI_CORE_WELL, 0x00),
28 REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGTS_CORE_WELL, 0x03),
29 REG_LEG_GPIO_WRITE(R_QNC_GPIO_CNMIEN_CORE_WELL, 0x00),
30
31 REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGEN_RESUME_WELL, 0x3f),
32 REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGIO_RESUME_WELL, 0x21),
33 REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGLVL_RESUME_WELL, 0x14),
34 REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGTPE_RESUME_WELL, 0x00),
35 REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGTNE_RESUME_WELL, 0x00),
36 REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGGPE_RESUME_WELL, 0x00),
37 REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGSMI_RESUME_WELL, 0x00),
38 REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGTS_RESUME_WELL, 0x3f),
39 REG_LEG_GPIO_WRITE(R_QNC_GPIO_RNMIEN_RESUME_WELL, 0x00),
40
41 /* Initialize the GPIO controller */
42 REG_GPIO_WRITE(GPIO_INTEN, 0),
43 REG_GPIO_WRITE(GPIO_INTSTATUS, 0),
44 REG_GPIO_WRITE(GPIO_SWPORTA_DR, 5),
45 REG_GPIO_WRITE(GPIO_SWPORTA_DDR, 0x15),
46 REG_GPIO_WRITE(GPIO_INTMASK, 0),
47 REG_GPIO_WRITE(GPIO_INTTYPE_LEVEL, 0),
48 REG_GPIO_WRITE(GPIO_INT_POLARITY, 0),
49 REG_GPIO_WRITE(GPIO_DEBOUNCE, 0),
50 REG_GPIO_WRITE(GPIO_LS_SYNC, 0),
51
52 /* Toggle the Cypress reset line */
53 REG_GPIO_OR(GPIO_SWPORTA_DR, BIT4),
54 REG_GPIO_AND(GPIO_SWPORTA_DR, ~BIT4),
Lee Leahy15843bd2016-05-15 15:05:56 -0700[diff] [blame^]55
56 REG_SCRIPT_END
57};
58
59static const struct reg_script gen1_i2c_0x20_init[] = {
60 /* Route I2C pins to Arduino header:
61 * Clear I2C_MUX (GPORT1_BIT5) to route I2C to Arduino Shield connector
62 *
63 * I2C_SDA -> ANALOG_A4
64 * I2C_SCL -> ANALOG_A5
65 */
66 REG_I2C_WRITE(GEN1_I2C_GPIO_EXP_0x20, GEN1_GPIO_EXP_PORT_SELECT, 1),
67 REG_I2C_AND(GEN1_I2C_GPIO_EXP_0x20, GEN1_GPIO_EXP_PORT_DIR, ~BIT5),
68 REG_I2C_WRITE(GEN1_I2C_GPIO_EXP_0x20, GEN1_GPIO_EXP_OUTPUT1, ~BIT5),
69
70 /* Set all GPIO expander pins connected to the Reset Button as inputs
71 * Configure RESET_N_SHLD (GPORT5_BIT0) and SW_RESET_N_SHLD
72 * (GPORT5_BIT1) as inputs
73 */
74 REG_I2C_WRITE(GEN1_I2C_GPIO_EXP_0x20, GEN1_GPIO_EXP_PORT_SELECT, 5),
75 REG_I2C_OR(GEN1_I2C_GPIO_EXP_0x20, GEN1_GPIO_EXP_PORT_DIR, BIT1 | BIT0),
76
77 REG_SCRIPT_END
78};
79
80static const struct reg_script gen1_i2c_0x21_init[] = {
81 /* Route I2C pins to Arduino header:
82 * Clear I2C_MUX (GPORT1_BIT5) to route I2C to Arduino Shield connector
83 *
84 * I2C_SDA -> ANALOG_A4
85 * I2C_SCL -> ANALOG_A5
86 */
87 REG_I2C_WRITE(GEN1_I2C_GPIO_EXP_0x21, GEN1_GPIO_EXP_PORT_SELECT, 1),
88 REG_I2C_AND(GEN1_I2C_GPIO_EXP_0x21, GEN1_GPIO_EXP_PORT_DIR, ~BIT5),
89 REG_I2C_AND(GEN1_I2C_GPIO_EXP_0x21, GEN1_GPIO_EXP_OUTPUT1, ~BIT5),
90
91 /* Set all GPIO expander pins connected to the Reset Button as inputs
92 * Configure RESET_N_SHLD (GPORT5_BIT0) and SW_RESET_N_SHLD
93 * (GPORT5_BIT1) as inputs
94 */
95 REG_I2C_WRITE(GEN1_I2C_GPIO_EXP_0x21, GEN1_GPIO_EXP_PORT_SELECT, 5),
96 REG_I2C_OR(GEN1_I2C_GPIO_EXP_0x21, GEN1_GPIO_EXP_PORT_DIR, BIT1 | BIT0),
97
Lee Leahy274d20a2016-05-15 13:52:36 -0700[diff] [blame]98 REG_SCRIPT_END
99};