Angel Pons | 1ddb894 | 2020-04-04 18:51:26 +0200 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | /* This file is part of the coreboot project. */ |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 3 | |
Stefan Reinauer | 08dc357 | 2013-05-14 16:57:50 -0700 | [diff] [blame] | 4 | /* Clock setup for SMDK5250 board based on EXYNOS5 */ |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 5 | |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 6 | #include <device/mmio.h> |
Julius Werner | 1ed0c8c | 2014-10-20 13:16:29 -0700 | [diff] [blame] | 7 | #include <soc/clk.h> |
| 8 | #include <soc/dp.h> |
| 9 | #include <soc/setup.h> |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 10 | |
David Hendricks | 0d4f97e | 2013-02-03 18:09:58 -0800 | [diff] [blame] | 11 | void system_clock_init(struct mem_timings *mem, |
| 12 | struct arm_clk_ratios *arm_clk_ratio) |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 13 | { |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 14 | u32 val, tmp; |
| 15 | |
| 16 | /* Turn on the MCT as early as possible. */ |
Julius Werner | fa938c7 | 2013-08-29 14:17:36 -0700 | [diff] [blame] | 17 | exynos_mct->g_tcon |= (1 << 8); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 18 | |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 19 | clrbits32(&exynos_clock->src_cpu, MUX_APLL_SEL_MASK); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 20 | do { |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 21 | val = read32(&exynos_clock->mux_stat_cpu); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 22 | } while ((val | MUX_APLL_SEL_MASK) != val); |
| 23 | |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 24 | clrbits32(&exynos_clock->src_core1, MUX_MPLL_SEL_MASK); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 25 | do { |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 26 | val = read32(&exynos_clock->mux_stat_core1); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 27 | } while ((val | MUX_MPLL_SEL_MASK) != val); |
| 28 | |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 29 | clrbits32(&exynos_clock->src_top2, MUX_CPLL_SEL_MASK); |
| 30 | clrbits32(&exynos_clock->src_top2, MUX_EPLL_SEL_MASK); |
| 31 | clrbits32(&exynos_clock->src_top2, MUX_VPLL_SEL_MASK); |
| 32 | clrbits32(&exynos_clock->src_top2, MUX_GPLL_SEL_MASK); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 33 | tmp = MUX_CPLL_SEL_MASK | MUX_EPLL_SEL_MASK | MUX_VPLL_SEL_MASK |
| 34 | | MUX_GPLL_SEL_MASK; |
| 35 | do { |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 36 | val = read32(&exynos_clock->mux_stat_top2); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 37 | } while ((val | tmp) != val); |
| 38 | |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 39 | clrbits32(&exynos_clock->src_cdrex, MUX_BPLL_SEL_MASK); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 40 | do { |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 41 | val = read32(&exynos_clock->mux_stat_cdrex); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 42 | } while ((val | MUX_BPLL_SEL_MASK) != val); |
| 43 | |
| 44 | /* PLL locktime */ |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 45 | write32(&exynos_clock->apll_lock, APLL_LOCK_VAL); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 46 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 47 | write32(&exynos_clock->mpll_lock, MPLL_LOCK_VAL); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 48 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 49 | write32(&exynos_clock->bpll_lock, BPLL_LOCK_VAL); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 50 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 51 | write32(&exynos_clock->cpll_lock, CPLL_LOCK_VAL); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 52 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 53 | write32(&exynos_clock->gpll_lock, GPLL_LOCK_VAL); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 54 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 55 | write32(&exynos_clock->epll_lock, EPLL_LOCK_VAL); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 56 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 57 | write32(&exynos_clock->vpll_lock, VPLL_LOCK_VAL); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 58 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 59 | write32(&exynos_clock->pll_div2_sel, CLK_REG_DISABLE); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 60 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 61 | write32(&exynos_clock->src_cpu, MUX_HPM_SEL_MASK); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 62 | do { |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 63 | val = read32(&exynos_clock->mux_stat_cpu); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 64 | } while ((val | HPM_SEL_SCLK_MPLL) != val); |
| 65 | |
| 66 | val = arm_clk_ratio->arm2_ratio << 28 |
| 67 | | arm_clk_ratio->apll_ratio << 24 |
| 68 | | arm_clk_ratio->pclk_dbg_ratio << 20 |
| 69 | | arm_clk_ratio->atb_ratio << 16 |
| 70 | | arm_clk_ratio->periph_ratio << 12 |
| 71 | | arm_clk_ratio->acp_ratio << 8 |
| 72 | | arm_clk_ratio->cpud_ratio << 4 |
| 73 | | arm_clk_ratio->arm_ratio; |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 74 | write32(&exynos_clock->div_cpu0, val); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 75 | do { |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 76 | val = read32(&exynos_clock->div_stat_cpu0); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 77 | } while (0 != val); |
| 78 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 79 | write32(&exynos_clock->div_cpu1, CLK_DIV_CPU1_VAL); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 80 | do { |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 81 | val = read32(&exynos_clock->div_stat_cpu1); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 82 | } while (0 != val); |
| 83 | |
David Hendricks | f05e871 | 2013-08-06 15:17:37 -0700 | [diff] [blame] | 84 | /* switch A15 clock source to OSC clock before changing APLL */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 85 | clrbits32(&exynos_clock->src_cpu, APLL_FOUT); |
David Hendricks | f05e871 | 2013-08-06 15:17:37 -0700 | [diff] [blame] | 86 | |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 87 | /* Set APLL */ |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 88 | write32(&exynos_clock->apll_con1, APLL_CON1_VAL); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 89 | val = set_pll(arm_clk_ratio->apll_mdiv, arm_clk_ratio->apll_pdiv, |
| 90 | arm_clk_ratio->apll_sdiv); |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 91 | write32(&exynos_clock->apll_con0, val); |
| 92 | while ((read32(&exynos_clock->apll_con0) & APLL_CON0_LOCKED) == 0) |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 93 | ; |
| 94 | |
David Hendricks | f05e871 | 2013-08-06 15:17:37 -0700 | [diff] [blame] | 95 | /* now it is safe to switch to APLL */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 96 | setbits32(&exynos_clock->src_cpu, APLL_FOUT); |
David Hendricks | f05e871 | 2013-08-06 15:17:37 -0700 | [diff] [blame] | 97 | |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 98 | /* Set MPLL */ |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 99 | write32(&exynos_clock->mpll_con1, MPLL_CON1_VAL); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 100 | val = set_pll(mem->mpll_mdiv, mem->mpll_pdiv, mem->mpll_sdiv); |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 101 | write32(&exynos_clock->mpll_con0, val); |
| 102 | while ((read32(&exynos_clock->mpll_con0) & MPLL_CON0_LOCKED) == 0) |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 103 | ; |
| 104 | |
| 105 | /* |
| 106 | * Configure MUX_MPLL_FOUT to choose the direct clock source |
| 107 | * path and avoid the fixed DIV/2 block to save power |
| 108 | */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 109 | setbits32(&exynos_clock->pll_div2_sel, MUX_MPLL_FOUT_SEL); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 110 | |
| 111 | /* Set BPLL */ |
| 112 | if (mem->use_bpll) { |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 113 | write32(&exynos_clock->bpll_con1, BPLL_CON1_VAL); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 114 | val = set_pll(mem->bpll_mdiv, mem->bpll_pdiv, mem->bpll_sdiv); |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 115 | write32(&exynos_clock->bpll_con0, val); |
| 116 | while ((read32(&exynos_clock->bpll_con0) & BPLL_CON0_LOCKED) == 0) |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 117 | ; |
| 118 | |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 119 | setbits32(&exynos_clock->pll_div2_sel, MUX_BPLL_FOUT_SEL); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 120 | } |
| 121 | |
| 122 | /* Set CPLL */ |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 123 | write32(&exynos_clock->cpll_con1, CPLL_CON1_VAL); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 124 | val = set_pll(mem->cpll_mdiv, mem->cpll_pdiv, mem->cpll_sdiv); |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 125 | write32(&exynos_clock->cpll_con0, val); |
| 126 | while ((read32(&exynos_clock->cpll_con0) & CPLL_CON0_LOCKED) == 0) |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 127 | ; |
| 128 | |
| 129 | /* Set GPLL */ |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 130 | write32(&exynos_clock->gpll_con1, GPLL_CON1_VAL); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 131 | val = set_pll(mem->gpll_mdiv, mem->gpll_pdiv, mem->gpll_sdiv); |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 132 | write32(&exynos_clock->gpll_con0, val); |
| 133 | while ((read32(&exynos_clock->gpll_con0) & GPLL_CON0_LOCKED) == 0) |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 134 | ; |
| 135 | |
| 136 | /* Set EPLL */ |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 137 | write32(&exynos_clock->epll_con2, EPLL_CON2_VAL); |
| 138 | write32(&exynos_clock->epll_con1, EPLL_CON1_VAL); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 139 | val = set_pll(mem->epll_mdiv, mem->epll_pdiv, mem->epll_sdiv); |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 140 | write32(&exynos_clock->epll_con0, val); |
| 141 | while ((read32(&exynos_clock->epll_con0) & EPLL_CON0_LOCKED) == 0) |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 142 | ; |
| 143 | |
| 144 | /* Set VPLL */ |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 145 | write32(&exynos_clock->vpll_con2, VPLL_CON2_VAL); |
| 146 | write32(&exynos_clock->vpll_con1, VPLL_CON1_VAL); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 147 | val = set_pll(mem->vpll_mdiv, mem->vpll_pdiv, mem->vpll_sdiv); |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 148 | write32(&exynos_clock->vpll_con0, val); |
| 149 | while ((read32(&exynos_clock->vpll_con0) & VPLL_CON0_LOCKED) == 0) |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 150 | ; |
| 151 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 152 | write32(&exynos_clock->src_core0, CLK_SRC_CORE0_VAL); |
| 153 | write32(&exynos_clock->div_core0, CLK_DIV_CORE0_VAL); |
| 154 | while (read32(&exynos_clock->div_stat_core0) != 0) |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 155 | ; |
| 156 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 157 | write32(&exynos_clock->div_core1, CLK_DIV_CORE1_VAL); |
| 158 | while (read32(&exynos_clock->div_stat_core1) != 0) |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 159 | ; |
| 160 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 161 | write32(&exynos_clock->div_sysrgt, CLK_DIV_SYSRGT_VAL); |
| 162 | while (read32(&exynos_clock->div_stat_sysrgt) != 0) |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 163 | ; |
| 164 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 165 | write32(&exynos_clock->div_acp, CLK_DIV_ACP_VAL); |
| 166 | while (read32(&exynos_clock->div_stat_acp) != 0) |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 167 | ; |
| 168 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 169 | write32(&exynos_clock->div_syslft, CLK_DIV_SYSLFT_VAL); |
| 170 | while (read32(&exynos_clock->div_stat_syslft) != 0) |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 171 | ; |
| 172 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 173 | write32(&exynos_clock->src_top0, CLK_SRC_TOP0_VAL); |
| 174 | write32(&exynos_clock->src_top1, CLK_SRC_TOP1_VAL); |
| 175 | write32(&exynos_clock->src_top2, TOP2_VAL); |
| 176 | write32(&exynos_clock->src_top3, CLK_SRC_TOP3_VAL); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 177 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 178 | write32(&exynos_clock->div_top0, CLK_DIV_TOP0_VAL); |
| 179 | while (read32(&exynos_clock->div_stat_top0)) |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 180 | ; |
| 181 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 182 | write32(&exynos_clock->div_top1, CLK_DIV_TOP1_VAL); |
| 183 | while (read32(&exynos_clock->div_stat_top1)) |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 184 | ; |
| 185 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 186 | write32(&exynos_clock->src_lex, CLK_SRC_LEX_VAL); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 187 | while (1) { |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 188 | val = read32(&exynos_clock->mux_stat_lex); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 189 | if (val == (val | 1)) |
| 190 | break; |
| 191 | } |
| 192 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 193 | write32(&exynos_clock->div_lex, CLK_DIV_LEX_VAL); |
| 194 | while (read32(&exynos_clock->div_stat_lex)) |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 195 | ; |
| 196 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 197 | write32(&exynos_clock->div_r0x, CLK_DIV_R0X_VAL); |
| 198 | while (read32(&exynos_clock->div_stat_r0x)) |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 199 | ; |
| 200 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 201 | write32(&exynos_clock->div_r0x, CLK_DIV_R0X_VAL); |
| 202 | while (read32(&exynos_clock->div_stat_r0x)) |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 203 | ; |
| 204 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 205 | write32(&exynos_clock->div_r1x, CLK_DIV_R1X_VAL); |
| 206 | while (read32(&exynos_clock->div_stat_r1x)) |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 207 | ; |
| 208 | |
| 209 | if (mem->use_bpll) { |
Julius Werner | 9418476 | 2015-02-19 20:19:23 -0800 | [diff] [blame] | 210 | write32(&exynos_clock->src_cdrex, MUX_BPLL_SEL_MASK | |
| 211 | MUX_MCLK_CDREX_SEL | MUX_MCLK_DPHY_SEL); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 212 | } else { |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 213 | write32(&exynos_clock->src_cdrex, CLK_REG_DISABLE); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 214 | } |
| 215 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 216 | write32(&exynos_clock->div_cdrex, CLK_DIV_CDREX_VAL); |
| 217 | while (read32(&exynos_clock->div_stat_cdrex)) |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 218 | ; |
| 219 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 220 | val = read32(&exynos_clock->src_cpu); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 221 | val |= CLK_SRC_CPU_VAL; |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 222 | write32(&exynos_clock->src_cpu, val); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 223 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 224 | val = read32(&exynos_clock->src_top2); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 225 | val |= CLK_SRC_TOP2_VAL; |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 226 | write32(&exynos_clock->src_top2, val); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 227 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 228 | val = read32(&exynos_clock->src_core1); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 229 | val |= CLK_SRC_CORE1_VAL; |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 230 | write32(&exynos_clock->src_core1, val); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 231 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 232 | write32(&exynos_clock->src_fsys, CLK_SRC_FSYS0_VAL); |
| 233 | write32(&exynos_clock->div_fsys0, CLK_DIV_FSYS0_VAL); |
| 234 | while (read32(&exynos_clock->div_stat_fsys0)) |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 235 | ; |
| 236 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 237 | write32(&exynos_clock->clkout_cmu_cpu, CLK_REG_DISABLE); |
| 238 | write32(&exynos_clock->clkout_cmu_core, CLK_REG_DISABLE); |
| 239 | write32(&exynos_clock->clkout_cmu_acp, CLK_REG_DISABLE); |
| 240 | write32(&exynos_clock->clkout_cmu_top, CLK_REG_DISABLE); |
| 241 | write32(&exynos_clock->clkout_cmu_lex, CLK_REG_DISABLE); |
| 242 | write32(&exynos_clock->clkout_cmu_r0x, CLK_REG_DISABLE); |
| 243 | write32(&exynos_clock->clkout_cmu_r1x, CLK_REG_DISABLE); |
| 244 | write32(&exynos_clock->clkout_cmu_cdrex, CLK_REG_DISABLE); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 245 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 246 | write32(&exynos_clock->src_peric0, CLK_SRC_PERIC0_VAL); |
| 247 | write32(&exynos_clock->div_peric0, CLK_DIV_PERIC0_VAL); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 248 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 249 | write32(&exynos_clock->src_peric1, CLK_SRC_PERIC1_VAL); |
| 250 | write32(&exynos_clock->div_peric1, CLK_DIV_PERIC1_VAL); |
| 251 | write32(&exynos_clock->div_peric2, CLK_DIV_PERIC2_VAL); |
| 252 | write32(&exynos_clock->sclk_src_isp, SCLK_SRC_ISP_VAL); |
| 253 | write32(&exynos_clock->sclk_div_isp, SCLK_DIV_ISP_VAL); |
| 254 | write32(&exynos_clock->div_isp0, CLK_DIV_ISP0_VAL); |
| 255 | write32(&exynos_clock->div_isp1, CLK_DIV_ISP1_VAL); |
| 256 | write32(&exynos_clock->div_isp2, CLK_DIV_ISP2_VAL); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 257 | |
| 258 | /* FIMD1 SRC CLK SELECTION */ |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 259 | write32(&exynos_clock->src_disp1_0, CLK_SRC_DISP1_0_VAL); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 260 | |
| 261 | val = MMC2_PRE_RATIO_VAL << MMC2_PRE_RATIO_OFFSET |
| 262 | | MMC2_RATIO_VAL << MMC2_RATIO_OFFSET |
| 263 | | MMC3_PRE_RATIO_VAL << MMC3_PRE_RATIO_OFFSET |
| 264 | | MMC3_RATIO_VAL << MMC3_RATIO_OFFSET; |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 265 | write32(&exynos_clock->div_fsys2, val); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 266 | } |
| 267 | |
| 268 | void clock_gate(void) |
| 269 | { |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 270 | /* CLK_GATE_IP_SYSRGT */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 271 | clrbits32(&exynos_clock->gate_ip_sysrgt, CLK_C2C_MASK); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 272 | |
| 273 | /* CLK_GATE_IP_ACP */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 274 | clrbits32(&exynos_clock->gate_ip_acp, CLK_SMMUG2D_MASK | |
| 275 | CLK_SMMUSSS_MASK | |
| 276 | CLK_SMMUMDMA_MASK | |
| 277 | CLK_ID_REMAPPER_MASK | |
| 278 | CLK_G2D_MASK | |
| 279 | CLK_SSS_MASK | |
| 280 | CLK_MDMA_MASK | |
| 281 | CLK_SECJTAG_MASK); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 282 | |
| 283 | /* CLK_GATE_BUS_SYSLFT */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 284 | clrbits32(&exynos_clock->gate_bus_syslft, CLK_EFCLK_MASK); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 285 | |
| 286 | /* CLK_GATE_IP_ISP0 */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 287 | clrbits32(&exynos_clock->gate_ip_isp0, CLK_UART_ISP_MASK | |
| 288 | CLK_WDT_ISP_MASK | |
| 289 | CLK_PWM_ISP_MASK | |
| 290 | CLK_MTCADC_ISP_MASK | |
| 291 | CLK_I2C1_ISP_MASK | |
| 292 | CLK_I2C0_ISP_MASK | |
| 293 | CLK_MPWM_ISP_MASK | |
| 294 | CLK_MCUCTL_ISP_MASK | |
| 295 | CLK_INT_COMB_ISP_MASK | |
| 296 | CLK_SMMU_MCUISP_MASK | |
| 297 | CLK_SMMU_SCALERP_MASK | |
| 298 | CLK_SMMU_SCALERC_MASK | |
| 299 | CLK_SMMU_FD_MASK | |
| 300 | CLK_SMMU_DRC_MASK | |
| 301 | CLK_SMMU_ISP_MASK | |
| 302 | CLK_GICISP_MASK | |
| 303 | CLK_ARM9S_MASK | |
| 304 | CLK_MCUISP_MASK | |
| 305 | CLK_SCALERP_MASK | |
| 306 | CLK_SCALERC_MASK | |
| 307 | CLK_FD_MASK | |
| 308 | CLK_DRC_MASK | |
| 309 | CLK_ISP_MASK); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 310 | |
| 311 | /* CLK_GATE_IP_ISP1 */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 312 | clrbits32(&exynos_clock->gate_ip_isp1, CLK_SPI1_ISP_MASK | |
| 313 | CLK_SPI0_ISP_MASK | |
| 314 | CLK_SMMU3DNR_MASK | |
| 315 | CLK_SMMUDIS1_MASK | |
| 316 | CLK_SMMUDIS0_MASK | |
| 317 | CLK_SMMUODC_MASK | |
| 318 | CLK_3DNR_MASK | |
| 319 | CLK_DIS_MASK | |
| 320 | CLK_ODC_MASK); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 321 | |
| 322 | /* CLK_GATE_SCLK_ISP */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 323 | clrbits32(&exynos_clock->gate_sclk_isp, SCLK_MPWM_ISP_MASK); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 324 | |
| 325 | /* CLK_GATE_IP_GSCL */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 326 | clrbits32(&exynos_clock->gate_ip_gscl, CLK_SMMUFIMC_LITE2_MASK | |
| 327 | CLK_SMMUFIMC_LITE1_MASK | |
| 328 | CLK_SMMUFIMC_LITE0_MASK | |
| 329 | CLK_SMMUGSCL3_MASK | |
| 330 | CLK_SMMUGSCL2_MASK | |
| 331 | CLK_SMMUGSCL1_MASK | |
| 332 | CLK_SMMUGSCL0_MASK | |
| 333 | CLK_GSCL_WRAP_B_MASK | |
| 334 | CLK_GSCL_WRAP_A_MASK | |
| 335 | CLK_CAMIF_TOP_MASK | |
| 336 | CLK_GSCL3_MASK | |
| 337 | CLK_GSCL2_MASK | |
| 338 | CLK_GSCL1_MASK | |
| 339 | CLK_GSCL0_MASK); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 340 | |
| 341 | /* CLK_GATE_IP_DISP1 */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 342 | clrbits32(&exynos_clock->gate_ip_disp1, CLK_SMMUTVX_MASK | |
| 343 | CLK_ASYNCTVX_MASK | |
| 344 | CLK_HDMI_MASK | |
| 345 | CLK_MIXER_MASK | |
| 346 | CLK_DSIM1_MASK); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 347 | |
| 348 | /* CLK_GATE_IP_MFC */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 349 | clrbits32(&exynos_clock->gate_ip_mfc, CLK_SMMUMFCR_MASK | |
| 350 | CLK_SMMUMFCL_MASK | |
| 351 | CLK_MFC_MASK); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 352 | |
| 353 | /* CLK_GATE_IP_GEN */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 354 | clrbits32(&exynos_clock->gate_ip_gen, CLK_SMMUMDMA1_MASK | |
| 355 | CLK_SMMUJPEG_MASK | |
| 356 | CLK_SMMUROTATOR_MASK | |
| 357 | CLK_MDMA1_MASK | |
| 358 | CLK_JPEG_MASK | |
| 359 | CLK_ROTATOR_MASK); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 360 | |
| 361 | /* CLK_GATE_IP_FSYS */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 362 | clrbits32(&exynos_clock->gate_ip_fsys, CLK_WDT_IOP_MASK | |
| 363 | CLK_SMMUMCU_IOP_MASK | |
| 364 | CLK_SATA_PHY_I2C_MASK | |
| 365 | CLK_SATA_PHY_CTRL_MASK | |
| 366 | CLK_MCUCTL_MASK | |
| 367 | CLK_NFCON_MASK | |
| 368 | CLK_SMMURTIC_MASK | |
| 369 | CLK_RTIC_MASK | |
| 370 | CLK_MIPI_HSI_MASK | |
| 371 | CLK_USBOTG_MASK | |
| 372 | CLK_SATA_MASK | |
| 373 | CLK_PDMA1_MASK | |
| 374 | CLK_PDMA0_MASK | |
| 375 | CLK_MCU_IOP_MASK); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 376 | |
| 377 | /* CLK_GATE_IP_PERIC */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 378 | clrbits32(&exynos_clock->gate_ip_peric, CLK_HS_I2C3_MASK | |
| 379 | CLK_HS_I2C2_MASK | |
| 380 | CLK_HS_I2C1_MASK | |
| 381 | CLK_HS_I2C0_MASK | |
| 382 | CLK_AC97_MASK | |
| 383 | CLK_SPDIF_MASK | |
| 384 | CLK_PCM2_MASK | |
| 385 | CLK_PCM1_MASK | |
| 386 | CLK_I2S2_MASK | |
| 387 | CLK_SPI2_MASK | |
| 388 | CLK_SPI0_MASK); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 389 | |
David Hendricks | aee444f | 2013-04-22 16:03:11 -0700 | [diff] [blame] | 390 | /* |
| 391 | * CLK_GATE_IP_PERIS |
| 392 | * Note: Keep CHIPID_APBIF ungated to ensure reading the product ID |
| 393 | * register (PRO_ID) works correctly when the OS kernel determines |
| 394 | * which chip it is running on. |
| 395 | */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 396 | clrbits32(&exynos_clock->gate_ip_peris, CLK_RTC_MASK | |
| 397 | CLK_TZPC9_MASK | |
| 398 | CLK_TZPC8_MASK | |
| 399 | CLK_TZPC7_MASK | |
| 400 | CLK_TZPC6_MASK | |
| 401 | CLK_TZPC5_MASK | |
| 402 | CLK_TZPC4_MASK | |
| 403 | CLK_TZPC3_MASK | |
| 404 | CLK_TZPC2_MASK | |
| 405 | CLK_TZPC1_MASK | |
| 406 | CLK_TZPC0_MASK); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 407 | |
| 408 | /* CLK_GATE_BLOCK */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 409 | clrbits32(&exynos_clock->gate_block, CLK_ACP_MASK); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 410 | |
| 411 | /* CLK_GATE_IP_CDREX */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 412 | clrbits32(&exynos_clock->gate_ip_cdrex, CLK_DPHY0_MASK | |
| 413 | CLK_DPHY1_MASK | |
| 414 | CLK_TZASC_DRBXR_MASK); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 415 | |
| 416 | } |
| 417 | |
| 418 | void clock_init_dp_clock(void) |
| 419 | { |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 420 | /* DP clock enable */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 421 | setbits32(&exynos_clock->gate_ip_disp1, CLK_GATE_DP1_ALLOW); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 422 | |
| 423 | /* We run DP at 267 Mhz */ |
Julius Werner | 55009af | 2019-12-02 22:03:27 -0800 | [diff] [blame] | 424 | setbits32(&exynos_clock->div_disp1_0, CLK_DIV_DISP1_0_FIMD1); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 425 | } |