Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 1 | /* |
Stefan Reinauer | 08dc357 | 2013-05-14 16:57:50 -0700 | [diff] [blame] | 2 | * This file is part of the coreboot project. |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 3 | * |
| 4 | * Copyright (C) 2012 Samsung Electronics |
| 5 | * |
Stefan Reinauer | 08dc357 | 2013-05-14 16:57:50 -0700 | [diff] [blame] | 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 14 | */ |
| 15 | |
Stefan Reinauer | 08dc357 | 2013-05-14 16:57:50 -0700 | [diff] [blame] | 16 | /* Clock setup for SMDK5250 board based on EXYNOS5 */ |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 17 | |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame^] | 18 | #include <device/mmio.h> |
Stefan Reinauer | 08dc357 | 2013-05-14 16:57:50 -0700 | [diff] [blame] | 19 | #include <delay.h> |
Julius Werner | 1ed0c8c | 2014-10-20 13:16:29 -0700 | [diff] [blame] | 20 | #include <soc/clk.h> |
| 21 | #include <soc/dp.h> |
| 22 | #include <soc/setup.h> |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 23 | |
David Hendricks | 0d4f97e | 2013-02-03 18:09:58 -0800 | [diff] [blame] | 24 | void system_clock_init(struct mem_timings *mem, |
| 25 | struct arm_clk_ratios *arm_clk_ratio) |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 26 | { |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 27 | u32 val, tmp; |
| 28 | |
| 29 | /* Turn on the MCT as early as possible. */ |
Julius Werner | fa938c7 | 2013-08-29 14:17:36 -0700 | [diff] [blame] | 30 | exynos_mct->g_tcon |= (1 << 8); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 31 | |
Julius Werner | fa938c7 | 2013-08-29 14:17:36 -0700 | [diff] [blame] | 32 | clrbits_le32(&exynos_clock->src_cpu, MUX_APLL_SEL_MASK); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 33 | do { |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 34 | val = read32(&exynos_clock->mux_stat_cpu); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 35 | } while ((val | MUX_APLL_SEL_MASK) != val); |
| 36 | |
Julius Werner | fa938c7 | 2013-08-29 14:17:36 -0700 | [diff] [blame] | 37 | clrbits_le32(&exynos_clock->src_core1, MUX_MPLL_SEL_MASK); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 38 | do { |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 39 | val = read32(&exynos_clock->mux_stat_core1); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 40 | } while ((val | MUX_MPLL_SEL_MASK) != val); |
| 41 | |
Julius Werner | fa938c7 | 2013-08-29 14:17:36 -0700 | [diff] [blame] | 42 | clrbits_le32(&exynos_clock->src_top2, MUX_CPLL_SEL_MASK); |
| 43 | clrbits_le32(&exynos_clock->src_top2, MUX_EPLL_SEL_MASK); |
| 44 | clrbits_le32(&exynos_clock->src_top2, MUX_VPLL_SEL_MASK); |
| 45 | clrbits_le32(&exynos_clock->src_top2, MUX_GPLL_SEL_MASK); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 46 | tmp = MUX_CPLL_SEL_MASK | MUX_EPLL_SEL_MASK | MUX_VPLL_SEL_MASK |
| 47 | | MUX_GPLL_SEL_MASK; |
| 48 | do { |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 49 | val = read32(&exynos_clock->mux_stat_top2); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 50 | } while ((val | tmp) != val); |
| 51 | |
Julius Werner | fa938c7 | 2013-08-29 14:17:36 -0700 | [diff] [blame] | 52 | clrbits_le32(&exynos_clock->src_cdrex, MUX_BPLL_SEL_MASK); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 53 | do { |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 54 | val = read32(&exynos_clock->mux_stat_cdrex); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 55 | } while ((val | MUX_BPLL_SEL_MASK) != val); |
| 56 | |
| 57 | /* PLL locktime */ |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 58 | write32(&exynos_clock->apll_lock, APLL_LOCK_VAL); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 59 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 60 | write32(&exynos_clock->mpll_lock, MPLL_LOCK_VAL); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 61 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 62 | write32(&exynos_clock->bpll_lock, BPLL_LOCK_VAL); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 63 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 64 | write32(&exynos_clock->cpll_lock, CPLL_LOCK_VAL); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 65 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 66 | write32(&exynos_clock->gpll_lock, GPLL_LOCK_VAL); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 67 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 68 | write32(&exynos_clock->epll_lock, EPLL_LOCK_VAL); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 69 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 70 | write32(&exynos_clock->vpll_lock, VPLL_LOCK_VAL); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 71 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 72 | write32(&exynos_clock->pll_div2_sel, CLK_REG_DISABLE); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 73 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 74 | write32(&exynos_clock->src_cpu, MUX_HPM_SEL_MASK); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 75 | do { |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 76 | val = read32(&exynos_clock->mux_stat_cpu); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 77 | } while ((val | HPM_SEL_SCLK_MPLL) != val); |
| 78 | |
| 79 | val = arm_clk_ratio->arm2_ratio << 28 |
| 80 | | arm_clk_ratio->apll_ratio << 24 |
| 81 | | arm_clk_ratio->pclk_dbg_ratio << 20 |
| 82 | | arm_clk_ratio->atb_ratio << 16 |
| 83 | | arm_clk_ratio->periph_ratio << 12 |
| 84 | | arm_clk_ratio->acp_ratio << 8 |
| 85 | | arm_clk_ratio->cpud_ratio << 4 |
| 86 | | arm_clk_ratio->arm_ratio; |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 87 | write32(&exynos_clock->div_cpu0, val); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 88 | do { |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 89 | val = read32(&exynos_clock->div_stat_cpu0); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 90 | } while (0 != val); |
| 91 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 92 | write32(&exynos_clock->div_cpu1, CLK_DIV_CPU1_VAL); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 93 | do { |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 94 | val = read32(&exynos_clock->div_stat_cpu1); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 95 | } while (0 != val); |
| 96 | |
David Hendricks | f05e871 | 2013-08-06 15:17:37 -0700 | [diff] [blame] | 97 | /* switch A15 clock source to OSC clock before changing APLL */ |
Julius Werner | fa938c7 | 2013-08-29 14:17:36 -0700 | [diff] [blame] | 98 | clrbits_le32(&exynos_clock->src_cpu, APLL_FOUT); |
David Hendricks | f05e871 | 2013-08-06 15:17:37 -0700 | [diff] [blame] | 99 | |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 100 | /* Set APLL */ |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 101 | write32(&exynos_clock->apll_con1, APLL_CON1_VAL); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 102 | val = set_pll(arm_clk_ratio->apll_mdiv, arm_clk_ratio->apll_pdiv, |
| 103 | arm_clk_ratio->apll_sdiv); |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 104 | write32(&exynos_clock->apll_con0, val); |
| 105 | while ((read32(&exynos_clock->apll_con0) & APLL_CON0_LOCKED) == 0) |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 106 | ; |
| 107 | |
David Hendricks | f05e871 | 2013-08-06 15:17:37 -0700 | [diff] [blame] | 108 | /* now it is safe to switch to APLL */ |
Julius Werner | fa938c7 | 2013-08-29 14:17:36 -0700 | [diff] [blame] | 109 | setbits_le32(&exynos_clock->src_cpu, APLL_FOUT); |
David Hendricks | f05e871 | 2013-08-06 15:17:37 -0700 | [diff] [blame] | 110 | |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 111 | /* Set MPLL */ |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 112 | write32(&exynos_clock->mpll_con1, MPLL_CON1_VAL); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 113 | val = set_pll(mem->mpll_mdiv, mem->mpll_pdiv, mem->mpll_sdiv); |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 114 | write32(&exynos_clock->mpll_con0, val); |
| 115 | while ((read32(&exynos_clock->mpll_con0) & MPLL_CON0_LOCKED) == 0) |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 116 | ; |
| 117 | |
| 118 | /* |
| 119 | * Configure MUX_MPLL_FOUT to choose the direct clock source |
| 120 | * path and avoid the fixed DIV/2 block to save power |
| 121 | */ |
Julius Werner | fa938c7 | 2013-08-29 14:17:36 -0700 | [diff] [blame] | 122 | setbits_le32(&exynos_clock->pll_div2_sel, MUX_MPLL_FOUT_SEL); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 123 | |
| 124 | /* Set BPLL */ |
| 125 | if (mem->use_bpll) { |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 126 | write32(&exynos_clock->bpll_con1, BPLL_CON1_VAL); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 127 | val = set_pll(mem->bpll_mdiv, mem->bpll_pdiv, mem->bpll_sdiv); |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 128 | write32(&exynos_clock->bpll_con0, val); |
| 129 | while ((read32(&exynos_clock->bpll_con0) & BPLL_CON0_LOCKED) == 0) |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 130 | ; |
| 131 | |
Julius Werner | fa938c7 | 2013-08-29 14:17:36 -0700 | [diff] [blame] | 132 | setbits_le32(&exynos_clock->pll_div2_sel, MUX_BPLL_FOUT_SEL); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 133 | } |
| 134 | |
| 135 | /* Set CPLL */ |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 136 | write32(&exynos_clock->cpll_con1, CPLL_CON1_VAL); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 137 | val = set_pll(mem->cpll_mdiv, mem->cpll_pdiv, mem->cpll_sdiv); |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 138 | write32(&exynos_clock->cpll_con0, val); |
| 139 | while ((read32(&exynos_clock->cpll_con0) & CPLL_CON0_LOCKED) == 0) |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 140 | ; |
| 141 | |
| 142 | /* Set GPLL */ |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 143 | write32(&exynos_clock->gpll_con1, GPLL_CON1_VAL); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 144 | val = set_pll(mem->gpll_mdiv, mem->gpll_pdiv, mem->gpll_sdiv); |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 145 | write32(&exynos_clock->gpll_con0, val); |
| 146 | while ((read32(&exynos_clock->gpll_con0) & GPLL_CON0_LOCKED) == 0) |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 147 | ; |
| 148 | |
| 149 | /* Set EPLL */ |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 150 | write32(&exynos_clock->epll_con2, EPLL_CON2_VAL); |
| 151 | write32(&exynos_clock->epll_con1, EPLL_CON1_VAL); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 152 | val = set_pll(mem->epll_mdiv, mem->epll_pdiv, mem->epll_sdiv); |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 153 | write32(&exynos_clock->epll_con0, val); |
| 154 | while ((read32(&exynos_clock->epll_con0) & EPLL_CON0_LOCKED) == 0) |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 155 | ; |
| 156 | |
| 157 | /* Set VPLL */ |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 158 | write32(&exynos_clock->vpll_con2, VPLL_CON2_VAL); |
| 159 | write32(&exynos_clock->vpll_con1, VPLL_CON1_VAL); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 160 | val = set_pll(mem->vpll_mdiv, mem->vpll_pdiv, mem->vpll_sdiv); |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 161 | write32(&exynos_clock->vpll_con0, val); |
| 162 | while ((read32(&exynos_clock->vpll_con0) & VPLL_CON0_LOCKED) == 0) |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 163 | ; |
| 164 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 165 | write32(&exynos_clock->src_core0, CLK_SRC_CORE0_VAL); |
| 166 | write32(&exynos_clock->div_core0, CLK_DIV_CORE0_VAL); |
| 167 | while (read32(&exynos_clock->div_stat_core0) != 0) |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 168 | ; |
| 169 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 170 | write32(&exynos_clock->div_core1, CLK_DIV_CORE1_VAL); |
| 171 | while (read32(&exynos_clock->div_stat_core1) != 0) |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 172 | ; |
| 173 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 174 | write32(&exynos_clock->div_sysrgt, CLK_DIV_SYSRGT_VAL); |
| 175 | while (read32(&exynos_clock->div_stat_sysrgt) != 0) |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 176 | ; |
| 177 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 178 | write32(&exynos_clock->div_acp, CLK_DIV_ACP_VAL); |
| 179 | while (read32(&exynos_clock->div_stat_acp) != 0) |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 180 | ; |
| 181 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 182 | write32(&exynos_clock->div_syslft, CLK_DIV_SYSLFT_VAL); |
| 183 | while (read32(&exynos_clock->div_stat_syslft) != 0) |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 184 | ; |
| 185 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 186 | write32(&exynos_clock->src_top0, CLK_SRC_TOP0_VAL); |
| 187 | write32(&exynos_clock->src_top1, CLK_SRC_TOP1_VAL); |
| 188 | write32(&exynos_clock->src_top2, TOP2_VAL); |
| 189 | write32(&exynos_clock->src_top3, CLK_SRC_TOP3_VAL); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 190 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 191 | write32(&exynos_clock->div_top0, CLK_DIV_TOP0_VAL); |
| 192 | while (read32(&exynos_clock->div_stat_top0)) |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 193 | ; |
| 194 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 195 | write32(&exynos_clock->div_top1, CLK_DIV_TOP1_VAL); |
| 196 | while (read32(&exynos_clock->div_stat_top1)) |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 197 | ; |
| 198 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 199 | write32(&exynos_clock->src_lex, CLK_SRC_LEX_VAL); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 200 | while (1) { |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 201 | val = read32(&exynos_clock->mux_stat_lex); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 202 | if (val == (val | 1)) |
| 203 | break; |
| 204 | } |
| 205 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 206 | write32(&exynos_clock->div_lex, CLK_DIV_LEX_VAL); |
| 207 | while (read32(&exynos_clock->div_stat_lex)) |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 208 | ; |
| 209 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 210 | write32(&exynos_clock->div_r0x, CLK_DIV_R0X_VAL); |
| 211 | while (read32(&exynos_clock->div_stat_r0x)) |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 212 | ; |
| 213 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 214 | write32(&exynos_clock->div_r0x, CLK_DIV_R0X_VAL); |
| 215 | while (read32(&exynos_clock->div_stat_r0x)) |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 216 | ; |
| 217 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 218 | write32(&exynos_clock->div_r1x, CLK_DIV_R1X_VAL); |
| 219 | while (read32(&exynos_clock->div_stat_r1x)) |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 220 | ; |
| 221 | |
| 222 | if (mem->use_bpll) { |
Julius Werner | 9418476 | 2015-02-19 20:19:23 -0800 | [diff] [blame] | 223 | write32(&exynos_clock->src_cdrex, MUX_BPLL_SEL_MASK | |
| 224 | MUX_MCLK_CDREX_SEL | MUX_MCLK_DPHY_SEL); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 225 | } else { |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 226 | write32(&exynos_clock->src_cdrex, CLK_REG_DISABLE); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 227 | } |
| 228 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 229 | write32(&exynos_clock->div_cdrex, CLK_DIV_CDREX_VAL); |
| 230 | while (read32(&exynos_clock->div_stat_cdrex)) |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 231 | ; |
| 232 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 233 | val = read32(&exynos_clock->src_cpu); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 234 | val |= CLK_SRC_CPU_VAL; |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 235 | write32(&exynos_clock->src_cpu, val); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 236 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 237 | val = read32(&exynos_clock->src_top2); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 238 | val |= CLK_SRC_TOP2_VAL; |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 239 | write32(&exynos_clock->src_top2, val); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 240 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 241 | val = read32(&exynos_clock->src_core1); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 242 | val |= CLK_SRC_CORE1_VAL; |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 243 | write32(&exynos_clock->src_core1, val); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 244 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 245 | write32(&exynos_clock->src_fsys, CLK_SRC_FSYS0_VAL); |
| 246 | write32(&exynos_clock->div_fsys0, CLK_DIV_FSYS0_VAL); |
| 247 | while (read32(&exynos_clock->div_stat_fsys0)) |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 248 | ; |
| 249 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 250 | write32(&exynos_clock->clkout_cmu_cpu, CLK_REG_DISABLE); |
| 251 | write32(&exynos_clock->clkout_cmu_core, CLK_REG_DISABLE); |
| 252 | write32(&exynos_clock->clkout_cmu_acp, CLK_REG_DISABLE); |
| 253 | write32(&exynos_clock->clkout_cmu_top, CLK_REG_DISABLE); |
| 254 | write32(&exynos_clock->clkout_cmu_lex, CLK_REG_DISABLE); |
| 255 | write32(&exynos_clock->clkout_cmu_r0x, CLK_REG_DISABLE); |
| 256 | write32(&exynos_clock->clkout_cmu_r1x, CLK_REG_DISABLE); |
| 257 | write32(&exynos_clock->clkout_cmu_cdrex, CLK_REG_DISABLE); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 258 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 259 | write32(&exynos_clock->src_peric0, CLK_SRC_PERIC0_VAL); |
| 260 | write32(&exynos_clock->div_peric0, CLK_DIV_PERIC0_VAL); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 261 | |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 262 | write32(&exynos_clock->src_peric1, CLK_SRC_PERIC1_VAL); |
| 263 | write32(&exynos_clock->div_peric1, CLK_DIV_PERIC1_VAL); |
| 264 | write32(&exynos_clock->div_peric2, CLK_DIV_PERIC2_VAL); |
| 265 | write32(&exynos_clock->sclk_src_isp, SCLK_SRC_ISP_VAL); |
| 266 | write32(&exynos_clock->sclk_div_isp, SCLK_DIV_ISP_VAL); |
| 267 | write32(&exynos_clock->div_isp0, CLK_DIV_ISP0_VAL); |
| 268 | write32(&exynos_clock->div_isp1, CLK_DIV_ISP1_VAL); |
| 269 | write32(&exynos_clock->div_isp2, CLK_DIV_ISP2_VAL); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 270 | |
| 271 | /* FIMD1 SRC CLK SELECTION */ |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 272 | write32(&exynos_clock->src_disp1_0, CLK_SRC_DISP1_0_VAL); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 273 | |
| 274 | val = MMC2_PRE_RATIO_VAL << MMC2_PRE_RATIO_OFFSET |
| 275 | | MMC2_RATIO_VAL << MMC2_RATIO_OFFSET |
| 276 | | MMC3_PRE_RATIO_VAL << MMC3_PRE_RATIO_OFFSET |
| 277 | | MMC3_RATIO_VAL << MMC3_RATIO_OFFSET; |
Julius Werner | 2f37bd6 | 2015-02-19 14:51:15 -0800 | [diff] [blame] | 278 | write32(&exynos_clock->div_fsys2, val); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 279 | } |
| 280 | |
| 281 | void clock_gate(void) |
| 282 | { |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 283 | /* CLK_GATE_IP_SYSRGT */ |
Julius Werner | fa938c7 | 2013-08-29 14:17:36 -0700 | [diff] [blame] | 284 | clrbits_le32(&exynos_clock->gate_ip_sysrgt, CLK_C2C_MASK); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 285 | |
| 286 | /* CLK_GATE_IP_ACP */ |
Julius Werner | fa938c7 | 2013-08-29 14:17:36 -0700 | [diff] [blame] | 287 | clrbits_le32(&exynos_clock->gate_ip_acp, CLK_SMMUG2D_MASK | |
| 288 | CLK_SMMUSSS_MASK | |
| 289 | CLK_SMMUMDMA_MASK | |
| 290 | CLK_ID_REMAPPER_MASK | |
| 291 | CLK_G2D_MASK | |
| 292 | CLK_SSS_MASK | |
| 293 | CLK_MDMA_MASK | |
| 294 | CLK_SECJTAG_MASK); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 295 | |
| 296 | /* CLK_GATE_BUS_SYSLFT */ |
Julius Werner | fa938c7 | 2013-08-29 14:17:36 -0700 | [diff] [blame] | 297 | clrbits_le32(&exynos_clock->gate_bus_syslft, CLK_EFCLK_MASK); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 298 | |
| 299 | /* CLK_GATE_IP_ISP0 */ |
Julius Werner | fa938c7 | 2013-08-29 14:17:36 -0700 | [diff] [blame] | 300 | clrbits_le32(&exynos_clock->gate_ip_isp0, CLK_UART_ISP_MASK | |
| 301 | CLK_WDT_ISP_MASK | |
| 302 | CLK_PWM_ISP_MASK | |
| 303 | CLK_MTCADC_ISP_MASK | |
| 304 | CLK_I2C1_ISP_MASK | |
| 305 | CLK_I2C0_ISP_MASK | |
| 306 | CLK_MPWM_ISP_MASK | |
| 307 | CLK_MCUCTL_ISP_MASK | |
| 308 | CLK_INT_COMB_ISP_MASK | |
| 309 | CLK_SMMU_MCUISP_MASK | |
| 310 | CLK_SMMU_SCALERP_MASK | |
| 311 | CLK_SMMU_SCALERC_MASK | |
| 312 | CLK_SMMU_FD_MASK | |
| 313 | CLK_SMMU_DRC_MASK | |
| 314 | CLK_SMMU_ISP_MASK | |
| 315 | CLK_GICISP_MASK | |
| 316 | CLK_ARM9S_MASK | |
| 317 | CLK_MCUISP_MASK | |
| 318 | CLK_SCALERP_MASK | |
| 319 | CLK_SCALERC_MASK | |
| 320 | CLK_FD_MASK | |
| 321 | CLK_DRC_MASK | |
| 322 | CLK_ISP_MASK); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 323 | |
| 324 | /* CLK_GATE_IP_ISP1 */ |
Julius Werner | fa938c7 | 2013-08-29 14:17:36 -0700 | [diff] [blame] | 325 | clrbits_le32(&exynos_clock->gate_ip_isp1, CLK_SPI1_ISP_MASK | |
| 326 | CLK_SPI0_ISP_MASK | |
| 327 | CLK_SMMU3DNR_MASK | |
| 328 | CLK_SMMUDIS1_MASK | |
| 329 | CLK_SMMUDIS0_MASK | |
| 330 | CLK_SMMUODC_MASK | |
| 331 | CLK_3DNR_MASK | |
| 332 | CLK_DIS_MASK | |
| 333 | CLK_ODC_MASK); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 334 | |
| 335 | /* CLK_GATE_SCLK_ISP */ |
Julius Werner | fa938c7 | 2013-08-29 14:17:36 -0700 | [diff] [blame] | 336 | clrbits_le32(&exynos_clock->gate_sclk_isp, SCLK_MPWM_ISP_MASK); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 337 | |
| 338 | /* CLK_GATE_IP_GSCL */ |
Julius Werner | fa938c7 | 2013-08-29 14:17:36 -0700 | [diff] [blame] | 339 | clrbits_le32(&exynos_clock->gate_ip_gscl, CLK_SMMUFIMC_LITE2_MASK | |
| 340 | CLK_SMMUFIMC_LITE1_MASK | |
| 341 | CLK_SMMUFIMC_LITE0_MASK | |
| 342 | CLK_SMMUGSCL3_MASK | |
| 343 | CLK_SMMUGSCL2_MASK | |
| 344 | CLK_SMMUGSCL1_MASK | |
| 345 | CLK_SMMUGSCL0_MASK | |
| 346 | CLK_GSCL_WRAP_B_MASK | |
| 347 | CLK_GSCL_WRAP_A_MASK | |
| 348 | CLK_CAMIF_TOP_MASK | |
| 349 | CLK_GSCL3_MASK | |
| 350 | CLK_GSCL2_MASK | |
| 351 | CLK_GSCL1_MASK | |
| 352 | CLK_GSCL0_MASK); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 353 | |
| 354 | /* CLK_GATE_IP_DISP1 */ |
Julius Werner | fa938c7 | 2013-08-29 14:17:36 -0700 | [diff] [blame] | 355 | clrbits_le32(&exynos_clock->gate_ip_disp1, CLK_SMMUTVX_MASK | |
| 356 | CLK_ASYNCTVX_MASK | |
| 357 | CLK_HDMI_MASK | |
| 358 | CLK_MIXER_MASK | |
| 359 | CLK_DSIM1_MASK); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 360 | |
| 361 | /* CLK_GATE_IP_MFC */ |
Julius Werner | fa938c7 | 2013-08-29 14:17:36 -0700 | [diff] [blame] | 362 | clrbits_le32(&exynos_clock->gate_ip_mfc, CLK_SMMUMFCR_MASK | |
| 363 | CLK_SMMUMFCL_MASK | |
| 364 | CLK_MFC_MASK); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 365 | |
| 366 | /* CLK_GATE_IP_GEN */ |
Julius Werner | fa938c7 | 2013-08-29 14:17:36 -0700 | [diff] [blame] | 367 | clrbits_le32(&exynos_clock->gate_ip_gen, CLK_SMMUMDMA1_MASK | |
| 368 | CLK_SMMUJPEG_MASK | |
| 369 | CLK_SMMUROTATOR_MASK | |
| 370 | CLK_MDMA1_MASK | |
| 371 | CLK_JPEG_MASK | |
| 372 | CLK_ROTATOR_MASK); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 373 | |
| 374 | /* CLK_GATE_IP_FSYS */ |
Julius Werner | fa938c7 | 2013-08-29 14:17:36 -0700 | [diff] [blame] | 375 | clrbits_le32(&exynos_clock->gate_ip_fsys, CLK_WDT_IOP_MASK | |
| 376 | CLK_SMMUMCU_IOP_MASK | |
| 377 | CLK_SATA_PHY_I2C_MASK | |
| 378 | CLK_SATA_PHY_CTRL_MASK | |
| 379 | CLK_MCUCTL_MASK | |
| 380 | CLK_NFCON_MASK | |
| 381 | CLK_SMMURTIC_MASK | |
| 382 | CLK_RTIC_MASK | |
| 383 | CLK_MIPI_HSI_MASK | |
| 384 | CLK_USBOTG_MASK | |
| 385 | CLK_SATA_MASK | |
| 386 | CLK_PDMA1_MASK | |
| 387 | CLK_PDMA0_MASK | |
| 388 | CLK_MCU_IOP_MASK); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 389 | |
| 390 | /* CLK_GATE_IP_PERIC */ |
Julius Werner | fa938c7 | 2013-08-29 14:17:36 -0700 | [diff] [blame] | 391 | clrbits_le32(&exynos_clock->gate_ip_peric, CLK_HS_I2C3_MASK | |
| 392 | CLK_HS_I2C2_MASK | |
| 393 | CLK_HS_I2C1_MASK | |
| 394 | CLK_HS_I2C0_MASK | |
| 395 | CLK_AC97_MASK | |
| 396 | CLK_SPDIF_MASK | |
| 397 | CLK_PCM2_MASK | |
| 398 | CLK_PCM1_MASK | |
| 399 | CLK_I2S2_MASK | |
| 400 | CLK_SPI2_MASK | |
| 401 | CLK_SPI0_MASK); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 402 | |
David Hendricks | aee444f | 2013-04-22 16:03:11 -0700 | [diff] [blame] | 403 | /* |
| 404 | * CLK_GATE_IP_PERIS |
| 405 | * Note: Keep CHIPID_APBIF ungated to ensure reading the product ID |
| 406 | * register (PRO_ID) works correctly when the OS kernel determines |
| 407 | * which chip it is running on. |
| 408 | */ |
Julius Werner | fa938c7 | 2013-08-29 14:17:36 -0700 | [diff] [blame] | 409 | clrbits_le32(&exynos_clock->gate_ip_peris, CLK_RTC_MASK | |
| 410 | CLK_TZPC9_MASK | |
| 411 | CLK_TZPC8_MASK | |
| 412 | CLK_TZPC7_MASK | |
| 413 | CLK_TZPC6_MASK | |
| 414 | CLK_TZPC5_MASK | |
| 415 | CLK_TZPC4_MASK | |
| 416 | CLK_TZPC3_MASK | |
| 417 | CLK_TZPC2_MASK | |
| 418 | CLK_TZPC1_MASK | |
| 419 | CLK_TZPC0_MASK); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 420 | |
| 421 | /* CLK_GATE_BLOCK */ |
Julius Werner | fa938c7 | 2013-08-29 14:17:36 -0700 | [diff] [blame] | 422 | clrbits_le32(&exynos_clock->gate_block, CLK_ACP_MASK); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 423 | |
| 424 | /* CLK_GATE_IP_CDREX */ |
Julius Werner | fa938c7 | 2013-08-29 14:17:36 -0700 | [diff] [blame] | 425 | clrbits_le32(&exynos_clock->gate_ip_cdrex, CLK_DPHY0_MASK | |
| 426 | CLK_DPHY1_MASK | |
| 427 | CLK_TZASC_DRBXR_MASK); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 428 | |
| 429 | } |
| 430 | |
| 431 | void clock_init_dp_clock(void) |
| 432 | { |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 433 | /* DP clock enable */ |
Julius Werner | fa938c7 | 2013-08-29 14:17:36 -0700 | [diff] [blame] | 434 | setbits_le32(&exynos_clock->gate_ip_disp1, CLK_GATE_DP1_ALLOW); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 435 | |
| 436 | /* We run DP at 267 Mhz */ |
Julius Werner | fa938c7 | 2013-08-29 14:17:36 -0700 | [diff] [blame] | 437 | setbits_le32(&exynos_clock->div_disp1_0, CLK_DIV_DISP1_0_FIMD1); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 438 | } |