exynos5xxx: use oscillator clock when changing ARM frequency
Switch ARM clock source when changing the APLL frequency to avoid
stability issues.
This is ported from https://gerrit.chromium.org/gerrit/#/c/64189/5
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: I923107555e6d3287b3694cbf9e4bb548d3e5f4a8
Reviewed-on: https://gerrit.chromium.org/gerrit/64838
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/4442
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
diff --git a/src/cpu/samsung/exynos5250/clock_init.c b/src/cpu/samsung/exynos5250/clock_init.c
index 2cfdaf4..bfcf844 100644
--- a/src/cpu/samsung/exynos5250/clock_init.c
+++ b/src/cpu/samsung/exynos5250/clock_init.c
@@ -102,6 +102,9 @@
val = readl(&clk->div_stat_cpu1);
} while (0 != val);
+ /* switch A15 clock source to OSC clock before changing APLL */
+ clrbits_le32(&clk->src_cpu, APLL_FOUT);
+
/* Set APLL */
writel(APLL_CON1_VAL, &clk->apll_con1);
val = set_pll(arm_clk_ratio->apll_mdiv, arm_clk_ratio->apll_pdiv,
@@ -110,6 +113,9 @@
while ((readl(&clk->apll_con0) & APLL_CON0_LOCKED) == 0)
;
+ /* now it is safe to switch to APLL */
+ setbits_le32(&clk->src_cpu, APLL_FOUT);
+
/* Set MPLL */
writel(MPLL_CON1_VAL, &clk->mpll_con1);
val = set_pll(mem->mpll_mdiv, mem->mpll_pdiv, mem->mpll_sdiv);