Duncan Laurie | 2d9d39a | 2013-05-29 15:27:55 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2013 Google Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; version 2 of |
| 9 | * the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Duncan Laurie | 2d9d39a | 2013-05-29 15:27:55 -0700 | [diff] [blame] | 15 | */ |
| 16 | |
Duncan Laurie | 1f52908 | 2013-07-30 15:53:45 -0700 | [diff] [blame] | 17 | #include <delay.h> |
Duncan Laurie | 2d9d39a | 2013-05-29 15:27:55 -0700 | [diff] [blame] | 18 | #include <device/device.h> |
| 19 | #include <device/pci.h> |
| 20 | #include <device/pci_ids.h> |
| 21 | #include <arch/io.h> |
| 22 | #include "pch.h" |
| 23 | |
Stefan Reinauer | 6dbbe2e | 2013-10-17 17:00:26 -0700 | [diff] [blame] | 24 | typedef struct southbridge_intel_lynxpoint_config config_t; |
| 25 | |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 26 | static u8 *usb_xhci_mem_base(device_t dev) |
Duncan Laurie | 1f52908 | 2013-07-30 15:53:45 -0700 | [diff] [blame] | 27 | { |
| 28 | u32 mem_base = pci_read_config32(dev, PCI_BASE_ADDRESS_0); |
| 29 | |
| 30 | /* Check if the controller is disabled or not present */ |
| 31 | if (mem_base == 0 || mem_base == 0xffffffff) |
| 32 | return 0; |
| 33 | |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 34 | return (u8 *)(mem_base & ~0xf); |
Duncan Laurie | 1f52908 | 2013-07-30 15:53:45 -0700 | [diff] [blame] | 35 | } |
| 36 | |
Duncan Laurie | 1f52908 | 2013-07-30 15:53:45 -0700 | [diff] [blame] | 37 | static int usb_xhci_port_count_usb3(device_t dev) |
| 38 | { |
| 39 | if (pch_is_lp()) { |
| 40 | /* LynxPoint-LP has 4 SS ports */ |
| 41 | return 4; |
Duncan Laurie | 1f52908 | 2013-07-30 15:53:45 -0700 | [diff] [blame] | 42 | } |
Elyes HAOUAS | 54f9424 | 2018-10-25 10:57:39 +0200 | [diff] [blame] | 43 | /* LynxPoint-H can have 0, 2, 4, or 6 SS ports */ |
| 44 | u8 *mem_base = usb_xhci_mem_base(dev); |
| 45 | u32 fus = read32(mem_base + XHCI_USB3FUS); |
| 46 | fus >>= XHCI_USB3FUS_SS_SHIFT; |
| 47 | fus &= XHCI_USB3FUS_SS_MASK; |
| 48 | switch (fus) { |
| 49 | case 3: return 0; |
| 50 | case 2: return 2; |
| 51 | case 1: return 4; |
| 52 | case 0: |
| 53 | default: return 6; |
| 54 | } |
Duncan Laurie | 1f52908 | 2013-07-30 15:53:45 -0700 | [diff] [blame] | 55 | } |
| 56 | |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 57 | static void usb_xhci_reset_status_usb3(u8 *mem_base, int port) |
Duncan Laurie | 1f52908 | 2013-07-30 15:53:45 -0700 | [diff] [blame] | 58 | { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 59 | u8 *portsc = mem_base + XHCI_USB3_PORTSC(port); |
Duncan Laurie | 0bf1dea | 2013-08-13 13:32:28 -0700 | [diff] [blame] | 60 | u32 status = read32(portsc); |
| 61 | /* Do not set Port Enabled/Disabled field */ |
| 62 | status &= ~XHCI_USB3_PORTSC_PED; |
| 63 | /* Clear all change status bits */ |
| 64 | status |= XHCI_USB3_PORTSC_CHST; |
| 65 | write32(portsc, status); |
Duncan Laurie | 1f52908 | 2013-07-30 15:53:45 -0700 | [diff] [blame] | 66 | } |
| 67 | |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 68 | static void usb_xhci_reset_port_usb3(u8 *mem_base, int port) |
Duncan Laurie | 1f52908 | 2013-07-30 15:53:45 -0700 | [diff] [blame] | 69 | { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 70 | u8 *portsc = mem_base + XHCI_USB3_PORTSC(port); |
Duncan Laurie | 1f52908 | 2013-07-30 15:53:45 -0700 | [diff] [blame] | 71 | write32(portsc, read32(portsc) | XHCI_USB3_PORTSC_WPR); |
| 72 | } |
| 73 | |
| 74 | #define XHCI_RESET_DELAY_US 1000 /* 1ms */ |
| 75 | #define XHCI_RESET_TIMEOUT 100 /* 100ms */ |
| 76 | |
| 77 | /* |
| 78 | * 1) Wait until port is done polling |
| 79 | * 2) If port is disconnected |
| 80 | * a) Issue warm port reset |
| 81 | * b) Poll for warm reset complete |
| 82 | * c) Write 1 to port change status bits |
| 83 | */ |
Duncan Laurie | 16a0f5c | 2013-09-25 14:08:16 -0700 | [diff] [blame] | 84 | static void usb_xhci_reset_usb3(device_t dev, int all) |
Duncan Laurie | 1f52908 | 2013-07-30 15:53:45 -0700 | [diff] [blame] | 85 | { |
| 86 | u32 status, port_disabled; |
| 87 | int timeout, port; |
| 88 | int port_count = usb_xhci_port_count_usb3(dev); |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 89 | u8 *mem_base = usb_xhci_mem_base(dev); |
Duncan Laurie | 1f52908 | 2013-07-30 15:53:45 -0700 | [diff] [blame] | 90 | |
| 91 | if (!mem_base || !port_count) |
| 92 | return; |
| 93 | |
| 94 | /* Get mask of disabled ports */ |
| 95 | port_disabled = pci_read_config32(dev, XHCI_USB3PDO); |
| 96 | |
| 97 | /* Wait until all enabled ports are done polling */ |
| 98 | for (timeout = XHCI_RESET_TIMEOUT; timeout; timeout--) { |
| 99 | int complete = 1; |
| 100 | for (port = 0; port < port_count; port++) { |
| 101 | /* Skip disabled ports */ |
| 102 | if (port_disabled & (1 << port)) |
| 103 | continue; |
| 104 | /* Read port link status field */ |
| 105 | status = read32(mem_base + XHCI_USB3_PORTSC(port)); |
| 106 | status &= XHCI_USB3_PORTSC_PLS; |
| 107 | if (status == XHCI_PLSR_POLLING) |
| 108 | complete = 0; |
| 109 | } |
| 110 | /* Exit if all ports not polling */ |
| 111 | if (complete) |
| 112 | break; |
| 113 | udelay(XHCI_RESET_DELAY_US); |
| 114 | } |
| 115 | |
| 116 | /* Reset all requested ports */ |
| 117 | for (port = 0; port < port_count; port++) { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 118 | u8 *portsc = mem_base + XHCI_USB3_PORTSC(port); |
Duncan Laurie | 1f52908 | 2013-07-30 15:53:45 -0700 | [diff] [blame] | 119 | /* Skip disabled ports */ |
| 120 | if (port_disabled & (1 << port)) |
| 121 | continue; |
| 122 | status = read32(portsc) & XHCI_USB3_PORTSC_PLS; |
| 123 | /* Reset all or only disconnected ports */ |
Duncan Laurie | 32d2e2b | 2013-09-25 14:08:32 -0700 | [diff] [blame] | 124 | if (all || (status == XHCI_PLSR_RXDETECT || |
| 125 | status == XHCI_PLSR_POLLING)) |
Duncan Laurie | 16a0f5c | 2013-09-25 14:08:16 -0700 | [diff] [blame] | 126 | usb_xhci_reset_port_usb3(mem_base, port); |
| 127 | else |
| 128 | port_disabled |= 1 << port; |
Duncan Laurie | 1f52908 | 2013-07-30 15:53:45 -0700 | [diff] [blame] | 129 | } |
| 130 | |
| 131 | /* Wait for warm reset complete on all reset ports */ |
| 132 | for (timeout = XHCI_RESET_TIMEOUT; timeout; timeout--) { |
| 133 | int complete = 1; |
| 134 | for (port = 0; port < port_count; port++) { |
| 135 | /* Only check ports that were reset */ |
| 136 | if (port_disabled & (1 << port)) |
| 137 | continue; |
| 138 | /* Check if warm reset is complete */ |
| 139 | status = read32(mem_base + XHCI_USB3_PORTSC(port)); |
| 140 | if (!(status & XHCI_USB3_PORTSC_WRC)) |
| 141 | complete = 0; |
| 142 | } |
| 143 | /* Check for warm reset complete in any port */ |
| 144 | if (complete) |
| 145 | break; |
| 146 | udelay(XHCI_RESET_DELAY_US); |
| 147 | } |
| 148 | |
| 149 | /* Clear port change status bits */ |
| 150 | for (port = 0; port < port_count; port++) |
| 151 | usb_xhci_reset_status_usb3(mem_base, port); |
| 152 | } |
| 153 | |
Duncan Laurie | 32d2e2b | 2013-09-25 14:08:32 -0700 | [diff] [blame] | 154 | #ifdef __SMM__ |
| 155 | |
Duncan Laurie | 1f52908 | 2013-07-30 15:53:45 -0700 | [diff] [blame] | 156 | /* Handler for XHCI controller on entry to S3/S4/S5 */ |
Elyes HAOUAS | ab72fc2 | 2018-11-29 16:13:14 +0100 | [diff] [blame] | 157 | void usb_xhci_sleep_prepare(pci_devfn_t dev, u8 slp_typ) |
Duncan Laurie | 1f52908 | 2013-07-30 15:53:45 -0700 | [diff] [blame] | 158 | { |
| 159 | u16 reg16; |
| 160 | u32 reg32; |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 161 | u8 *mem_base = usb_xhci_mem_base(dev); |
Duncan Laurie | 1f52908 | 2013-07-30 15:53:45 -0700 | [diff] [blame] | 162 | |
Aaron Durbin | da5f509 | 2016-07-13 23:23:16 -0500 | [diff] [blame] | 163 | if (!mem_base || slp_typ < ACPI_S3) |
Duncan Laurie | 1f52908 | 2013-07-30 15:53:45 -0700 | [diff] [blame] | 164 | return; |
| 165 | |
| 166 | if (pch_is_lp()) { |
| 167 | /* Set D0 state */ |
| 168 | reg16 = pci_read_config16(dev, XHCI_PWR_CTL_STS); |
| 169 | reg16 &= ~PWR_CTL_SET_MASK; |
| 170 | reg16 |= PWR_CTL_SET_D0; |
| 171 | pci_write_config16(dev, XHCI_PWR_CTL_STS, reg16); |
| 172 | |
| 173 | /* Clear PCI 0xB0[14:13] */ |
| 174 | reg32 = pci_read_config32(dev, 0xb0); |
| 175 | reg32 &= ~((1 << 14) | (1 << 13)); |
| 176 | pci_write_config32(dev, 0xb0, reg32); |
| 177 | |
| 178 | /* Clear MMIO 0x816c[14,2] */ |
| 179 | reg32 = read32(mem_base + 0x816c); |
| 180 | reg32 &= ~((1 << 14) | (1 << 2)); |
| 181 | write32(mem_base + 0x816c, reg32); |
| 182 | |
Duncan Laurie | 0bf1dea | 2013-08-13 13:32:28 -0700 | [diff] [blame] | 183 | /* Reset disconnected USB3 ports */ |
Duncan Laurie | 16a0f5c | 2013-09-25 14:08:16 -0700 | [diff] [blame] | 184 | usb_xhci_reset_usb3(dev, 0); |
Duncan Laurie | 0bf1dea | 2013-08-13 13:32:28 -0700 | [diff] [blame] | 185 | |
Duncan Laurie | 1f52908 | 2013-07-30 15:53:45 -0700 | [diff] [blame] | 186 | /* Set MMIO 0x80e0[15] */ |
| 187 | reg32 = read32(mem_base + 0x80e0); |
| 188 | reg32 |= (1 << 15); |
| 189 | write32(mem_base + 0x80e0, reg32); |
| 190 | } |
| 191 | |
| 192 | /* Set D3Hot state and enable PME */ |
| 193 | pci_or_config16(dev, XHCI_PWR_CTL_STS, PWR_CTL_SET_D3); |
Duncan Laurie | 0bf1dea | 2013-08-13 13:32:28 -0700 | [diff] [blame] | 194 | pci_or_config16(dev, XHCI_PWR_CTL_STS, PWR_CTL_STATUS_PME); |
Duncan Laurie | 1f52908 | 2013-07-30 15:53:45 -0700 | [diff] [blame] | 195 | pci_or_config16(dev, XHCI_PWR_CTL_STS, PWR_CTL_ENABLE_PME); |
| 196 | } |
| 197 | |
Duncan Laurie | 911cedf | 2013-07-30 16:05:55 -0700 | [diff] [blame] | 198 | /* Route all ports to XHCI controller */ |
| 199 | void usb_xhci_route_all(void) |
| 200 | { |
| 201 | u32 port_mask, route; |
| 202 | u16 reg16; |
| 203 | |
| 204 | /* Skip if EHCI is already disabled */ |
| 205 | if (RCBA32(FD) & PCH_DISABLE_EHCI1) |
| 206 | return; |
| 207 | |
| 208 | /* Set D0 state */ |
| 209 | reg16 = pci_read_config16(PCH_XHCI_DEV, XHCI_PWR_CTL_STS); |
| 210 | reg16 &= ~PWR_CTL_SET_MASK; |
| 211 | reg16 |= PWR_CTL_SET_D0; |
| 212 | pci_write_config16(PCH_XHCI_DEV, XHCI_PWR_CTL_STS, reg16); |
| 213 | |
| 214 | /* Set USB3 superspeed enable */ |
| 215 | port_mask = pci_read_config32(PCH_XHCI_DEV, XHCI_USB3PRM); |
| 216 | route = pci_read_config32(PCH_XHCI_DEV, XHCI_USB3PR); |
| 217 | route &= ~XHCI_USB3PR_SSEN; |
| 218 | route |= XHCI_USB3PR_SSEN & port_mask; |
| 219 | pci_write_config32(PCH_XHCI_DEV, XHCI_USB3PR, route); |
| 220 | |
| 221 | /* Route USB2 ports to XHCI controller */ |
| 222 | port_mask = pci_read_config32(PCH_XHCI_DEV, XHCI_USB2PRM); |
| 223 | route = pci_read_config32(PCH_XHCI_DEV, XHCI_USB2PR); |
| 224 | route &= ~XHCI_USB2PR_HCSEL; |
| 225 | route |= XHCI_USB2PR_HCSEL & port_mask; |
| 226 | pci_write_config32(PCH_XHCI_DEV, XHCI_USB2PR, route); |
| 227 | |
| 228 | /* Disable EHCI controller */ |
| 229 | usb_ehci_disable(PCH_EHCI1_DEV); |
| 230 | |
| 231 | /* LynxPoint-H has a second EHCI controller */ |
| 232 | if (!pch_is_lp()) |
| 233 | usb_ehci_disable(PCH_EHCI2_DEV); |
| 234 | |
| 235 | /* Reset and clear port change status */ |
Duncan Laurie | 16a0f5c | 2013-09-25 14:08:16 -0700 | [diff] [blame] | 236 | usb_xhci_reset_usb3(PCH_XHCI_DEV, 1); |
Duncan Laurie | 911cedf | 2013-07-30 16:05:55 -0700 | [diff] [blame] | 237 | } |
| 238 | |
Duncan Laurie | 1f52908 | 2013-07-30 15:53:45 -0700 | [diff] [blame] | 239 | #else /* !__SMM__ */ |
| 240 | |
Elyes HAOUAS | ab72fc2 | 2018-11-29 16:13:14 +0100 | [diff] [blame] | 241 | static void usb_xhci_clock_gating(struct device *dev) |
Duncan Laurie | 2d9d39a | 2013-05-29 15:27:55 -0700 | [diff] [blame] | 242 | { |
| 243 | u32 reg32; |
Duncan Laurie | 0dcb577 | 2013-07-30 15:58:18 -0700 | [diff] [blame] | 244 | u16 reg16; |
Duncan Laurie | 2d9d39a | 2013-05-29 15:27:55 -0700 | [diff] [blame] | 245 | |
| 246 | /* IOBP 0xE5004001[7:6] = 11b */ |
| 247 | pch_iobp_update(0xe5004001, ~0, (1 << 7)|(1 << 6)); |
| 248 | |
| 249 | reg32 = pci_read_config32(dev, 0x40); |
| 250 | reg32 &= ~(1 << 23); /* unsupported request */ |
| 251 | |
| 252 | if (pch_is_lp()) { |
| 253 | /* D20:F0:40h[18,17,8] = 111b */ |
| 254 | reg32 |= (1 << 18) | (1 << 17) | (1 << 8); |
| 255 | /* D20:F0:40h[21,20,19] = 110b to enable XHCI Idle L1 */ |
| 256 | reg32 &= ~(1 << 19); |
| 257 | reg32 |= (1 << 21) | (1 << 20); |
| 258 | } else { |
| 259 | /* D20:F0:40h[21,20,18,17,8] = 11111b */ |
| 260 | reg32 |= (1 << 21)|(1 << 20)|(1 << 18)|(1 << 17)|(1 << 8); |
| 261 | } |
| 262 | |
| 263 | /* Avoid writing upper byte as it is write-once */ |
| 264 | pci_write_config16(dev, 0x40, (u16)(reg32 & 0xffff)); |
| 265 | pci_write_config8(dev, 0x40 + 2, (u8)((reg32 >> 16) & 0xff)); |
| 266 | |
| 267 | /* D20:F0:44h[9,7,3] = 111b */ |
Duncan Laurie | 0dcb577 | 2013-07-30 15:58:18 -0700 | [diff] [blame] | 268 | reg16 = pci_read_config16(dev, 0x44); |
| 269 | reg16 |= (1 << 9) | (1 << 7) | (1 << 3); |
| 270 | pci_write_config16(dev, 0x44, reg16); |
Duncan Laurie | 2d9d39a | 2013-05-29 15:27:55 -0700 | [diff] [blame] | 271 | |
| 272 | reg32 = pci_read_config32(dev, 0xa0); |
| 273 | if (pch_is_lp()) { |
| 274 | /* D20:F0:A0h[18] = 1 */ |
| 275 | reg32 |= (1 << 18); |
| 276 | } else { |
| 277 | /* D20:F0:A0h[6] = 1 */ |
| 278 | reg32 |= (1 << 6); |
| 279 | } |
| 280 | pci_write_config32(dev, 0xa0, reg32); |
| 281 | |
| 282 | /* D20:F0:A4h[13] = 0 */ |
| 283 | reg32 = pci_read_config32(dev, 0xa4); |
| 284 | reg32 &= ~(1 << 13); |
| 285 | pci_write_config32(dev, 0xa4, reg32); |
| 286 | } |
| 287 | |
Elyes HAOUAS | ab72fc2 | 2018-11-29 16:13:14 +0100 | [diff] [blame] | 288 | static void usb_xhci_init(struct device *dev) |
Duncan Laurie | 2d9d39a | 2013-05-29 15:27:55 -0700 | [diff] [blame] | 289 | { |
Duncan Laurie | 2d9d39a | 2013-05-29 15:27:55 -0700 | [diff] [blame] | 290 | u32 reg32; |
Duncan Laurie | 0dcb577 | 2013-07-30 15:58:18 -0700 | [diff] [blame] | 291 | u16 reg16; |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 292 | u8 *mem_base = usb_xhci_mem_base(dev); |
Stefan Reinauer | 6dbbe2e | 2013-10-17 17:00:26 -0700 | [diff] [blame] | 293 | config_t *config = dev->chip_info; |
Duncan Laurie | 2d9d39a | 2013-05-29 15:27:55 -0700 | [diff] [blame] | 294 | |
Duncan Laurie | 0dcb577 | 2013-07-30 15:58:18 -0700 | [diff] [blame] | 295 | /* D20:F0:74h[1:0] = 00b (set D0 state) */ |
| 296 | reg16 = pci_read_config16(dev, XHCI_PWR_CTL_STS); |
| 297 | reg16 &= ~PWR_CTL_SET_MASK; |
| 298 | reg16 |= PWR_CTL_SET_D0; |
| 299 | pci_write_config16(dev, XHCI_PWR_CTL_STS, reg16); |
Duncan Laurie | 2d9d39a | 2013-05-29 15:27:55 -0700 | [diff] [blame] | 300 | |
| 301 | /* Enable clock gating first */ |
| 302 | usb_xhci_clock_gating(dev); |
| 303 | |
Duncan Laurie | 0dcb577 | 2013-07-30 15:58:18 -0700 | [diff] [blame] | 304 | reg32 = read32(mem_base + 0x8144); |
Duncan Laurie | 2d9d39a | 2013-05-29 15:27:55 -0700 | [diff] [blame] | 305 | if (pch_is_lp()) { |
| 306 | /* XHCIBAR + 8144h[8,7,6] = 111b */ |
| 307 | reg32 |= (1 << 8) | (1 << 7) | (1 << 6); |
| 308 | } else { |
| 309 | /* XHCIBAR + 8144h[8,7,6] = 100b */ |
| 310 | reg32 &= ~((1 << 7) | (1 << 6)); |
| 311 | reg32 |= (1 << 8); |
| 312 | } |
Duncan Laurie | 0dcb577 | 2013-07-30 15:58:18 -0700 | [diff] [blame] | 313 | write32(mem_base + 0x8144, reg32); |
Duncan Laurie | 2d9d39a | 2013-05-29 15:27:55 -0700 | [diff] [blame] | 314 | |
| 315 | if (pch_is_lp()) { |
Duncan Laurie | 527b03a | 2013-08-28 09:53:50 -0700 | [diff] [blame] | 316 | /* XHCIBAR + 816Ch[19:0] = 000e0038h */ |
Duncan Laurie | 0dcb577 | 2013-07-30 15:58:18 -0700 | [diff] [blame] | 317 | reg32 = read32(mem_base + 0x816c); |
Duncan Laurie | 2d9d39a | 2013-05-29 15:27:55 -0700 | [diff] [blame] | 318 | reg32 &= ~0x000fffff; |
Duncan Laurie | 527b03a | 2013-08-28 09:53:50 -0700 | [diff] [blame] | 319 | reg32 |= 0x000e0038; |
Duncan Laurie | 0dcb577 | 2013-07-30 15:58:18 -0700 | [diff] [blame] | 320 | write32(mem_base + 0x816c, reg32); |
Duncan Laurie | 2d9d39a | 2013-05-29 15:27:55 -0700 | [diff] [blame] | 321 | |
| 322 | /* D20:F0:B0h[17,14,13] = 100b */ |
| 323 | reg32 = pci_read_config32(dev, 0xb0); |
| 324 | reg32 &= ~((1 << 14) | (1 << 13)); |
| 325 | reg32 |= (1 << 17); |
| 326 | pci_write_config32(dev, 0xb0, reg32); |
Duncan Laurie | 2d9d39a | 2013-05-29 15:27:55 -0700 | [diff] [blame] | 327 | } |
| 328 | |
| 329 | reg32 = pci_read_config32(dev, 0x50); |
| 330 | if (pch_is_lp()) { |
| 331 | /* D20:F0:50h[28:0] = 0FCE2E5Fh */ |
| 332 | reg32 &= ~0x1fffffff; |
| 333 | reg32 |= 0x0fce2e5f; |
| 334 | } else { |
| 335 | /* D20:F0:50h[26:0] = 07886E9Fh */ |
| 336 | reg32 &= ~0x07ffffff; |
| 337 | reg32 |= 0x07886e9f; |
| 338 | } |
| 339 | pci_write_config32(dev, 0x50, reg32); |
| 340 | |
| 341 | /* D20:F0:44h[31] = 1 (Access Control Bit) */ |
Duncan Laurie | 0dcb577 | 2013-07-30 15:58:18 -0700 | [diff] [blame] | 342 | reg32 = pci_read_config32(dev, 0x44); |
Ryan Salsamendi | 0d9b360 | 2017-06-30 17:15:57 -0700 | [diff] [blame] | 343 | reg32 |= (1UL << 31); |
Duncan Laurie | 0dcb577 | 2013-07-30 15:58:18 -0700 | [diff] [blame] | 344 | pci_write_config32(dev, 0x44, reg32); |
Duncan Laurie | 2d9d39a | 2013-05-29 15:27:55 -0700 | [diff] [blame] | 345 | |
| 346 | /* D20:F0:40h[31,23] = 10b (OC Configuration Done) */ |
| 347 | reg32 = pci_read_config32(dev, 0x40); |
| 348 | reg32 &= ~(1 << 23); /* unsupported request */ |
Ryan Salsamendi | 0d9b360 | 2017-06-30 17:15:57 -0700 | [diff] [blame] | 349 | reg32 |= (1UL << 31); |
Duncan Laurie | 2d9d39a | 2013-05-29 15:27:55 -0700 | [diff] [blame] | 350 | pci_write_config32(dev, 0x40, reg32); |
Duncan Laurie | 32d2e2b | 2013-09-25 14:08:32 -0700 | [diff] [blame] | 351 | |
| 352 | if (acpi_is_wakeup_s3()) { |
| 353 | /* Reset ports that are disabled or |
| 354 | * polling before returning to the OS. */ |
| 355 | usb_xhci_reset_usb3(dev, 0); |
Stefan Reinauer | 6dbbe2e | 2013-10-17 17:00:26 -0700 | [diff] [blame] | 356 | } else if (config->xhci_default) { |
| 357 | /* Route all ports to XHCI */ |
| 358 | outb(0xca, 0xb2); |
Duncan Laurie | 32d2e2b | 2013-09-25 14:08:32 -0700 | [diff] [blame] | 359 | } |
Duncan Laurie | 2d9d39a | 2013-05-29 15:27:55 -0700 | [diff] [blame] | 360 | } |
| 361 | |
Elyes HAOUAS | ab72fc2 | 2018-11-29 16:13:14 +0100 | [diff] [blame] | 362 | static void usb_xhci_set_subsystem(struct device *dev, unsigned int vendor, |
| 363 | unsigned int device) |
Duncan Laurie | 2d9d39a | 2013-05-29 15:27:55 -0700 | [diff] [blame] | 364 | { |
| 365 | if (!vendor || !device) { |
| 366 | pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, |
| 367 | pci_read_config32(dev, PCI_VENDOR_ID)); |
| 368 | } else { |
| 369 | pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, |
| 370 | ((device & 0xffff) << 16) | (vendor & 0xffff)); |
| 371 | } |
| 372 | } |
| 373 | |
| 374 | static struct pci_operations lops_pci = { |
| 375 | .set_subsystem = &usb_xhci_set_subsystem, |
| 376 | }; |
| 377 | |
| 378 | static struct device_operations usb_xhci_ops = { |
| 379 | .read_resources = pci_dev_read_resources, |
| 380 | .set_resources = pci_dev_set_resources, |
| 381 | .enable_resources = pci_dev_enable_resources, |
| 382 | .init = usb_xhci_init, |
| 383 | .ops_pci = &lops_pci, |
| 384 | }; |
| 385 | |
| 386 | static const unsigned short pci_device_ids[] = { 0x8c31, /* LynxPoint-H */ |
| 387 | 0x9c31, /* LynxPoint-LP */ |
| 388 | 0 }; |
| 389 | |
| 390 | static const struct pci_driver pch_usb_xhci __pci_driver = { |
| 391 | .ops = &usb_xhci_ops, |
| 392 | .vendor = PCI_VENDOR_ID_INTEL, |
| 393 | .devices = pci_device_ids, |
| 394 | }; |
Duncan Laurie | 1f52908 | 2013-07-30 15:53:45 -0700 | [diff] [blame] | 395 | #endif /* !__SMM__ */ |