Duncan Laurie | 2d9d39a | 2013-05-29 15:27:55 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2013 Google Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; version 2 of |
| 9 | * the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 19 | */ |
| 20 | |
Duncan Laurie | 1f52908 | 2013-07-30 15:53:45 -0700 | [diff] [blame] | 21 | #include <console/console.h> |
| 22 | #include <delay.h> |
Duncan Laurie | 2d9d39a | 2013-05-29 15:27:55 -0700 | [diff] [blame] | 23 | #include <device/device.h> |
| 24 | #include <device/pci.h> |
| 25 | #include <device/pci_ids.h> |
| 26 | #include <arch/io.h> |
| 27 | #include "pch.h" |
| 28 | |
Duncan Laurie | 1f52908 | 2013-07-30 15:53:45 -0700 | [diff] [blame] | 29 | static u32 usb_xhci_mem_base(device_t dev) |
| 30 | { |
| 31 | u32 mem_base = pci_read_config32(dev, PCI_BASE_ADDRESS_0); |
| 32 | |
| 33 | /* Check if the controller is disabled or not present */ |
| 34 | if (mem_base == 0 || mem_base == 0xffffffff) |
| 35 | return 0; |
| 36 | |
| 37 | return mem_base & ~0xf; |
| 38 | } |
| 39 | |
Duncan Laurie | 1f52908 | 2013-07-30 15:53:45 -0700 | [diff] [blame] | 40 | static int usb_xhci_port_count_usb3(device_t dev) |
| 41 | { |
| 42 | if (pch_is_lp()) { |
| 43 | /* LynxPoint-LP has 4 SS ports */ |
| 44 | return 4; |
| 45 | } else { |
| 46 | /* LynxPoint-H can have 0, 2, 4, or 6 SS ports */ |
| 47 | u32 mem_base = usb_xhci_mem_base(dev); |
| 48 | u32 fus = read32(mem_base + XHCI_USB3FUS); |
| 49 | fus >>= XHCI_USB3FUS_SS_SHIFT; |
| 50 | fus &= XHCI_USB3FUS_SS_MASK; |
| 51 | switch (fus) { |
| 52 | case 3: return 0; |
| 53 | case 2: return 2; |
| 54 | case 1: return 4; |
| 55 | case 0: default: return 6; |
| 56 | } |
| 57 | } |
| 58 | return 0; |
| 59 | } |
| 60 | |
| 61 | static void usb_xhci_reset_status_usb3(u32 mem_base, int port) |
| 62 | { |
| 63 | u32 portsc = mem_base + XHCI_USB3_PORTSC(port); |
| 64 | write32(portsc, read32(portsc) | XHCI_USB3_PORTSC_CHST); |
| 65 | } |
| 66 | |
| 67 | static void usb_xhci_reset_port_usb3(u32 mem_base, int port) |
| 68 | { |
| 69 | u32 portsc = mem_base + XHCI_USB3_PORTSC(port); |
| 70 | write32(portsc, read32(portsc) | XHCI_USB3_PORTSC_WPR); |
| 71 | } |
| 72 | |
Duncan Laurie | 911cedf | 2013-07-30 16:05:55 -0700 | [diff] [blame] | 73 | #ifdef __SMM__ |
| 74 | |
Duncan Laurie | 1f52908 | 2013-07-30 15:53:45 -0700 | [diff] [blame] | 75 | #define XHCI_RESET_DELAY_US 1000 /* 1ms */ |
| 76 | #define XHCI_RESET_TIMEOUT 100 /* 100ms */ |
| 77 | |
| 78 | /* |
| 79 | * 1) Wait until port is done polling |
| 80 | * 2) If port is disconnected |
| 81 | * a) Issue warm port reset |
| 82 | * b) Poll for warm reset complete |
| 83 | * c) Write 1 to port change status bits |
| 84 | */ |
| 85 | static void usb_xhci_reset_usb3(device_t dev, int all) |
| 86 | { |
| 87 | u32 status, port_disabled; |
| 88 | int timeout, port; |
| 89 | int port_count = usb_xhci_port_count_usb3(dev); |
| 90 | u32 mem_base = usb_xhci_mem_base(dev); |
| 91 | |
| 92 | if (!mem_base || !port_count) |
| 93 | return; |
| 94 | |
| 95 | /* Get mask of disabled ports */ |
| 96 | port_disabled = pci_read_config32(dev, XHCI_USB3PDO); |
| 97 | |
| 98 | /* Wait until all enabled ports are done polling */ |
| 99 | for (timeout = XHCI_RESET_TIMEOUT; timeout; timeout--) { |
| 100 | int complete = 1; |
| 101 | for (port = 0; port < port_count; port++) { |
| 102 | /* Skip disabled ports */ |
| 103 | if (port_disabled & (1 << port)) |
| 104 | continue; |
| 105 | /* Read port link status field */ |
| 106 | status = read32(mem_base + XHCI_USB3_PORTSC(port)); |
| 107 | status &= XHCI_USB3_PORTSC_PLS; |
| 108 | if (status == XHCI_PLSR_POLLING) |
| 109 | complete = 0; |
| 110 | } |
| 111 | /* Exit if all ports not polling */ |
| 112 | if (complete) |
| 113 | break; |
| 114 | udelay(XHCI_RESET_DELAY_US); |
| 115 | } |
| 116 | |
| 117 | /* Reset all requested ports */ |
| 118 | for (port = 0; port < port_count; port++) { |
| 119 | u32 portsc = mem_base + XHCI_USB3_PORTSC(port); |
| 120 | /* Skip disabled ports */ |
| 121 | if (port_disabled & (1 << port)) |
| 122 | continue; |
| 123 | status = read32(portsc) & XHCI_USB3_PORTSC_PLS; |
| 124 | /* Reset all or only disconnected ports */ |
| 125 | if (all || status == XHCI_PLSR_RXDETECT) |
| 126 | usb_xhci_reset_port_usb3(mem_base, port); |
| 127 | else |
| 128 | port_disabled |= 1 << port; /* No reset */ |
| 129 | } |
| 130 | |
| 131 | /* Wait for warm reset complete on all reset ports */ |
| 132 | for (timeout = XHCI_RESET_TIMEOUT; timeout; timeout--) { |
| 133 | int complete = 1; |
| 134 | for (port = 0; port < port_count; port++) { |
| 135 | /* Only check ports that were reset */ |
| 136 | if (port_disabled & (1 << port)) |
| 137 | continue; |
| 138 | /* Check if warm reset is complete */ |
| 139 | status = read32(mem_base + XHCI_USB3_PORTSC(port)); |
| 140 | if (!(status & XHCI_USB3_PORTSC_WRC)) |
| 141 | complete = 0; |
| 142 | } |
| 143 | /* Check for warm reset complete in any port */ |
| 144 | if (complete) |
| 145 | break; |
| 146 | udelay(XHCI_RESET_DELAY_US); |
| 147 | } |
| 148 | |
| 149 | /* Clear port change status bits */ |
| 150 | for (port = 0; port < port_count; port++) |
| 151 | usb_xhci_reset_status_usb3(mem_base, port); |
| 152 | } |
| 153 | |
Duncan Laurie | 1f52908 | 2013-07-30 15:53:45 -0700 | [diff] [blame] | 154 | /* Handler for XHCI controller on entry to S3/S4/S5 */ |
| 155 | void usb_xhci_sleep_prepare(device_t dev, u8 slp_typ) |
| 156 | { |
| 157 | u16 reg16; |
| 158 | u32 reg32; |
| 159 | u32 mem_base = usb_xhci_mem_base(dev); |
| 160 | |
| 161 | if (!mem_base || slp_typ < 3) |
| 162 | return; |
| 163 | |
| 164 | if (pch_is_lp()) { |
| 165 | /* Set D0 state */ |
| 166 | reg16 = pci_read_config16(dev, XHCI_PWR_CTL_STS); |
| 167 | reg16 &= ~PWR_CTL_SET_MASK; |
| 168 | reg16 |= PWR_CTL_SET_D0; |
| 169 | pci_write_config16(dev, XHCI_PWR_CTL_STS, reg16); |
| 170 | |
| 171 | /* Clear PCI 0xB0[14:13] */ |
| 172 | reg32 = pci_read_config32(dev, 0xb0); |
| 173 | reg32 &= ~((1 << 14) | (1 << 13)); |
| 174 | pci_write_config32(dev, 0xb0, reg32); |
| 175 | |
| 176 | /* Clear MMIO 0x816c[14,2] */ |
| 177 | reg32 = read32(mem_base + 0x816c); |
| 178 | reg32 &= ~((1 << 14) | (1 << 2)); |
| 179 | write32(mem_base + 0x816c, reg32); |
| 180 | |
| 181 | /* Set MMIO 0x80e0[15] */ |
| 182 | reg32 = read32(mem_base + 0x80e0); |
| 183 | reg32 |= (1 << 15); |
| 184 | write32(mem_base + 0x80e0, reg32); |
| 185 | } |
| 186 | |
| 187 | /* Set D3Hot state and enable PME */ |
| 188 | pci_or_config16(dev, XHCI_PWR_CTL_STS, PWR_CTL_SET_D3); |
| 189 | pci_or_config16(dev, XHCI_PWR_CTL_STS, PWR_CTL_ENABLE_PME); |
| 190 | } |
| 191 | |
Duncan Laurie | 911cedf | 2013-07-30 16:05:55 -0700 | [diff] [blame] | 192 | /* Route all ports to XHCI controller */ |
| 193 | void usb_xhci_route_all(void) |
| 194 | { |
| 195 | u32 port_mask, route; |
| 196 | u16 reg16; |
| 197 | |
| 198 | /* Skip if EHCI is already disabled */ |
| 199 | if (RCBA32(FD) & PCH_DISABLE_EHCI1) |
| 200 | return; |
| 201 | |
| 202 | /* Set D0 state */ |
| 203 | reg16 = pci_read_config16(PCH_XHCI_DEV, XHCI_PWR_CTL_STS); |
| 204 | reg16 &= ~PWR_CTL_SET_MASK; |
| 205 | reg16 |= PWR_CTL_SET_D0; |
| 206 | pci_write_config16(PCH_XHCI_DEV, XHCI_PWR_CTL_STS, reg16); |
| 207 | |
| 208 | /* Set USB3 superspeed enable */ |
| 209 | port_mask = pci_read_config32(PCH_XHCI_DEV, XHCI_USB3PRM); |
| 210 | route = pci_read_config32(PCH_XHCI_DEV, XHCI_USB3PR); |
| 211 | route &= ~XHCI_USB3PR_SSEN; |
| 212 | route |= XHCI_USB3PR_SSEN & port_mask; |
| 213 | pci_write_config32(PCH_XHCI_DEV, XHCI_USB3PR, route); |
| 214 | |
| 215 | /* Route USB2 ports to XHCI controller */ |
| 216 | port_mask = pci_read_config32(PCH_XHCI_DEV, XHCI_USB2PRM); |
| 217 | route = pci_read_config32(PCH_XHCI_DEV, XHCI_USB2PR); |
| 218 | route &= ~XHCI_USB2PR_HCSEL; |
| 219 | route |= XHCI_USB2PR_HCSEL & port_mask; |
| 220 | pci_write_config32(PCH_XHCI_DEV, XHCI_USB2PR, route); |
| 221 | |
| 222 | /* Disable EHCI controller */ |
| 223 | usb_ehci_disable(PCH_EHCI1_DEV); |
| 224 | |
| 225 | /* LynxPoint-H has a second EHCI controller */ |
| 226 | if (!pch_is_lp()) |
| 227 | usb_ehci_disable(PCH_EHCI2_DEV); |
| 228 | |
| 229 | /* Reset and clear port change status */ |
| 230 | usb_xhci_reset_usb3(PCH_XHCI_DEV, 1); |
| 231 | } |
| 232 | |
Duncan Laurie | 1f52908 | 2013-07-30 15:53:45 -0700 | [diff] [blame] | 233 | #else /* !__SMM__ */ |
| 234 | |
Duncan Laurie | 2d9d39a | 2013-05-29 15:27:55 -0700 | [diff] [blame] | 235 | static void usb_xhci_clock_gating(device_t dev) |
| 236 | { |
| 237 | u32 reg32; |
Duncan Laurie | 0dcb577 | 2013-07-30 15:58:18 -0700 | [diff] [blame^] | 238 | u16 reg16; |
Duncan Laurie | 2d9d39a | 2013-05-29 15:27:55 -0700 | [diff] [blame] | 239 | |
| 240 | /* IOBP 0xE5004001[7:6] = 11b */ |
| 241 | pch_iobp_update(0xe5004001, ~0, (1 << 7)|(1 << 6)); |
| 242 | |
| 243 | reg32 = pci_read_config32(dev, 0x40); |
| 244 | reg32 &= ~(1 << 23); /* unsupported request */ |
| 245 | |
| 246 | if (pch_is_lp()) { |
| 247 | /* D20:F0:40h[18,17,8] = 111b */ |
| 248 | reg32 |= (1 << 18) | (1 << 17) | (1 << 8); |
| 249 | /* D20:F0:40h[21,20,19] = 110b to enable XHCI Idle L1 */ |
| 250 | reg32 &= ~(1 << 19); |
| 251 | reg32 |= (1 << 21) | (1 << 20); |
| 252 | } else { |
| 253 | /* D20:F0:40h[21,20,18,17,8] = 11111b */ |
| 254 | reg32 |= (1 << 21)|(1 << 20)|(1 << 18)|(1 << 17)|(1 << 8); |
| 255 | } |
| 256 | |
| 257 | /* Avoid writing upper byte as it is write-once */ |
| 258 | pci_write_config16(dev, 0x40, (u16)(reg32 & 0xffff)); |
| 259 | pci_write_config8(dev, 0x40 + 2, (u8)((reg32 >> 16) & 0xff)); |
| 260 | |
| 261 | /* D20:F0:44h[9,7,3] = 111b */ |
Duncan Laurie | 0dcb577 | 2013-07-30 15:58:18 -0700 | [diff] [blame^] | 262 | reg16 = pci_read_config16(dev, 0x44); |
| 263 | reg16 |= (1 << 9) | (1 << 7) | (1 << 3); |
| 264 | pci_write_config16(dev, 0x44, reg16); |
Duncan Laurie | 2d9d39a | 2013-05-29 15:27:55 -0700 | [diff] [blame] | 265 | |
| 266 | reg32 = pci_read_config32(dev, 0xa0); |
| 267 | if (pch_is_lp()) { |
| 268 | /* D20:F0:A0h[18] = 1 */ |
| 269 | reg32 |= (1 << 18); |
| 270 | } else { |
| 271 | /* D20:F0:A0h[6] = 1 */ |
| 272 | reg32 |= (1 << 6); |
| 273 | } |
| 274 | pci_write_config32(dev, 0xa0, reg32); |
| 275 | |
| 276 | /* D20:F0:A4h[13] = 0 */ |
| 277 | reg32 = pci_read_config32(dev, 0xa4); |
| 278 | reg32 &= ~(1 << 13); |
| 279 | pci_write_config32(dev, 0xa4, reg32); |
| 280 | } |
| 281 | |
Duncan Laurie | 911cedf | 2013-07-30 16:05:55 -0700 | [diff] [blame] | 282 | /* Re-enable ports that are disabled */ |
| 283 | static void usb_xhci_enable_ports_usb3(device_t dev) |
| 284 | { |
| 285 | #if CONFIG_FINALIZE_USB_ROUTE_XHCI |
| 286 | int port; |
| 287 | u32 portsc, status, disabled; |
| 288 | u32 mem_base = usb_xhci_mem_base(dev); |
| 289 | int port_count = usb_xhci_port_count_usb3(dev); |
| 290 | |
| 291 | if (!mem_base || !port_count) |
| 292 | return; |
| 293 | |
| 294 | /* Get port disable override map */ |
| 295 | disabled = pci_read_config32(dev, XHCI_USB3PDO); |
| 296 | |
| 297 | for (port = 0; port < port_count; port++) { |
| 298 | /* Skip overridden ports */ |
| 299 | if (disabled & (1 << port)) |
| 300 | continue; |
| 301 | portsc = mem_base + XHCI_USB3_PORTSC(port); |
| 302 | status = read32(portsc) & XHCI_USB3_PORTSC_PLS; |
| 303 | |
| 304 | switch (status) { |
| 305 | case XHCI_PLSR_RXDETECT: |
| 306 | /* Clear change status */ |
| 307 | printk(BIOS_DEBUG, "usb_xhci reset port %d\n", port); |
| 308 | usb_xhci_reset_status_usb3(mem_base, port); |
| 309 | break; |
| 310 | case XHCI_PLSR_DISABLED: |
| 311 | default: |
| 312 | /* Transition to enabled */ |
| 313 | printk(BIOS_DEBUG, "usb_xhci enable port %d\n", port); |
| 314 | usb_xhci_reset_port_usb3(mem_base, port); |
| 315 | status = read32(portsc); |
| 316 | status &= ~XHCI_USB3_PORTSC_PLS; |
| 317 | status |= XHCI_PLSW_ENABLE | XHCI_USB3_PORTSC_LWS; |
| 318 | write32(portsc, status); |
| 319 | break; |
| 320 | } |
| 321 | } |
| 322 | #endif |
| 323 | } |
| 324 | |
Duncan Laurie | 2d9d39a | 2013-05-29 15:27:55 -0700 | [diff] [blame] | 325 | static void usb_xhci_init(device_t dev) |
| 326 | { |
Duncan Laurie | 2d9d39a | 2013-05-29 15:27:55 -0700 | [diff] [blame] | 327 | u32 reg32; |
Duncan Laurie | 0dcb577 | 2013-07-30 15:58:18 -0700 | [diff] [blame^] | 328 | u16 reg16; |
| 329 | u32 mem_base = usb_xhci_mem_base(dev); |
Duncan Laurie | 2d9d39a | 2013-05-29 15:27:55 -0700 | [diff] [blame] | 330 | |
Duncan Laurie | 0dcb577 | 2013-07-30 15:58:18 -0700 | [diff] [blame^] | 331 | /* D20:F0:74h[1:0] = 00b (set D0 state) */ |
| 332 | reg16 = pci_read_config16(dev, XHCI_PWR_CTL_STS); |
| 333 | reg16 &= ~PWR_CTL_SET_MASK; |
| 334 | reg16 |= PWR_CTL_SET_D0; |
| 335 | pci_write_config16(dev, XHCI_PWR_CTL_STS, reg16); |
Duncan Laurie | 2d9d39a | 2013-05-29 15:27:55 -0700 | [diff] [blame] | 336 | |
| 337 | /* Enable clock gating first */ |
| 338 | usb_xhci_clock_gating(dev); |
| 339 | |
Duncan Laurie | 0dcb577 | 2013-07-30 15:58:18 -0700 | [diff] [blame^] | 340 | reg32 = read32(mem_base + 0x8144); |
Duncan Laurie | 2d9d39a | 2013-05-29 15:27:55 -0700 | [diff] [blame] | 341 | if (pch_is_lp()) { |
| 342 | /* XHCIBAR + 8144h[8,7,6] = 111b */ |
| 343 | reg32 |= (1 << 8) | (1 << 7) | (1 << 6); |
| 344 | } else { |
| 345 | /* XHCIBAR + 8144h[8,7,6] = 100b */ |
| 346 | reg32 &= ~((1 << 7) | (1 << 6)); |
| 347 | reg32 |= (1 << 8); |
| 348 | } |
Duncan Laurie | 0dcb577 | 2013-07-30 15:58:18 -0700 | [diff] [blame^] | 349 | write32(mem_base + 0x8144, reg32); |
Duncan Laurie | 2d9d39a | 2013-05-29 15:27:55 -0700 | [diff] [blame] | 350 | |
| 351 | if (pch_is_lp()) { |
| 352 | /* XHCIBAR + 816Ch[19:0] = 000f0038h */ |
Duncan Laurie | 0dcb577 | 2013-07-30 15:58:18 -0700 | [diff] [blame^] | 353 | reg32 = read32(mem_base + 0x816c); |
Duncan Laurie | 2d9d39a | 2013-05-29 15:27:55 -0700 | [diff] [blame] | 354 | reg32 &= ~0x000fffff; |
| 355 | reg32 |= 0x000f0038; |
Duncan Laurie | 0dcb577 | 2013-07-30 15:58:18 -0700 | [diff] [blame^] | 356 | write32(mem_base + 0x816c, reg32); |
Duncan Laurie | 2d9d39a | 2013-05-29 15:27:55 -0700 | [diff] [blame] | 357 | |
| 358 | /* D20:F0:B0h[17,14,13] = 100b */ |
| 359 | reg32 = pci_read_config32(dev, 0xb0); |
| 360 | reg32 &= ~((1 << 14) | (1 << 13)); |
| 361 | reg32 |= (1 << 17); |
| 362 | pci_write_config32(dev, 0xb0, reg32); |
Duncan Laurie | 2d9d39a | 2013-05-29 15:27:55 -0700 | [diff] [blame] | 363 | } |
| 364 | |
| 365 | reg32 = pci_read_config32(dev, 0x50); |
| 366 | if (pch_is_lp()) { |
| 367 | /* D20:F0:50h[28:0] = 0FCE2E5Fh */ |
| 368 | reg32 &= ~0x1fffffff; |
| 369 | reg32 |= 0x0fce2e5f; |
| 370 | } else { |
| 371 | /* D20:F0:50h[26:0] = 07886E9Fh */ |
| 372 | reg32 &= ~0x07ffffff; |
| 373 | reg32 |= 0x07886e9f; |
| 374 | } |
| 375 | pci_write_config32(dev, 0x50, reg32); |
| 376 | |
| 377 | /* D20:F0:44h[31] = 1 (Access Control Bit) */ |
Duncan Laurie | 0dcb577 | 2013-07-30 15:58:18 -0700 | [diff] [blame^] | 378 | reg32 = pci_read_config32(dev, 0x44); |
Duncan Laurie | 2d9d39a | 2013-05-29 15:27:55 -0700 | [diff] [blame] | 379 | reg32 |= (1 << 31); |
Duncan Laurie | 0dcb577 | 2013-07-30 15:58:18 -0700 | [diff] [blame^] | 380 | pci_write_config32(dev, 0x44, reg32); |
Duncan Laurie | 2d9d39a | 2013-05-29 15:27:55 -0700 | [diff] [blame] | 381 | |
| 382 | /* D20:F0:40h[31,23] = 10b (OC Configuration Done) */ |
| 383 | reg32 = pci_read_config32(dev, 0x40); |
| 384 | reg32 &= ~(1 << 23); /* unsupported request */ |
| 385 | reg32 |= (1 << 31); |
| 386 | pci_write_config32(dev, 0x40, reg32); |
Duncan Laurie | 911cedf | 2013-07-30 16:05:55 -0700 | [diff] [blame] | 387 | |
| 388 | #if CONFIG_HAVE_ACPI_RESUME |
| 389 | /* Enable ports that are disabled before returning to OS */ |
| 390 | if (acpi_slp_type == 3) |
| 391 | usb_xhci_enable_ports_usb3(dev); |
| 392 | #endif |
Duncan Laurie | 2d9d39a | 2013-05-29 15:27:55 -0700 | [diff] [blame] | 393 | } |
| 394 | |
| 395 | static void usb_xhci_set_subsystem(device_t dev, unsigned vendor, |
| 396 | unsigned device) |
| 397 | { |
| 398 | if (!vendor || !device) { |
| 399 | pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, |
| 400 | pci_read_config32(dev, PCI_VENDOR_ID)); |
| 401 | } else { |
| 402 | pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, |
| 403 | ((device & 0xffff) << 16) | (vendor & 0xffff)); |
| 404 | } |
| 405 | } |
| 406 | |
| 407 | static struct pci_operations lops_pci = { |
| 408 | .set_subsystem = &usb_xhci_set_subsystem, |
| 409 | }; |
| 410 | |
| 411 | static struct device_operations usb_xhci_ops = { |
| 412 | .read_resources = pci_dev_read_resources, |
| 413 | .set_resources = pci_dev_set_resources, |
| 414 | .enable_resources = pci_dev_enable_resources, |
| 415 | .init = usb_xhci_init, |
| 416 | .ops_pci = &lops_pci, |
| 417 | }; |
| 418 | |
| 419 | static const unsigned short pci_device_ids[] = { 0x8c31, /* LynxPoint-H */ |
| 420 | 0x9c31, /* LynxPoint-LP */ |
| 421 | 0 }; |
| 422 | |
| 423 | static const struct pci_driver pch_usb_xhci __pci_driver = { |
| 424 | .ops = &usb_xhci_ops, |
| 425 | .vendor = PCI_VENDOR_ID_INTEL, |
| 426 | .devices = pci_device_ids, |
| 427 | }; |
Duncan Laurie | 1f52908 | 2013-07-30 15:53:45 -0700 | [diff] [blame] | 428 | #endif /* !__SMM__ */ |