x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointer
On x86, change the type of the address parameter in
read8()/read16/read32()/write8()/write16()/write32() to be a
pointer, instead of unsigned long.
Change-Id: Ic26dd8a72d82828b69be3c04944710681b7bd330
Signed-off-by: Kevin Paul Herbert <kph@meraki.net>
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/7784
Tested-by: build bot (Jenkins)
diff --git a/src/southbridge/intel/lynxpoint/usb_xhci.c b/src/southbridge/intel/lynxpoint/usb_xhci.c
index 6c7bf04..3b8c23b 100644
--- a/src/southbridge/intel/lynxpoint/usb_xhci.c
+++ b/src/southbridge/intel/lynxpoint/usb_xhci.c
@@ -28,7 +28,7 @@
typedef struct southbridge_intel_lynxpoint_config config_t;
-static u32 usb_xhci_mem_base(device_t dev)
+static u8 *usb_xhci_mem_base(device_t dev)
{
u32 mem_base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
@@ -36,7 +36,7 @@
if (mem_base == 0 || mem_base == 0xffffffff)
return 0;
- return mem_base & ~0xf;
+ return (u8 *)(mem_base & ~0xf);
}
static int usb_xhci_port_count_usb3(device_t dev)
@@ -46,7 +46,7 @@
return 4;
} else {
/* LynxPoint-H can have 0, 2, 4, or 6 SS ports */
- u32 mem_base = usb_xhci_mem_base(dev);
+ u8 *mem_base = usb_xhci_mem_base(dev);
u32 fus = read32(mem_base + XHCI_USB3FUS);
fus >>= XHCI_USB3FUS_SS_SHIFT;
fus &= XHCI_USB3FUS_SS_MASK;
@@ -60,9 +60,9 @@
return 0;
}
-static void usb_xhci_reset_status_usb3(u32 mem_base, int port)
+static void usb_xhci_reset_status_usb3(u8 *mem_base, int port)
{
- u32 portsc = mem_base + XHCI_USB3_PORTSC(port);
+ u8 *portsc = mem_base + XHCI_USB3_PORTSC(port);
u32 status = read32(portsc);
/* Do not set Port Enabled/Disabled field */
status &= ~XHCI_USB3_PORTSC_PED;
@@ -71,9 +71,9 @@
write32(portsc, status);
}
-static void usb_xhci_reset_port_usb3(u32 mem_base, int port)
+static void usb_xhci_reset_port_usb3(u8 *mem_base, int port)
{
- u32 portsc = mem_base + XHCI_USB3_PORTSC(port);
+ u8 *portsc = mem_base + XHCI_USB3_PORTSC(port);
write32(portsc, read32(portsc) | XHCI_USB3_PORTSC_WPR);
}
@@ -92,7 +92,7 @@
u32 status, port_disabled;
int timeout, port;
int port_count = usb_xhci_port_count_usb3(dev);
- u32 mem_base = usb_xhci_mem_base(dev);
+ u8 *mem_base = usb_xhci_mem_base(dev);
if (!mem_base || !port_count)
return;
@@ -121,7 +121,7 @@
/* Reset all requested ports */
for (port = 0; port < port_count; port++) {
- u32 portsc = mem_base + XHCI_USB3_PORTSC(port);
+ u8 *portsc = mem_base + XHCI_USB3_PORTSC(port);
/* Skip disabled ports */
if (port_disabled & (1 << port))
continue;
@@ -164,7 +164,7 @@
{
u16 reg16;
u32 reg32;
- u32 mem_base = usb_xhci_mem_base(dev);
+ u8 *mem_base = usb_xhci_mem_base(dev);
if (!mem_base || slp_typ < 3)
return;
@@ -295,7 +295,7 @@
{
u32 reg32;
u16 reg16;
- u32 mem_base = usb_xhci_mem_base(dev);
+ u8 *mem_base = usb_xhci_mem_base(dev);
config_t *config = dev->chip_info;
/* D20:F0:74h[1:0] = 00b (set D0 state) */