Duncan Laurie | 2d9d39a | 2013-05-29 15:27:55 -0700 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2013 Google Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; version 2 of |
| 9 | * the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 19 | */ |
| 20 | |
| 21 | #include <device/device.h> |
| 22 | #include <device/pci.h> |
| 23 | #include <device/pci_ids.h> |
| 24 | #include <arch/io.h> |
| 25 | #include "pch.h" |
| 26 | |
| 27 | static void usb_xhci_clock_gating(device_t dev) |
| 28 | { |
| 29 | u32 reg32; |
| 30 | |
| 31 | /* IOBP 0xE5004001[7:6] = 11b */ |
| 32 | pch_iobp_update(0xe5004001, ~0, (1 << 7)|(1 << 6)); |
| 33 | |
| 34 | reg32 = pci_read_config32(dev, 0x40); |
| 35 | reg32 &= ~(1 << 23); /* unsupported request */ |
| 36 | |
| 37 | if (pch_is_lp()) { |
| 38 | /* D20:F0:40h[18,17,8] = 111b */ |
| 39 | reg32 |= (1 << 18) | (1 << 17) | (1 << 8); |
| 40 | /* D20:F0:40h[21,20,19] = 110b to enable XHCI Idle L1 */ |
| 41 | reg32 &= ~(1 << 19); |
| 42 | reg32 |= (1 << 21) | (1 << 20); |
| 43 | } else { |
| 44 | /* D20:F0:40h[21,20,18,17,8] = 11111b */ |
| 45 | reg32 |= (1 << 21)|(1 << 20)|(1 << 18)|(1 << 17)|(1 << 8); |
| 46 | } |
| 47 | |
| 48 | /* Avoid writing upper byte as it is write-once */ |
| 49 | pci_write_config16(dev, 0x40, (u16)(reg32 & 0xffff)); |
| 50 | pci_write_config8(dev, 0x40 + 2, (u8)((reg32 >> 16) & 0xff)); |
| 51 | |
| 52 | /* D20:F0:44h[9,7,3] = 111b */ |
| 53 | reg32 = pci_read_config32(dev, 0x44); |
| 54 | reg32 |= (1 << 9) | (1 << 7) | (1 << 3); |
| 55 | pci_write_config32(dev, 0x44, reg32); |
| 56 | |
| 57 | reg32 = pci_read_config32(dev, 0xa0); |
| 58 | if (pch_is_lp()) { |
| 59 | /* D20:F0:A0h[18] = 1 */ |
| 60 | reg32 |= (1 << 18); |
| 61 | } else { |
| 62 | /* D20:F0:A0h[6] = 1 */ |
| 63 | reg32 |= (1 << 6); |
| 64 | } |
| 65 | pci_write_config32(dev, 0xa0, reg32); |
| 66 | |
| 67 | /* D20:F0:A4h[13] = 0 */ |
| 68 | reg32 = pci_read_config32(dev, 0xa4); |
| 69 | reg32 &= ~(1 << 13); |
| 70 | pci_write_config32(dev, 0xa4, reg32); |
| 71 | } |
| 72 | |
| 73 | static void usb_xhci_init(device_t dev) |
| 74 | { |
| 75 | struct resource *bar0 = find_resource(dev, PCI_BASE_ADDRESS_0); |
| 76 | u32 reg32; |
| 77 | |
| 78 | if (!bar0 || bar0->base == 0 || bar0->base == 0xffffffff) |
| 79 | return; |
| 80 | |
| 81 | /* Enable clock gating first */ |
| 82 | usb_xhci_clock_gating(dev); |
| 83 | |
| 84 | /* D20:F0:74h[1:0] = 11b (set D3Hot state) */ |
| 85 | reg32 = pci_read_config16(dev, 0x74); |
| 86 | reg32 |= (1 << 1) | (1 << 0); |
| 87 | pci_write_config16(dev, 0x74, reg32); |
| 88 | |
| 89 | reg32 = read32(bar0->base + 0x8144); |
| 90 | if (pch_is_lp()) { |
| 91 | /* XHCIBAR + 8144h[8,7,6] = 111b */ |
| 92 | reg32 |= (1 << 8) | (1 << 7) | (1 << 6); |
| 93 | } else { |
| 94 | /* XHCIBAR + 8144h[8,7,6] = 100b */ |
| 95 | reg32 &= ~((1 << 7) | (1 << 6)); |
| 96 | reg32 |= (1 << 8); |
| 97 | } |
| 98 | write32(bar0->base + 0x8144, reg32); |
| 99 | |
| 100 | if (pch_is_lp()) { |
| 101 | /* XHCIBAR + 816Ch[19:0] = 000f0038h */ |
| 102 | reg32 = read32(bar0->base + 0x816c); |
| 103 | reg32 &= ~0x000fffff; |
| 104 | reg32 |= 0x000f0038; |
| 105 | write32(bar0->base + 0x816c, reg32); |
| 106 | |
| 107 | /* D20:F0:B0h[17,14,13] = 100b */ |
| 108 | reg32 = pci_read_config32(dev, 0xb0); |
| 109 | reg32 &= ~((1 << 14) | (1 << 13)); |
| 110 | reg32 |= (1 << 17); |
| 111 | pci_write_config32(dev, 0xb0, reg32); |
| 112 | |
| 113 | /* XHCIBAR + 818Ch[7:0] = FFh */ |
| 114 | reg32 = read32(bar0->base + 0x818c); |
| 115 | reg32 |= 0xff; |
| 116 | write32(bar0->base + 0x818c, reg32); |
| 117 | } |
| 118 | |
| 119 | reg32 = pci_read_config32(dev, 0x50); |
| 120 | if (pch_is_lp()) { |
| 121 | /* D20:F0:50h[28:0] = 0FCE2E5Fh */ |
| 122 | reg32 &= ~0x1fffffff; |
| 123 | reg32 |= 0x0fce2e5f; |
| 124 | } else { |
| 125 | /* D20:F0:50h[26:0] = 07886E9Fh */ |
| 126 | reg32 &= ~0x07ffffff; |
| 127 | reg32 |= 0x07886e9f; |
| 128 | } |
| 129 | pci_write_config32(dev, 0x50, reg32); |
| 130 | |
| 131 | /* D20:F0:44h[31] = 1 (Access Control Bit) */ |
| 132 | reg32 = pci_read_config32(dev, 0x40); |
| 133 | reg32 |= (1 << 31); |
| 134 | pci_write_config32(dev, 0x40, reg32); |
| 135 | |
| 136 | /* D20:F0:40h[31,23] = 10b (OC Configuration Done) */ |
| 137 | reg32 = pci_read_config32(dev, 0x40); |
| 138 | reg32 &= ~(1 << 23); /* unsupported request */ |
| 139 | reg32 |= (1 << 31); |
| 140 | pci_write_config32(dev, 0x40, reg32); |
| 141 | } |
| 142 | |
| 143 | static void usb_xhci_set_subsystem(device_t dev, unsigned vendor, |
| 144 | unsigned device) |
| 145 | { |
| 146 | if (!vendor || !device) { |
| 147 | pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, |
| 148 | pci_read_config32(dev, PCI_VENDOR_ID)); |
| 149 | } else { |
| 150 | pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, |
| 151 | ((device & 0xffff) << 16) | (vendor & 0xffff)); |
| 152 | } |
| 153 | } |
| 154 | |
| 155 | static struct pci_operations lops_pci = { |
| 156 | .set_subsystem = &usb_xhci_set_subsystem, |
| 157 | }; |
| 158 | |
| 159 | static struct device_operations usb_xhci_ops = { |
| 160 | .read_resources = pci_dev_read_resources, |
| 161 | .set_resources = pci_dev_set_resources, |
| 162 | .enable_resources = pci_dev_enable_resources, |
| 163 | .init = usb_xhci_init, |
| 164 | .ops_pci = &lops_pci, |
| 165 | }; |
| 166 | |
| 167 | static const unsigned short pci_device_ids[] = { 0x8c31, /* LynxPoint-H */ |
| 168 | 0x9c31, /* LynxPoint-LP */ |
| 169 | 0 }; |
| 170 | |
| 171 | static const struct pci_driver pch_usb_xhci __pci_driver = { |
| 172 | .ops = &usb_xhci_ops, |
| 173 | .vendor = PCI_VENDOR_ID_INTEL, |
| 174 | .devices = pci_device_ids, |
| 175 | }; |