Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2005 Yinghai Lu <yinghailu@gmail.com> |
| 5 | * Copyright (C) 2009 coresystems GmbH |
| 6 | * Copyright (C) 2013 Vladimir Serbinenko |
Frans Hendriks | e48be35 | 2019-06-19 11:01:27 +0200 | [diff] [blame] | 7 | * Copyright (C) 2018-2019 Eltan B.V. |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License as published by |
| 11 | * the Free Software Foundation; version 2 of the License. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | */ |
| 18 | |
| 19 | #include <arch/io.h> |
Kyösti Mälkki | b5d998b | 2017-08-20 21:36:08 +0300 | [diff] [blame] | 20 | #include <console/console.h> |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 21 | #include <device/smbus_def.h> |
Kyösti Mälkki | 1cae454 | 2020-01-06 12:31:34 +0200 | [diff] [blame^] | 22 | #include <device/smbus_host.h> |
Elyes HAOUAS | ab89edb | 2019-05-15 21:10:44 +0200 | [diff] [blame] | 23 | #include <types.h> |
| 24 | |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 25 | #include "smbus.h" |
| 26 | |
| 27 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 28 | #if CONFIG(DEBUG_SMBUS) |
Kyösti Mälkki | b5d998b | 2017-08-20 21:36:08 +0300 | [diff] [blame] | 29 | #define dprintk(args...) printk(BIOS_DEBUG, ##args) |
| 30 | #else |
| 31 | #define dprintk(args...) do {} while (0) |
| 32 | #endif |
| 33 | |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 34 | /* I801 command constants */ |
| 35 | #define I801_QUICK (0 << 2) |
| 36 | #define I801_BYTE (1 << 2) |
| 37 | #define I801_BYTE_DATA (2 << 2) |
| 38 | #define I801_WORD_DATA (3 << 2) |
| 39 | #define I801_BLOCK_DATA (5 << 2) |
| 40 | #define I801_I2C_BLOCK_DATA (6 << 2) /* ICH5 and later */ |
| 41 | |
| 42 | /* I801 Host Control register bits */ |
| 43 | #define SMBHSTCNT_INTREN (1 << 0) |
| 44 | #define SMBHSTCNT_KILL (1 << 1) |
| 45 | #define SMBHSTCNT_LAST_BYTE (1 << 5) |
| 46 | #define SMBHSTCNT_START (1 << 6) |
| 47 | #define SMBHSTCNT_PEC_EN (1 << 7) /* ICH3 and later */ |
| 48 | |
| 49 | /* I801 Hosts Status register bits */ |
| 50 | #define SMBHSTSTS_BYTE_DONE (1 << 7) |
| 51 | #define SMBHSTSTS_INUSE_STS (1 << 6) |
| 52 | #define SMBHSTSTS_SMBALERT_STS (1 << 5) |
| 53 | #define SMBHSTSTS_FAILED (1 << 4) |
| 54 | #define SMBHSTSTS_BUS_ERR (1 << 3) |
| 55 | #define SMBHSTSTS_DEV_ERR (1 << 2) |
| 56 | #define SMBHSTSTS_INTR (1 << 1) |
| 57 | #define SMBHSTSTS_HOST_BUSY (1 << 0) |
| 58 | |
Kyösti Mälkki | 957511c | 2017-08-20 21:36:11 +0300 | [diff] [blame] | 59 | /* For SMBXMITADD register. */ |
| 60 | #define XMIT_WRITE(dev) (((dev) << 1) | 0) |
| 61 | #define XMIT_READ(dev) (((dev) << 1) | 1) |
| 62 | |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 63 | #define SMBUS_TIMEOUT (10 * 1000 * 100) |
Elyes HAOUAS | b0f1988 | 2018-06-09 11:59:00 +0200 | [diff] [blame] | 64 | #define SMBUS_BLOCK_MAXLEN 32 |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 65 | |
Kyösti Mälkki | 893edee | 2017-08-20 21:36:24 +0300 | [diff] [blame] | 66 | /* block_cmd_loop flags */ |
| 67 | #define BLOCK_READ 0 |
| 68 | #define BLOCK_WRITE (1 << 0) |
| 69 | #define BLOCK_I2C (1 << 1) |
| 70 | |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 71 | static void smbus_delay(void) |
| 72 | { |
| 73 | inb(0x80); |
| 74 | } |
| 75 | |
Kyösti Mälkki | 5e9ae0c | 2020-01-06 13:35:59 +0200 | [diff] [blame] | 76 | static void host_outb(uintptr_t base, u8 reg, u8 value) |
Kyösti Mälkki | b49638d | 2020-01-02 16:36:56 +0200 | [diff] [blame] | 77 | { |
| 78 | outb(value, base + reg); |
| 79 | } |
| 80 | |
Kyösti Mälkki | 5e9ae0c | 2020-01-06 13:35:59 +0200 | [diff] [blame] | 81 | static u8 host_inb(uintptr_t base, u8 reg) |
Kyösti Mälkki | b49638d | 2020-01-02 16:36:56 +0200 | [diff] [blame] | 82 | { |
| 83 | return inb(base + reg); |
| 84 | } |
| 85 | |
Kyösti Mälkki | 5e9ae0c | 2020-01-06 13:35:59 +0200 | [diff] [blame] | 86 | static void host_and_or(uintptr_t base, u8 reg, u8 mask, u8 or) |
Kyösti Mälkki | 65f5de2 | 2020-01-02 16:36:56 +0200 | [diff] [blame] | 87 | { |
| 88 | u8 value; |
| 89 | value = host_inb(base, reg); |
| 90 | value &= mask; |
| 91 | value |= or; |
| 92 | host_outb(base, reg, value); |
| 93 | } |
| 94 | |
Kyösti Mälkki | c38d543 | 2017-08-20 21:36:18 +0300 | [diff] [blame] | 95 | static int host_completed(u8 status) |
| 96 | { |
| 97 | if (status & SMBHSTSTS_HOST_BUSY) |
| 98 | return 0; |
Kyösti Mälkki | 44206e3 | 2019-02-26 17:17:24 +0200 | [diff] [blame] | 99 | |
| 100 | /* These status bits do not imply completion of transaction. */ |
| 101 | status &= ~(SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INUSE_STS | |
| 102 | SMBHSTSTS_SMBALERT_STS); |
Kyösti Mälkki | c38d543 | 2017-08-20 21:36:18 +0300 | [diff] [blame] | 103 | return status != 0; |
| 104 | } |
| 105 | |
Kyösti Mälkki | 5e9ae0c | 2020-01-06 13:35:59 +0200 | [diff] [blame] | 106 | static int recover_master(uintptr_t base, int ret) |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 107 | { |
Kyösti Mälkki | 957511c | 2017-08-20 21:36:11 +0300 | [diff] [blame] | 108 | /* TODO: Depending of the failure, drive KILL transaction |
| 109 | * or force soft reset on SMBus master controller. |
| 110 | */ |
| 111 | printk(BIOS_ERR, "SMBus: Fatal master timeout (%d)\n", ret); |
| 112 | return ret; |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 113 | } |
| 114 | |
Kyösti Mälkki | c38d543 | 2017-08-20 21:36:18 +0300 | [diff] [blame] | 115 | static int cb_err_from_stat(u8 status) |
| 116 | { |
Kyösti Mälkki | 44206e3 | 2019-02-26 17:17:24 +0200 | [diff] [blame] | 117 | /* These status bits do not imply errors. */ |
| 118 | status &= ~(SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INUSE_STS | |
| 119 | SMBHSTSTS_SMBALERT_STS); |
Kyösti Mälkki | c38d543 | 2017-08-20 21:36:18 +0300 | [diff] [blame] | 120 | |
| 121 | if (status == SMBHSTSTS_INTR) |
| 122 | return 0; |
| 123 | |
| 124 | return SMBUS_ERROR; |
| 125 | } |
| 126 | |
Kyösti Mälkki | 5e9ae0c | 2020-01-06 13:35:59 +0200 | [diff] [blame] | 127 | static int setup_command(uintptr_t base, u8 ctrl, u8 xmitadd) |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 128 | { |
| 129 | unsigned int loops = SMBUS_TIMEOUT; |
Kyösti Mälkki | 957511c | 2017-08-20 21:36:11 +0300 | [diff] [blame] | 130 | u8 host_busy; |
| 131 | |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 132 | do { |
| 133 | smbus_delay(); |
Kyösti Mälkki | 5e9ae0c | 2020-01-06 13:35:59 +0200 | [diff] [blame] | 134 | host_busy = host_inb(base, SMBHSTSTAT) & SMBHSTSTS_HOST_BUSY; |
Kyösti Mälkki | 957511c | 2017-08-20 21:36:11 +0300 | [diff] [blame] | 135 | } while (--loops && host_busy); |
| 136 | |
| 137 | if (loops == 0) |
Kyösti Mälkki | 5e9ae0c | 2020-01-06 13:35:59 +0200 | [diff] [blame] | 138 | return recover_master(base, SMBUS_WAIT_UNTIL_READY_TIMEOUT); |
Kyösti Mälkki | 957511c | 2017-08-20 21:36:11 +0300 | [diff] [blame] | 139 | |
| 140 | /* Clear any lingering errors, so the transaction will run. */ |
Kyösti Mälkki | 5e9ae0c | 2020-01-06 13:35:59 +0200 | [diff] [blame] | 141 | host_and_or(base, SMBHSTSTAT, 0xff, 0); |
Kyösti Mälkki | 957511c | 2017-08-20 21:36:11 +0300 | [diff] [blame] | 142 | |
| 143 | /* Set up transaction */ |
| 144 | /* Disable interrupts */ |
Kyösti Mälkki | 5e9ae0c | 2020-01-06 13:35:59 +0200 | [diff] [blame] | 145 | host_outb(base, SMBHSTCTL, ctrl); |
Kyösti Mälkki | 957511c | 2017-08-20 21:36:11 +0300 | [diff] [blame] | 146 | |
| 147 | /* Set the device I'm talking to. */ |
Kyösti Mälkki | 5e9ae0c | 2020-01-06 13:35:59 +0200 | [diff] [blame] | 148 | host_outb(base, SMBXMITADD, xmitadd); |
Kyösti Mälkki | 957511c | 2017-08-20 21:36:11 +0300 | [diff] [blame] | 149 | |
| 150 | return 0; |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 151 | } |
| 152 | |
Kyösti Mälkki | 5e9ae0c | 2020-01-06 13:35:59 +0200 | [diff] [blame] | 153 | static int execute_command(uintptr_t base) |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 154 | { |
Kyösti Mälkki | a2dcf73 | 2017-08-20 21:36:15 +0300 | [diff] [blame] | 155 | unsigned int loops = SMBUS_TIMEOUT; |
| 156 | u8 status; |
| 157 | |
| 158 | /* Start the command. */ |
Kyösti Mälkki | 5e9ae0c | 2020-01-06 13:35:59 +0200 | [diff] [blame] | 159 | host_and_or(base, SMBHSTCTL, 0xff, SMBHSTCNT_START); |
Kyösti Mälkki | a2dcf73 | 2017-08-20 21:36:15 +0300 | [diff] [blame] | 160 | |
| 161 | /* Poll for it to start. */ |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 162 | do { |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 163 | smbus_delay(); |
Kyösti Mälkki | a2dcf73 | 2017-08-20 21:36:15 +0300 | [diff] [blame] | 164 | |
| 165 | /* If we poll too slow, we could miss HOST_BUSY flag |
| 166 | * set and detect INTR or x_ERR flags instead here. |
| 167 | */ |
Kyösti Mälkki | 5e9ae0c | 2020-01-06 13:35:59 +0200 | [diff] [blame] | 168 | status = host_inb(base, SMBHSTSTAT); |
Kyösti Mälkki | a2dcf73 | 2017-08-20 21:36:15 +0300 | [diff] [blame] | 169 | status &= ~(SMBHSTSTS_SMBALERT_STS | SMBHSTSTS_INUSE_STS); |
| 170 | } while (--loops && status == 0); |
| 171 | |
| 172 | if (loops == 0) |
Kyösti Mälkki | 5e9ae0c | 2020-01-06 13:35:59 +0200 | [diff] [blame] | 173 | return recover_master(base, |
Kyösti Mälkki | a2dcf73 | 2017-08-20 21:36:15 +0300 | [diff] [blame] | 174 | SMBUS_WAIT_UNTIL_ACTIVE_TIMEOUT); |
| 175 | |
| 176 | return 0; |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 177 | } |
| 178 | |
Kyösti Mälkki | 5e9ae0c | 2020-01-06 13:35:59 +0200 | [diff] [blame] | 179 | static int complete_command(uintptr_t base) |
Kyösti Mälkki | 957511c | 2017-08-20 21:36:11 +0300 | [diff] [blame] | 180 | { |
| 181 | unsigned int loops = SMBUS_TIMEOUT; |
Kyösti Mälkki | c38d543 | 2017-08-20 21:36:18 +0300 | [diff] [blame] | 182 | u8 status; |
| 183 | |
Kyösti Mälkki | 957511c | 2017-08-20 21:36:11 +0300 | [diff] [blame] | 184 | do { |
| 185 | smbus_delay(); |
Kyösti Mälkki | 5e9ae0c | 2020-01-06 13:35:59 +0200 | [diff] [blame] | 186 | status = host_inb(base, SMBHSTSTAT); |
Kyösti Mälkki | c38d543 | 2017-08-20 21:36:18 +0300 | [diff] [blame] | 187 | } while (--loops && !host_completed(status)); |
| 188 | |
| 189 | if (loops == 0) |
Kyösti Mälkki | 5e9ae0c | 2020-01-06 13:35:59 +0200 | [diff] [blame] | 190 | return recover_master(base, |
Kyösti Mälkki | c38d543 | 2017-08-20 21:36:18 +0300 | [diff] [blame] | 191 | SMBUS_WAIT_UNTIL_DONE_TIMEOUT); |
| 192 | |
| 193 | return cb_err_from_stat(status); |
Kyösti Mälkki | 957511c | 2017-08-20 21:36:11 +0300 | [diff] [blame] | 194 | } |
| 195 | |
Kyösti Mälkki | 5e9ae0c | 2020-01-06 13:35:59 +0200 | [diff] [blame] | 196 | static int smbus_read_cmd(uintptr_t base, u8 ctrl, u8 device, u8 address) |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 197 | { |
Kyösti Mälkki | 957511c | 2017-08-20 21:36:11 +0300 | [diff] [blame] | 198 | int ret; |
Kyösti Mälkki | 7ca19b2 | 2020-01-02 17:02:54 +0200 | [diff] [blame] | 199 | u16 word; |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 200 | |
Kyösti Mälkki | 957511c | 2017-08-20 21:36:11 +0300 | [diff] [blame] | 201 | /* Set up for a byte data read. */ |
Kyösti Mälkki | 5e9ae0c | 2020-01-06 13:35:59 +0200 | [diff] [blame] | 202 | ret = setup_command(base, ctrl, XMIT_READ(device)); |
Kyösti Mälkki | 957511c | 2017-08-20 21:36:11 +0300 | [diff] [blame] | 203 | if (ret < 0) |
| 204 | return ret; |
| 205 | |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 206 | /* Set the command/address... */ |
Kyösti Mälkki | 5e9ae0c | 2020-01-06 13:35:59 +0200 | [diff] [blame] | 207 | host_outb(base, SMBHSTCMD, address); |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 208 | |
Kyösti Mälkki | 7ca19b2 | 2020-01-02 17:02:54 +0200 | [diff] [blame] | 209 | /* Clear the data bytes... */ |
Kyösti Mälkki | 5e9ae0c | 2020-01-06 13:35:59 +0200 | [diff] [blame] | 210 | host_outb(base, SMBHSTDAT0, 0); |
| 211 | host_outb(base, SMBHSTDAT1, 0); |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 212 | |
| 213 | /* Start the command */ |
Kyösti Mälkki | 5e9ae0c | 2020-01-06 13:35:59 +0200 | [diff] [blame] | 214 | ret = execute_command(base); |
Kyösti Mälkki | a2dcf73 | 2017-08-20 21:36:15 +0300 | [diff] [blame] | 215 | if (ret < 0) |
| 216 | return ret; |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 217 | |
| 218 | /* Poll for transaction completion */ |
Kyösti Mälkki | 5e9ae0c | 2020-01-06 13:35:59 +0200 | [diff] [blame] | 219 | ret = complete_command(base); |
Kyösti Mälkki | c38d543 | 2017-08-20 21:36:18 +0300 | [diff] [blame] | 220 | if (ret < 0) |
| 221 | return ret; |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 222 | |
| 223 | /* Read results of transaction */ |
Kyösti Mälkki | 5e9ae0c | 2020-01-06 13:35:59 +0200 | [diff] [blame] | 224 | word = host_inb(base, SMBHSTDAT0); |
Kyösti Mälkki | 7ca19b2 | 2020-01-02 17:02:54 +0200 | [diff] [blame] | 225 | if (ctrl == I801_WORD_DATA) |
Kyösti Mälkki | 5e9ae0c | 2020-01-06 13:35:59 +0200 | [diff] [blame] | 226 | word |= host_inb(base, SMBHSTDAT1) << 8; |
Kyösti Mälkki | 7ca19b2 | 2020-01-02 17:02:54 +0200 | [diff] [blame] | 227 | |
| 228 | return word; |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 229 | } |
| 230 | |
Kyösti Mälkki | 5e9ae0c | 2020-01-06 13:35:59 +0200 | [diff] [blame] | 231 | static int smbus_write_cmd(uintptr_t base, u8 ctrl, u8 device, u8 address, u16 data) |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 232 | { |
Kyösti Mälkki | 957511c | 2017-08-20 21:36:11 +0300 | [diff] [blame] | 233 | int ret; |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 234 | |
Kyösti Mälkki | 957511c | 2017-08-20 21:36:11 +0300 | [diff] [blame] | 235 | /* Set up for a byte data write. */ |
Kyösti Mälkki | 5e9ae0c | 2020-01-06 13:35:59 +0200 | [diff] [blame] | 236 | ret = setup_command(base, ctrl, XMIT_WRITE(device)); |
Kyösti Mälkki | 957511c | 2017-08-20 21:36:11 +0300 | [diff] [blame] | 237 | if (ret < 0) |
| 238 | return ret; |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 239 | |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 240 | /* Set the command/address... */ |
Kyösti Mälkki | 5e9ae0c | 2020-01-06 13:35:59 +0200 | [diff] [blame] | 241 | host_outb(base, SMBHSTCMD, address); |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 242 | |
Kyösti Mälkki | 7ca19b2 | 2020-01-02 17:02:54 +0200 | [diff] [blame] | 243 | /* Set the data bytes... */ |
Kyösti Mälkki | 5e9ae0c | 2020-01-06 13:35:59 +0200 | [diff] [blame] | 244 | host_outb(base, SMBHSTDAT0, data & 0xff); |
Kyösti Mälkki | 7ca19b2 | 2020-01-02 17:02:54 +0200 | [diff] [blame] | 245 | if (ctrl == I801_WORD_DATA) |
Kyösti Mälkki | 5e9ae0c | 2020-01-06 13:35:59 +0200 | [diff] [blame] | 246 | host_outb(base, SMBHSTDAT1, data >> 8); |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 247 | |
| 248 | /* Start the command */ |
Kyösti Mälkki | 5e9ae0c | 2020-01-06 13:35:59 +0200 | [diff] [blame] | 249 | ret = execute_command(base); |
Kyösti Mälkki | a2dcf73 | 2017-08-20 21:36:15 +0300 | [diff] [blame] | 250 | if (ret < 0) |
| 251 | return ret; |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 252 | |
| 253 | /* Poll for transaction completion */ |
Kyösti Mälkki | 5e9ae0c | 2020-01-06 13:35:59 +0200 | [diff] [blame] | 254 | return complete_command(base); |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 255 | } |
| 256 | |
Kyösti Mälkki | 5e9ae0c | 2020-01-06 13:35:59 +0200 | [diff] [blame] | 257 | static int block_cmd_loop(uintptr_t base, u8 *buf, size_t max_bytes, int flags) |
Kyösti Mälkki | 893edee | 2017-08-20 21:36:24 +0300 | [diff] [blame] | 258 | { |
| 259 | u8 status; |
| 260 | unsigned int loops = SMBUS_TIMEOUT; |
Kyösti Mälkki | 5e9ae0c | 2020-01-06 13:35:59 +0200 | [diff] [blame] | 261 | int ret; |
| 262 | size_t bytes = 0; |
Kyösti Mälkki | 893edee | 2017-08-20 21:36:24 +0300 | [diff] [blame] | 263 | int is_write_cmd = flags & BLOCK_WRITE; |
| 264 | int sw_drives_nak = flags & BLOCK_I2C; |
| 265 | |
| 266 | /* Hardware limitations. */ |
| 267 | if (flags == (BLOCK_WRITE | BLOCK_I2C)) |
| 268 | return SMBUS_ERROR; |
| 269 | |
Kyösti Mälkki | d6c15d0 | 2017-08-20 21:36:24 +0300 | [diff] [blame] | 270 | /* Set number of bytes to transfer. */ |
| 271 | /* Reset number of bytes to transfer so we notice later it |
| 272 | * was really updated with the transaction. */ |
| 273 | if (!sw_drives_nak) { |
| 274 | if (is_write_cmd) |
Kyösti Mälkki | 5e9ae0c | 2020-01-06 13:35:59 +0200 | [diff] [blame] | 275 | host_outb(base, SMBHSTDAT0, max_bytes); |
Kyösti Mälkki | d6c15d0 | 2017-08-20 21:36:24 +0300 | [diff] [blame] | 276 | else |
Kyösti Mälkki | 5e9ae0c | 2020-01-06 13:35:59 +0200 | [diff] [blame] | 277 | host_outb(base, SMBHSTDAT0, 0); |
Kyösti Mälkki | d6c15d0 | 2017-08-20 21:36:24 +0300 | [diff] [blame] | 278 | } |
| 279 | |
| 280 | /* Send first byte from buffer, bytes_sent increments after |
| 281 | * hardware acknowledges it. |
| 282 | */ |
| 283 | if (is_write_cmd) |
Kyösti Mälkki | 5e9ae0c | 2020-01-06 13:35:59 +0200 | [diff] [blame] | 284 | host_outb(base, SMBBLKDAT, *buf++); |
Kyösti Mälkki | d6c15d0 | 2017-08-20 21:36:24 +0300 | [diff] [blame] | 285 | |
| 286 | /* Start the command */ |
Kyösti Mälkki | 5e9ae0c | 2020-01-06 13:35:59 +0200 | [diff] [blame] | 287 | ret = execute_command(base); |
Kyösti Mälkki | d6c15d0 | 2017-08-20 21:36:24 +0300 | [diff] [blame] | 288 | if (ret < 0) |
| 289 | return ret; |
| 290 | |
Kyösti Mälkki | 893edee | 2017-08-20 21:36:24 +0300 | [diff] [blame] | 291 | /* Poll for transaction completion */ |
| 292 | do { |
Kyösti Mälkki | 5e9ae0c | 2020-01-06 13:35:59 +0200 | [diff] [blame] | 293 | status = host_inb(base, SMBHSTSTAT); |
Kyösti Mälkki | 893edee | 2017-08-20 21:36:24 +0300 | [diff] [blame] | 294 | |
| 295 | if (status & SMBHSTSTS_BYTE_DONE) { /* Byte done */ |
| 296 | |
| 297 | if (is_write_cmd) { |
| 298 | bytes++; |
| 299 | if (bytes < max_bytes) |
Kyösti Mälkki | 5e9ae0c | 2020-01-06 13:35:59 +0200 | [diff] [blame] | 300 | host_outb(base, SMBBLKDAT, *buf++); |
Kyösti Mälkki | 893edee | 2017-08-20 21:36:24 +0300 | [diff] [blame] | 301 | } else { |
| 302 | if (bytes < max_bytes) |
Kyösti Mälkki | 5e9ae0c | 2020-01-06 13:35:59 +0200 | [diff] [blame] | 303 | *buf++ = host_inb(base, SMBBLKDAT); |
Kyösti Mälkki | 893edee | 2017-08-20 21:36:24 +0300 | [diff] [blame] | 304 | bytes++; |
| 305 | |
| 306 | /* Indicate that next byte is the last one. */ |
| 307 | if (sw_drives_nak && (bytes + 1 >= max_bytes)) { |
Kyösti Mälkki | 5e9ae0c | 2020-01-06 13:35:59 +0200 | [diff] [blame] | 308 | host_and_or(base, SMBHSTCTL, 0xff, |
| 309 | SMBHSTCNT_LAST_BYTE); |
Kyösti Mälkki | 893edee | 2017-08-20 21:36:24 +0300 | [diff] [blame] | 310 | } |
| 311 | |
| 312 | } |
| 313 | |
| 314 | /* Engine internally completes the transaction |
| 315 | * and clears HOST_BUSY flag once the byte count |
| 316 | * has been reached or LAST_BYTE was set. |
| 317 | */ |
Kyösti Mälkki | 5e9ae0c | 2020-01-06 13:35:59 +0200 | [diff] [blame] | 318 | host_outb(base, SMBHSTSTAT, SMBHSTSTS_BYTE_DONE); |
Kyösti Mälkki | 893edee | 2017-08-20 21:36:24 +0300 | [diff] [blame] | 319 | } |
| 320 | |
| 321 | } while (--loops && !host_completed(status)); |
| 322 | |
Kyösti Mälkki | 5e9ae0c | 2020-01-06 13:35:59 +0200 | [diff] [blame] | 323 | dprintk("%s: status = %02x, len = %zd / %zd, loops = %d\n", |
Kyösti Mälkki | 893edee | 2017-08-20 21:36:24 +0300 | [diff] [blame] | 324 | __func__, status, bytes, max_bytes, SMBUS_TIMEOUT - loops); |
| 325 | |
| 326 | if (loops == 0) |
Kyösti Mälkki | 5e9ae0c | 2020-01-06 13:35:59 +0200 | [diff] [blame] | 327 | return recover_master(base, SMBUS_WAIT_UNTIL_DONE_TIMEOUT); |
Kyösti Mälkki | 893edee | 2017-08-20 21:36:24 +0300 | [diff] [blame] | 328 | |
| 329 | ret = cb_err_from_stat(status); |
| 330 | if (ret < 0) |
| 331 | return ret; |
| 332 | |
| 333 | return bytes; |
| 334 | } |
| 335 | |
Kyösti Mälkki | 1cae454 | 2020-01-06 12:31:34 +0200 | [diff] [blame^] | 336 | int do_smbus_read_byte(uintptr_t smbus_base, u8 device, u8 address) |
Kyösti Mälkki | 7ca19b2 | 2020-01-02 17:02:54 +0200 | [diff] [blame] | 337 | { |
| 338 | return smbus_read_cmd(smbus_base, I801_BYTE_DATA, device, address); |
| 339 | } |
| 340 | |
Kyösti Mälkki | 1cae454 | 2020-01-06 12:31:34 +0200 | [diff] [blame^] | 341 | int do_smbus_read_word(uintptr_t smbus_base, u8 device, u8 address) |
Kyösti Mälkki | 7ca19b2 | 2020-01-02 17:02:54 +0200 | [diff] [blame] | 342 | { |
| 343 | return smbus_read_cmd(smbus_base, I801_WORD_DATA, device, address); |
| 344 | } |
| 345 | |
Kyösti Mälkki | 1cae454 | 2020-01-06 12:31:34 +0200 | [diff] [blame^] | 346 | int do_smbus_write_byte(uintptr_t smbus_base, u8 device, u8 address, u8 data) |
Kyösti Mälkki | 7ca19b2 | 2020-01-02 17:02:54 +0200 | [diff] [blame] | 347 | { |
| 348 | return smbus_write_cmd(smbus_base, I801_BYTE_DATA, device, address, data); |
| 349 | } |
| 350 | |
Kyösti Mälkki | 1cae454 | 2020-01-06 12:31:34 +0200 | [diff] [blame^] | 351 | int do_smbus_write_word(uintptr_t smbus_base, u8 device, u8 address, u16 data) |
Kyösti Mälkki | 7ca19b2 | 2020-01-02 17:02:54 +0200 | [diff] [blame] | 352 | { |
| 353 | return smbus_write_cmd(smbus_base, I801_WORD_DATA, device, address, data); |
| 354 | } |
| 355 | |
Kyösti Mälkki | 1cae454 | 2020-01-06 12:31:34 +0200 | [diff] [blame^] | 356 | int do_smbus_block_read(uintptr_t smbus_base, u8 device, u8 cmd, size_t max_bytes, u8 *buf) |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 357 | { |
Kyösti Mälkki | 957511c | 2017-08-20 21:36:11 +0300 | [diff] [blame] | 358 | int ret, slave_bytes; |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 359 | |
Kyösti Mälkki | c17e855 | 2017-08-20 23:48:23 +0300 | [diff] [blame] | 360 | max_bytes = MIN(SMBUS_BLOCK_MAXLEN, max_bytes); |
Arthur Heymans | 1b04aa2 | 2017-08-04 14:28:50 +0200 | [diff] [blame] | 361 | |
Kyösti Mälkki | 957511c | 2017-08-20 21:36:11 +0300 | [diff] [blame] | 362 | /* Set up for a block data read. */ |
| 363 | ret = setup_command(smbus_base, I801_BLOCK_DATA, XMIT_READ(device)); |
| 364 | if (ret < 0) |
| 365 | return ret; |
| 366 | |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 367 | /* Set the command/address... */ |
Kyösti Mälkki | b49638d | 2020-01-02 16:36:56 +0200 | [diff] [blame] | 368 | host_outb(smbus_base, SMBHSTCMD, cmd); |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 369 | |
Kyösti Mälkki | d6c15d0 | 2017-08-20 21:36:24 +0300 | [diff] [blame] | 370 | /* Execute block transaction. */ |
Kyösti Mälkki | 893edee | 2017-08-20 21:36:24 +0300 | [diff] [blame] | 371 | ret = block_cmd_loop(smbus_base, buf, max_bytes, BLOCK_READ); |
Kyösti Mälkki | c38d543 | 2017-08-20 21:36:18 +0300 | [diff] [blame] | 372 | if (ret < 0) |
| 373 | return ret; |
| 374 | |
Kyösti Mälkki | 893edee | 2017-08-20 21:36:24 +0300 | [diff] [blame] | 375 | /* Post-check we received complete message. */ |
Kyösti Mälkki | b49638d | 2020-01-02 16:36:56 +0200 | [diff] [blame] | 376 | slave_bytes = host_inb(smbus_base, SMBHSTDAT0); |
Kyösti Mälkki | 893edee | 2017-08-20 21:36:24 +0300 | [diff] [blame] | 377 | if (ret < slave_bytes) |
Arthur Heymans | 1b04aa2 | 2017-08-04 14:28:50 +0200 | [diff] [blame] | 378 | return SMBUS_ERROR; |
| 379 | |
Kyösti Mälkki | 893edee | 2017-08-20 21:36:24 +0300 | [diff] [blame] | 380 | return ret; |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 381 | } |
| 382 | |
Kyösti Mälkki | 1cae454 | 2020-01-06 12:31:34 +0200 | [diff] [blame^] | 383 | int do_smbus_block_write(uintptr_t smbus_base, u8 device, u8 cmd, const size_t bytes, const u8 *buf) |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 384 | { |
Kyösti Mälkki | 893edee | 2017-08-20 21:36:24 +0300 | [diff] [blame] | 385 | int ret; |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 386 | |
Kyösti Mälkki | c17e855 | 2017-08-20 23:48:23 +0300 | [diff] [blame] | 387 | if (bytes > SMBUS_BLOCK_MAXLEN) |
Arthur Heymans | 1b04aa2 | 2017-08-04 14:28:50 +0200 | [diff] [blame] | 388 | return SMBUS_ERROR; |
| 389 | |
Kyösti Mälkki | 957511c | 2017-08-20 21:36:11 +0300 | [diff] [blame] | 390 | /* Set up for a block data write. */ |
| 391 | ret = setup_command(smbus_base, I801_BLOCK_DATA, XMIT_WRITE(device)); |
| 392 | if (ret < 0) |
| 393 | return ret; |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 394 | |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 395 | /* Set the command/address... */ |
Kyösti Mälkki | b49638d | 2020-01-02 16:36:56 +0200 | [diff] [blame] | 396 | host_outb(smbus_base, SMBHSTCMD, cmd); |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 397 | |
Kyösti Mälkki | d6c15d0 | 2017-08-20 21:36:24 +0300 | [diff] [blame] | 398 | /* Execute block transaction. */ |
Kyösti Mälkki | 893edee | 2017-08-20 21:36:24 +0300 | [diff] [blame] | 399 | ret = block_cmd_loop(smbus_base, (u8 *)buf, bytes, BLOCK_WRITE); |
Kyösti Mälkki | c38d543 | 2017-08-20 21:36:18 +0300 | [diff] [blame] | 400 | if (ret < 0) |
| 401 | return ret; |
| 402 | |
Kyösti Mälkki | 893edee | 2017-08-20 21:36:24 +0300 | [diff] [blame] | 403 | if (ret < bytes) |
Kyösti Mälkki | c17e855 | 2017-08-20 23:48:23 +0300 | [diff] [blame] | 404 | return SMBUS_ERROR; |
| 405 | |
Kyösti Mälkki | 893edee | 2017-08-20 21:36:24 +0300 | [diff] [blame] | 406 | return ret; |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 407 | } |
| 408 | |
| 409 | /* Only since ICH5 */ |
Kyösti Mälkki | c01a505 | 2019-01-30 09:39:23 +0200 | [diff] [blame] | 410 | static int has_i2c_read_command(void) |
| 411 | { |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 412 | if (CONFIG(SOUTHBRIDGE_INTEL_I82371EB) || |
| 413 | CONFIG(SOUTHBRIDGE_INTEL_I82801DX)) |
Kyösti Mälkki | c01a505 | 2019-01-30 09:39:23 +0200 | [diff] [blame] | 414 | return 0; |
| 415 | return 1; |
| 416 | } |
| 417 | |
Kyösti Mälkki | 1cae454 | 2020-01-06 12:31:34 +0200 | [diff] [blame^] | 418 | int do_i2c_eeprom_read(uintptr_t smbus_base, u8 device, u8 offset, const size_t bytes, u8 *buf) |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 419 | { |
Kyösti Mälkki | 893edee | 2017-08-20 21:36:24 +0300 | [diff] [blame] | 420 | int ret; |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 421 | |
Kyösti Mälkki | c01a505 | 2019-01-30 09:39:23 +0200 | [diff] [blame] | 422 | if (!has_i2c_read_command()) |
| 423 | return SMBUS_ERROR; |
| 424 | |
Kyösti Mälkki | 957511c | 2017-08-20 21:36:11 +0300 | [diff] [blame] | 425 | /* Set up for a i2c block data read. |
| 426 | * |
| 427 | * FIXME: Address parameter changes to XMIT_READ(device) with |
| 428 | * some revision of PCH. Presumably hardware revisions that |
| 429 | * do not have i2c block write support internally set LSB. |
| 430 | */ |
| 431 | ret = setup_command(smbus_base, I801_I2C_BLOCK_DATA, |
| 432 | XMIT_WRITE(device)); |
| 433 | if (ret < 0) |
| 434 | return ret; |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 435 | |
| 436 | /* device offset */ |
Kyösti Mälkki | b49638d | 2020-01-02 16:36:56 +0200 | [diff] [blame] | 437 | host_outb(smbus_base, SMBHSTDAT1, offset); |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 438 | |
Kyösti Mälkki | d6c15d0 | 2017-08-20 21:36:24 +0300 | [diff] [blame] | 439 | /* Execute block transaction. */ |
Kyösti Mälkki | 893edee | 2017-08-20 21:36:24 +0300 | [diff] [blame] | 440 | ret = block_cmd_loop(smbus_base, buf, bytes, BLOCK_READ | BLOCK_I2C); |
Kyösti Mälkki | c38d543 | 2017-08-20 21:36:18 +0300 | [diff] [blame] | 441 | if (ret < 0) |
| 442 | return ret; |
| 443 | |
Kyösti Mälkki | 893edee | 2017-08-20 21:36:24 +0300 | [diff] [blame] | 444 | /* Post-check we received complete message. */ |
| 445 | if (ret < bytes) |
Kyösti Mälkki | 1e39236 | 2017-08-20 21:36:03 +0300 | [diff] [blame] | 446 | return SMBUS_ERROR; |
| 447 | |
Kyösti Mälkki | 893edee | 2017-08-20 21:36:24 +0300 | [diff] [blame] | 448 | return ret; |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 449 | } |
Frans Hendriks | e48be35 | 2019-06-19 11:01:27 +0200 | [diff] [blame] | 450 | |
| 451 | /* |
| 452 | * The caller is responsible of settings HOSTC I2C_EN bit prior to making this |
| 453 | * call! |
| 454 | */ |
Kyösti Mälkki | 1cae454 | 2020-01-06 12:31:34 +0200 | [diff] [blame^] | 455 | int do_i2c_block_write(uintptr_t smbus_base, u8 device, size_t bytes, u8 *buf) |
Frans Hendriks | e48be35 | 2019-06-19 11:01:27 +0200 | [diff] [blame] | 456 | { |
| 457 | u8 cmd; |
| 458 | int ret; |
| 459 | |
| 460 | if (!CONFIG(SOC_INTEL_BRASWELL)) |
| 461 | return SMBUS_ERROR; |
| 462 | |
| 463 | if (!bytes || (bytes > SMBUS_BLOCK_MAXLEN)) |
| 464 | return SMBUS_ERROR; |
| 465 | |
| 466 | /* Set up for a block data write. */ |
| 467 | ret = setup_command(smbus_base, I801_BLOCK_DATA, XMIT_WRITE(device)); |
| 468 | if (ret < 0) |
| 469 | return ret; |
| 470 | |
| 471 | /* |
| 472 | * In i2c mode SMBus controller sequence on bus will be: |
| 473 | * <SMBXINTADD> <SMBHSTDAT1> <SMBBLKDAT> .. <SMBBLKDAT> |
| 474 | * The SMBHSTCMD must be written also to ensure the SMBUs controller |
| 475 | * will generate the i2c sequence. |
| 476 | */ |
| 477 | cmd = *buf++; |
| 478 | bytes--; |
Kyösti Mälkki | b49638d | 2020-01-02 16:36:56 +0200 | [diff] [blame] | 479 | host_outb(smbus_base, SMBHSTCMD, cmd); |
| 480 | host_outb(smbus_base, SMBHSTDAT1, cmd); |
Frans Hendriks | e48be35 | 2019-06-19 11:01:27 +0200 | [diff] [blame] | 481 | |
| 482 | /* Execute block transaction. */ |
| 483 | ret = block_cmd_loop(smbus_base, buf, bytes, BLOCK_WRITE); |
| 484 | if (ret < 0) |
| 485 | return ret; |
| 486 | |
| 487 | if (ret < bytes) |
| 488 | return SMBUS_ERROR; |
| 489 | |
| 490 | ret++; /* 1st byte has been written using SMBHSTDAT1 */ |
| 491 | return ret; |
| 492 | } |