Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2005 Yinghai Lu <yinghailu@gmail.com> |
| 5 | * Copyright (C) 2009 coresystems GmbH |
| 6 | * Copyright (C) 2013 Vladimir Serbinenko |
Frans Hendriks | e48be35 | 2019-06-19 11:01:27 +0200 | [diff] [blame^] | 7 | * Copyright (C) 2018-2019 Eltan B.V. |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License as published by |
| 11 | * the Free Software Foundation; version 2 of the License. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | */ |
| 18 | |
| 19 | #include <arch/io.h> |
Kyösti Mälkki | b5d998b | 2017-08-20 21:36:08 +0300 | [diff] [blame] | 20 | #include <console/console.h> |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 21 | #include <device/smbus_def.h> |
Arthur Heymans | 1b04aa2 | 2017-08-04 14:28:50 +0200 | [diff] [blame] | 22 | #include <stdlib.h> |
Elyes HAOUAS | ab89edb | 2019-05-15 21:10:44 +0200 | [diff] [blame] | 23 | #include <types.h> |
| 24 | |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 25 | #include "smbus.h" |
| 26 | |
| 27 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 28 | #if CONFIG(DEBUG_SMBUS) |
Kyösti Mälkki | b5d998b | 2017-08-20 21:36:08 +0300 | [diff] [blame] | 29 | #define dprintk(args...) printk(BIOS_DEBUG, ##args) |
| 30 | #else |
| 31 | #define dprintk(args...) do {} while (0) |
| 32 | #endif |
| 33 | |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 34 | /* I801 command constants */ |
| 35 | #define I801_QUICK (0 << 2) |
| 36 | #define I801_BYTE (1 << 2) |
| 37 | #define I801_BYTE_DATA (2 << 2) |
| 38 | #define I801_WORD_DATA (3 << 2) |
| 39 | #define I801_BLOCK_DATA (5 << 2) |
| 40 | #define I801_I2C_BLOCK_DATA (6 << 2) /* ICH5 and later */ |
| 41 | |
| 42 | /* I801 Host Control register bits */ |
| 43 | #define SMBHSTCNT_INTREN (1 << 0) |
| 44 | #define SMBHSTCNT_KILL (1 << 1) |
| 45 | #define SMBHSTCNT_LAST_BYTE (1 << 5) |
| 46 | #define SMBHSTCNT_START (1 << 6) |
| 47 | #define SMBHSTCNT_PEC_EN (1 << 7) /* ICH3 and later */ |
| 48 | |
| 49 | /* I801 Hosts Status register bits */ |
| 50 | #define SMBHSTSTS_BYTE_DONE (1 << 7) |
| 51 | #define SMBHSTSTS_INUSE_STS (1 << 6) |
| 52 | #define SMBHSTSTS_SMBALERT_STS (1 << 5) |
| 53 | #define SMBHSTSTS_FAILED (1 << 4) |
| 54 | #define SMBHSTSTS_BUS_ERR (1 << 3) |
| 55 | #define SMBHSTSTS_DEV_ERR (1 << 2) |
| 56 | #define SMBHSTSTS_INTR (1 << 1) |
| 57 | #define SMBHSTSTS_HOST_BUSY (1 << 0) |
| 58 | |
Kyösti Mälkki | 957511c | 2017-08-20 21:36:11 +0300 | [diff] [blame] | 59 | /* For SMBXMITADD register. */ |
| 60 | #define XMIT_WRITE(dev) (((dev) << 1) | 0) |
| 61 | #define XMIT_READ(dev) (((dev) << 1) | 1) |
| 62 | |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 63 | #define SMBUS_TIMEOUT (10 * 1000 * 100) |
Elyes HAOUAS | b0f1988 | 2018-06-09 11:59:00 +0200 | [diff] [blame] | 64 | #define SMBUS_BLOCK_MAXLEN 32 |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 65 | |
Kyösti Mälkki | 893edee | 2017-08-20 21:36:24 +0300 | [diff] [blame] | 66 | /* block_cmd_loop flags */ |
| 67 | #define BLOCK_READ 0 |
| 68 | #define BLOCK_WRITE (1 << 0) |
| 69 | #define BLOCK_I2C (1 << 1) |
| 70 | |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 71 | static void smbus_delay(void) |
| 72 | { |
| 73 | inb(0x80); |
| 74 | } |
| 75 | |
Kyösti Mälkki | c38d543 | 2017-08-20 21:36:18 +0300 | [diff] [blame] | 76 | static int host_completed(u8 status) |
| 77 | { |
| 78 | if (status & SMBHSTSTS_HOST_BUSY) |
| 79 | return 0; |
Kyösti Mälkki | 44206e3 | 2019-02-26 17:17:24 +0200 | [diff] [blame] | 80 | |
| 81 | /* These status bits do not imply completion of transaction. */ |
| 82 | status &= ~(SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INUSE_STS | |
| 83 | SMBHSTSTS_SMBALERT_STS); |
Kyösti Mälkki | c38d543 | 2017-08-20 21:36:18 +0300 | [diff] [blame] | 84 | return status != 0; |
| 85 | } |
| 86 | |
Kyösti Mälkki | 957511c | 2017-08-20 21:36:11 +0300 | [diff] [blame] | 87 | static int recover_master(int smbus_base, int ret) |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 88 | { |
Kyösti Mälkki | 957511c | 2017-08-20 21:36:11 +0300 | [diff] [blame] | 89 | /* TODO: Depending of the failure, drive KILL transaction |
| 90 | * or force soft reset on SMBus master controller. |
| 91 | */ |
| 92 | printk(BIOS_ERR, "SMBus: Fatal master timeout (%d)\n", ret); |
| 93 | return ret; |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 94 | } |
| 95 | |
Kyösti Mälkki | c38d543 | 2017-08-20 21:36:18 +0300 | [diff] [blame] | 96 | static int cb_err_from_stat(u8 status) |
| 97 | { |
Kyösti Mälkki | 44206e3 | 2019-02-26 17:17:24 +0200 | [diff] [blame] | 98 | /* These status bits do not imply errors. */ |
| 99 | status &= ~(SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INUSE_STS | |
| 100 | SMBHSTSTS_SMBALERT_STS); |
Kyösti Mälkki | c38d543 | 2017-08-20 21:36:18 +0300 | [diff] [blame] | 101 | |
| 102 | if (status == SMBHSTSTS_INTR) |
| 103 | return 0; |
| 104 | |
| 105 | return SMBUS_ERROR; |
| 106 | } |
| 107 | |
Kyösti Mälkki | 957511c | 2017-08-20 21:36:11 +0300 | [diff] [blame] | 108 | static int setup_command(unsigned int smbus_base, u8 ctrl, u8 xmitadd) |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 109 | { |
| 110 | unsigned int loops = SMBUS_TIMEOUT; |
Kyösti Mälkki | 957511c | 2017-08-20 21:36:11 +0300 | [diff] [blame] | 111 | u8 host_busy; |
| 112 | |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 113 | do { |
| 114 | smbus_delay(); |
Kyösti Mälkki | 957511c | 2017-08-20 21:36:11 +0300 | [diff] [blame] | 115 | host_busy = inb(smbus_base + SMBHSTSTAT) & SMBHSTSTS_HOST_BUSY; |
| 116 | } while (--loops && host_busy); |
| 117 | |
| 118 | if (loops == 0) |
| 119 | return recover_master(smbus_base, |
| 120 | SMBUS_WAIT_UNTIL_READY_TIMEOUT); |
| 121 | |
| 122 | /* Clear any lingering errors, so the transaction will run. */ |
| 123 | outb(inb(smbus_base + SMBHSTSTAT), smbus_base + SMBHSTSTAT); |
| 124 | |
| 125 | /* Set up transaction */ |
| 126 | /* Disable interrupts */ |
| 127 | outb(ctrl, (smbus_base + SMBHSTCTL)); |
| 128 | |
| 129 | /* Set the device I'm talking to. */ |
| 130 | outb(xmitadd, smbus_base + SMBXMITADD); |
| 131 | |
| 132 | return 0; |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 133 | } |
| 134 | |
Kyösti Mälkki | a2dcf73 | 2017-08-20 21:36:15 +0300 | [diff] [blame] | 135 | static int execute_command(unsigned int smbus_base) |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 136 | { |
Kyösti Mälkki | a2dcf73 | 2017-08-20 21:36:15 +0300 | [diff] [blame] | 137 | unsigned int loops = SMBUS_TIMEOUT; |
| 138 | u8 status; |
| 139 | |
| 140 | /* Start the command. */ |
| 141 | outb((inb(smbus_base + SMBHSTCTL) | SMBHSTCNT_START), |
| 142 | smbus_base + SMBHSTCTL); |
| 143 | |
| 144 | /* Poll for it to start. */ |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 145 | do { |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 146 | smbus_delay(); |
Kyösti Mälkki | a2dcf73 | 2017-08-20 21:36:15 +0300 | [diff] [blame] | 147 | |
| 148 | /* If we poll too slow, we could miss HOST_BUSY flag |
| 149 | * set and detect INTR or x_ERR flags instead here. |
| 150 | */ |
| 151 | status = inb(smbus_base + SMBHSTSTAT); |
| 152 | status &= ~(SMBHSTSTS_SMBALERT_STS | SMBHSTSTS_INUSE_STS); |
| 153 | } while (--loops && status == 0); |
| 154 | |
| 155 | if (loops == 0) |
| 156 | return recover_master(smbus_base, |
| 157 | SMBUS_WAIT_UNTIL_ACTIVE_TIMEOUT); |
| 158 | |
| 159 | return 0; |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 160 | } |
| 161 | |
Kyösti Mälkki | c38d543 | 2017-08-20 21:36:18 +0300 | [diff] [blame] | 162 | static int complete_command(unsigned int smbus_base) |
Kyösti Mälkki | 957511c | 2017-08-20 21:36:11 +0300 | [diff] [blame] | 163 | { |
| 164 | unsigned int loops = SMBUS_TIMEOUT; |
Kyösti Mälkki | c38d543 | 2017-08-20 21:36:18 +0300 | [diff] [blame] | 165 | u8 status; |
| 166 | |
Kyösti Mälkki | 957511c | 2017-08-20 21:36:11 +0300 | [diff] [blame] | 167 | do { |
| 168 | smbus_delay(); |
Kyösti Mälkki | c38d543 | 2017-08-20 21:36:18 +0300 | [diff] [blame] | 169 | status = inb(smbus_base + SMBHSTSTAT); |
| 170 | } while (--loops && !host_completed(status)); |
| 171 | |
| 172 | if (loops == 0) |
| 173 | return recover_master(smbus_base, |
| 174 | SMBUS_WAIT_UNTIL_DONE_TIMEOUT); |
| 175 | |
| 176 | return cb_err_from_stat(status); |
Kyösti Mälkki | 957511c | 2017-08-20 21:36:11 +0300 | [diff] [blame] | 177 | } |
| 178 | |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 179 | int do_smbus_read_byte(unsigned int smbus_base, u8 device, |
| 180 | unsigned int address) |
| 181 | { |
Kyösti Mälkki | 957511c | 2017-08-20 21:36:11 +0300 | [diff] [blame] | 182 | int ret; |
Kyösti Mälkki | c38d543 | 2017-08-20 21:36:18 +0300 | [diff] [blame] | 183 | u8 byte; |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 184 | |
Kyösti Mälkki | 957511c | 2017-08-20 21:36:11 +0300 | [diff] [blame] | 185 | /* Set up for a byte data read. */ |
| 186 | ret = setup_command(smbus_base, I801_BYTE_DATA, XMIT_READ(device)); |
| 187 | if (ret < 0) |
| 188 | return ret; |
| 189 | |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 190 | /* Set the command/address... */ |
Kyösti Mälkki | 957511c | 2017-08-20 21:36:11 +0300 | [diff] [blame] | 191 | outb(address, smbus_base + SMBHSTCMD); |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 192 | |
| 193 | /* Clear the data byte... */ |
| 194 | outb(0, smbus_base + SMBHSTDAT0); |
| 195 | |
| 196 | /* Start the command */ |
Kyösti Mälkki | a2dcf73 | 2017-08-20 21:36:15 +0300 | [diff] [blame] | 197 | ret = execute_command(smbus_base); |
| 198 | if (ret < 0) |
| 199 | return ret; |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 200 | |
| 201 | /* Poll for transaction completion */ |
Kyösti Mälkki | c38d543 | 2017-08-20 21:36:18 +0300 | [diff] [blame] | 202 | ret = complete_command(smbus_base); |
| 203 | if (ret < 0) |
| 204 | return ret; |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 205 | |
| 206 | /* Read results of transaction */ |
| 207 | byte = inb(smbus_base + SMBHSTDAT0); |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 208 | return byte; |
| 209 | } |
| 210 | |
| 211 | int do_smbus_write_byte(unsigned int smbus_base, u8 device, |
| 212 | unsigned int address, unsigned int data) |
| 213 | { |
Kyösti Mälkki | 957511c | 2017-08-20 21:36:11 +0300 | [diff] [blame] | 214 | int ret; |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 215 | |
Kyösti Mälkki | 957511c | 2017-08-20 21:36:11 +0300 | [diff] [blame] | 216 | /* Set up for a byte data write. */ |
| 217 | ret = setup_command(smbus_base, I801_BYTE_DATA, XMIT_WRITE(device)); |
| 218 | if (ret < 0) |
| 219 | return ret; |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 220 | |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 221 | /* Set the command/address... */ |
Kyösti Mälkki | 957511c | 2017-08-20 21:36:11 +0300 | [diff] [blame] | 222 | outb(address, smbus_base + SMBHSTCMD); |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 223 | |
Kyösti Mälkki | 957511c | 2017-08-20 21:36:11 +0300 | [diff] [blame] | 224 | /* Set the data byte... */ |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 225 | outb(data, smbus_base + SMBHSTDAT0); |
| 226 | |
| 227 | /* Start the command */ |
Kyösti Mälkki | a2dcf73 | 2017-08-20 21:36:15 +0300 | [diff] [blame] | 228 | ret = execute_command(smbus_base); |
| 229 | if (ret < 0) |
| 230 | return ret; |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 231 | |
| 232 | /* Poll for transaction completion */ |
Kyösti Mälkki | c38d543 | 2017-08-20 21:36:18 +0300 | [diff] [blame] | 233 | return complete_command(smbus_base); |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 234 | } |
| 235 | |
Kyösti Mälkki | 893edee | 2017-08-20 21:36:24 +0300 | [diff] [blame] | 236 | static int block_cmd_loop(unsigned int smbus_base, |
| 237 | u8 *buf, const unsigned int max_bytes, int flags) |
| 238 | { |
| 239 | u8 status; |
| 240 | unsigned int loops = SMBUS_TIMEOUT; |
| 241 | int ret, bytes = 0; |
| 242 | int is_write_cmd = flags & BLOCK_WRITE; |
| 243 | int sw_drives_nak = flags & BLOCK_I2C; |
| 244 | |
| 245 | /* Hardware limitations. */ |
| 246 | if (flags == (BLOCK_WRITE | BLOCK_I2C)) |
| 247 | return SMBUS_ERROR; |
| 248 | |
Kyösti Mälkki | d6c15d0 | 2017-08-20 21:36:24 +0300 | [diff] [blame] | 249 | /* Set number of bytes to transfer. */ |
| 250 | /* Reset number of bytes to transfer so we notice later it |
| 251 | * was really updated with the transaction. */ |
| 252 | if (!sw_drives_nak) { |
| 253 | if (is_write_cmd) |
| 254 | outb(max_bytes, smbus_base + SMBHSTDAT0); |
| 255 | else |
| 256 | outb(0, smbus_base + SMBHSTDAT0); |
| 257 | } |
| 258 | |
| 259 | /* Send first byte from buffer, bytes_sent increments after |
| 260 | * hardware acknowledges it. |
| 261 | */ |
| 262 | if (is_write_cmd) |
| 263 | outb(*buf++, smbus_base + SMBBLKDAT); |
| 264 | |
| 265 | /* Start the command */ |
| 266 | ret = execute_command(smbus_base); |
| 267 | if (ret < 0) |
| 268 | return ret; |
| 269 | |
Kyösti Mälkki | 893edee | 2017-08-20 21:36:24 +0300 | [diff] [blame] | 270 | /* Poll for transaction completion */ |
| 271 | do { |
| 272 | status = inb(smbus_base + SMBHSTSTAT); |
| 273 | |
| 274 | if (status & SMBHSTSTS_BYTE_DONE) { /* Byte done */ |
| 275 | |
| 276 | if (is_write_cmd) { |
| 277 | bytes++; |
| 278 | if (bytes < max_bytes) |
| 279 | outb(*buf++, smbus_base + SMBBLKDAT); |
| 280 | } else { |
| 281 | if (bytes < max_bytes) |
| 282 | *buf++ = inb(smbus_base + SMBBLKDAT); |
| 283 | bytes++; |
| 284 | |
| 285 | /* Indicate that next byte is the last one. */ |
| 286 | if (sw_drives_nak && (bytes + 1 >= max_bytes)) { |
| 287 | outb(inb(smbus_base + SMBHSTCTL) |
| 288 | | SMBHSTCNT_LAST_BYTE, |
| 289 | smbus_base + SMBHSTCTL); |
| 290 | } |
| 291 | |
| 292 | } |
| 293 | |
| 294 | /* Engine internally completes the transaction |
| 295 | * and clears HOST_BUSY flag once the byte count |
| 296 | * has been reached or LAST_BYTE was set. |
| 297 | */ |
| 298 | outb(SMBHSTSTS_BYTE_DONE, smbus_base + SMBHSTSTAT); |
| 299 | } |
| 300 | |
| 301 | } while (--loops && !host_completed(status)); |
| 302 | |
| 303 | dprintk("%s: status = %02x, len = %d / %d, loops = %d\n", |
| 304 | __func__, status, bytes, max_bytes, SMBUS_TIMEOUT - loops); |
| 305 | |
| 306 | if (loops == 0) |
| 307 | return recover_master(smbus_base, |
| 308 | SMBUS_WAIT_UNTIL_DONE_TIMEOUT); |
| 309 | |
| 310 | ret = cb_err_from_stat(status); |
| 311 | if (ret < 0) |
| 312 | return ret; |
| 313 | |
| 314 | return bytes; |
| 315 | } |
| 316 | |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 317 | int do_smbus_block_read(unsigned int smbus_base, u8 device, u8 cmd, |
Arthur Heymans | 1b04aa2 | 2017-08-04 14:28:50 +0200 | [diff] [blame] | 318 | unsigned int max_bytes, u8 *buf) |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 319 | { |
Kyösti Mälkki | 957511c | 2017-08-20 21:36:11 +0300 | [diff] [blame] | 320 | int ret, slave_bytes; |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 321 | |
Kyösti Mälkki | c17e855 | 2017-08-20 23:48:23 +0300 | [diff] [blame] | 322 | max_bytes = MIN(SMBUS_BLOCK_MAXLEN, max_bytes); |
Arthur Heymans | 1b04aa2 | 2017-08-04 14:28:50 +0200 | [diff] [blame] | 323 | |
Kyösti Mälkki | 957511c | 2017-08-20 21:36:11 +0300 | [diff] [blame] | 324 | /* Set up for a block data read. */ |
| 325 | ret = setup_command(smbus_base, I801_BLOCK_DATA, XMIT_READ(device)); |
| 326 | if (ret < 0) |
| 327 | return ret; |
| 328 | |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 329 | /* Set the command/address... */ |
Kyösti Mälkki | 957511c | 2017-08-20 21:36:11 +0300 | [diff] [blame] | 330 | outb(cmd, smbus_base + SMBHSTCMD); |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 331 | |
Kyösti Mälkki | d6c15d0 | 2017-08-20 21:36:24 +0300 | [diff] [blame] | 332 | /* Execute block transaction. */ |
Kyösti Mälkki | 893edee | 2017-08-20 21:36:24 +0300 | [diff] [blame] | 333 | ret = block_cmd_loop(smbus_base, buf, max_bytes, BLOCK_READ); |
Kyösti Mälkki | c38d543 | 2017-08-20 21:36:18 +0300 | [diff] [blame] | 334 | if (ret < 0) |
| 335 | return ret; |
| 336 | |
Kyösti Mälkki | 893edee | 2017-08-20 21:36:24 +0300 | [diff] [blame] | 337 | /* Post-check we received complete message. */ |
| 338 | slave_bytes = inb(smbus_base + SMBHSTDAT0); |
| 339 | if (ret < slave_bytes) |
Arthur Heymans | 1b04aa2 | 2017-08-04 14:28:50 +0200 | [diff] [blame] | 340 | return SMBUS_ERROR; |
| 341 | |
Kyösti Mälkki | 893edee | 2017-08-20 21:36:24 +0300 | [diff] [blame] | 342 | return ret; |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 343 | } |
| 344 | |
| 345 | int do_smbus_block_write(unsigned int smbus_base, u8 device, u8 cmd, |
Arthur Heymans | 1b04aa2 | 2017-08-04 14:28:50 +0200 | [diff] [blame] | 346 | const unsigned int bytes, const u8 *buf) |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 347 | { |
Kyösti Mälkki | 893edee | 2017-08-20 21:36:24 +0300 | [diff] [blame] | 348 | int ret; |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 349 | |
Kyösti Mälkki | c17e855 | 2017-08-20 23:48:23 +0300 | [diff] [blame] | 350 | if (bytes > SMBUS_BLOCK_MAXLEN) |
Arthur Heymans | 1b04aa2 | 2017-08-04 14:28:50 +0200 | [diff] [blame] | 351 | return SMBUS_ERROR; |
| 352 | |
Kyösti Mälkki | 957511c | 2017-08-20 21:36:11 +0300 | [diff] [blame] | 353 | /* Set up for a block data write. */ |
| 354 | ret = setup_command(smbus_base, I801_BLOCK_DATA, XMIT_WRITE(device)); |
| 355 | if (ret < 0) |
| 356 | return ret; |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 357 | |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 358 | /* Set the command/address... */ |
Kyösti Mälkki | 957511c | 2017-08-20 21:36:11 +0300 | [diff] [blame] | 359 | outb(cmd, smbus_base + SMBHSTCMD); |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 360 | |
Kyösti Mälkki | d6c15d0 | 2017-08-20 21:36:24 +0300 | [diff] [blame] | 361 | /* Execute block transaction. */ |
Kyösti Mälkki | 893edee | 2017-08-20 21:36:24 +0300 | [diff] [blame] | 362 | ret = block_cmd_loop(smbus_base, (u8 *)buf, bytes, BLOCK_WRITE); |
Kyösti Mälkki | c38d543 | 2017-08-20 21:36:18 +0300 | [diff] [blame] | 363 | if (ret < 0) |
| 364 | return ret; |
| 365 | |
Kyösti Mälkki | 893edee | 2017-08-20 21:36:24 +0300 | [diff] [blame] | 366 | if (ret < bytes) |
Kyösti Mälkki | c17e855 | 2017-08-20 23:48:23 +0300 | [diff] [blame] | 367 | return SMBUS_ERROR; |
| 368 | |
Kyösti Mälkki | 893edee | 2017-08-20 21:36:24 +0300 | [diff] [blame] | 369 | return ret; |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 370 | } |
| 371 | |
| 372 | /* Only since ICH5 */ |
Kyösti Mälkki | c01a505 | 2019-01-30 09:39:23 +0200 | [diff] [blame] | 373 | static int has_i2c_read_command(void) |
| 374 | { |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 375 | if (CONFIG(SOUTHBRIDGE_INTEL_I82371EB) || |
| 376 | CONFIG(SOUTHBRIDGE_INTEL_I82801DX)) |
Kyösti Mälkki | c01a505 | 2019-01-30 09:39:23 +0200 | [diff] [blame] | 377 | return 0; |
| 378 | return 1; |
| 379 | } |
| 380 | |
| 381 | int do_i2c_eeprom_read(unsigned int smbus_base, u8 device, |
Kyösti Mälkki | 1e39236 | 2017-08-20 21:36:03 +0300 | [diff] [blame] | 382 | unsigned int offset, const unsigned int bytes, u8 *buf) |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 383 | { |
Kyösti Mälkki | 893edee | 2017-08-20 21:36:24 +0300 | [diff] [blame] | 384 | int ret; |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 385 | |
Kyösti Mälkki | c01a505 | 2019-01-30 09:39:23 +0200 | [diff] [blame] | 386 | if (!has_i2c_read_command()) |
| 387 | return SMBUS_ERROR; |
| 388 | |
Kyösti Mälkki | 957511c | 2017-08-20 21:36:11 +0300 | [diff] [blame] | 389 | /* Set up for a i2c block data read. |
| 390 | * |
| 391 | * FIXME: Address parameter changes to XMIT_READ(device) with |
| 392 | * some revision of PCH. Presumably hardware revisions that |
| 393 | * do not have i2c block write support internally set LSB. |
| 394 | */ |
| 395 | ret = setup_command(smbus_base, I801_I2C_BLOCK_DATA, |
| 396 | XMIT_WRITE(device)); |
| 397 | if (ret < 0) |
| 398 | return ret; |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 399 | |
| 400 | /* device offset */ |
| 401 | outb(offset, smbus_base + SMBHSTDAT1); |
| 402 | |
Kyösti Mälkki | d6c15d0 | 2017-08-20 21:36:24 +0300 | [diff] [blame] | 403 | /* Execute block transaction. */ |
Kyösti Mälkki | 893edee | 2017-08-20 21:36:24 +0300 | [diff] [blame] | 404 | ret = block_cmd_loop(smbus_base, buf, bytes, BLOCK_READ | BLOCK_I2C); |
Kyösti Mälkki | c38d543 | 2017-08-20 21:36:18 +0300 | [diff] [blame] | 405 | if (ret < 0) |
| 406 | return ret; |
| 407 | |
Kyösti Mälkki | 893edee | 2017-08-20 21:36:24 +0300 | [diff] [blame] | 408 | /* Post-check we received complete message. */ |
| 409 | if (ret < bytes) |
Kyösti Mälkki | 1e39236 | 2017-08-20 21:36:03 +0300 | [diff] [blame] | 410 | return SMBUS_ERROR; |
| 411 | |
Kyösti Mälkki | 893edee | 2017-08-20 21:36:24 +0300 | [diff] [blame] | 412 | return ret; |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 413 | } |
Frans Hendriks | e48be35 | 2019-06-19 11:01:27 +0200 | [diff] [blame^] | 414 | |
| 415 | /* |
| 416 | * The caller is responsible of settings HOSTC I2C_EN bit prior to making this |
| 417 | * call! |
| 418 | */ |
| 419 | int do_i2c_block_write(unsigned int smbus_base, u8 device, |
| 420 | unsigned int bytes, u8 *buf) |
| 421 | { |
| 422 | u8 cmd; |
| 423 | int ret; |
| 424 | |
| 425 | if (!CONFIG(SOC_INTEL_BRASWELL)) |
| 426 | return SMBUS_ERROR; |
| 427 | |
| 428 | if (!bytes || (bytes > SMBUS_BLOCK_MAXLEN)) |
| 429 | return SMBUS_ERROR; |
| 430 | |
| 431 | /* Set up for a block data write. */ |
| 432 | ret = setup_command(smbus_base, I801_BLOCK_DATA, XMIT_WRITE(device)); |
| 433 | if (ret < 0) |
| 434 | return ret; |
| 435 | |
| 436 | /* |
| 437 | * In i2c mode SMBus controller sequence on bus will be: |
| 438 | * <SMBXINTADD> <SMBHSTDAT1> <SMBBLKDAT> .. <SMBBLKDAT> |
| 439 | * The SMBHSTCMD must be written also to ensure the SMBUs controller |
| 440 | * will generate the i2c sequence. |
| 441 | */ |
| 442 | cmd = *buf++; |
| 443 | bytes--; |
| 444 | outb(cmd, smbus_base + SMBHSTCMD); |
| 445 | outb(cmd, smbus_base + SMBHSTDAT1); |
| 446 | |
| 447 | /* Execute block transaction. */ |
| 448 | ret = block_cmd_loop(smbus_base, buf, bytes, BLOCK_WRITE); |
| 449 | if (ret < 0) |
| 450 | return ret; |
| 451 | |
| 452 | if (ret < bytes) |
| 453 | return SMBUS_ERROR; |
| 454 | |
| 455 | ret++; /* 1st byte has been written using SMBHSTDAT1 */ |
| 456 | return ret; |
| 457 | } |