Angel Pons | 4b42983 | 2020-04-02 23:48:50 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 2 | |
Arthur Heymans | 17ad459 | 2018-08-06 15:35:28 +0200 | [diff] [blame] | 3 | #include <cbmem.h> |
Angel Pons | b9bbed2 | 2020-08-03 15:11:55 +0200 | [diff] [blame] | 4 | #include <commonlib/helpers.h> |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 5 | #include <console/console.h> |
Elyes HAOUAS | 748caed | 2019-12-19 17:02:08 +0100 | [diff] [blame] | 6 | #include <device/pci_def.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 7 | #include <device/pci_ops.h> |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 8 | #include <stdint.h> |
| 9 | #include <device/device.h> |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 10 | #include <boot/tables.h> |
Furquan Shaikh | 76cedd2 | 2020-05-02 10:24:23 -0700 | [diff] [blame] | 11 | #include <acpi/acpi.h> |
Kyösti Mälkki | f091f4d | 2019-08-14 03:49:21 +0300 | [diff] [blame] | 12 | #include <cpu/intel/smm_reloc.h> |
Elyes HAOUAS | a1e22b8 | 2019-03-18 22:49:36 +0100 | [diff] [blame] | 13 | |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 14 | #include "chip.h" |
| 15 | #include "gm45.h" |
| 16 | |
Elyes HAOUAS | 6dcdaaf | 2018-02-09 07:44:31 +0100 | [diff] [blame] | 17 | static void mch_domain_read_resources(struct device *dev) |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 18 | { |
| 19 | u64 tom, touud; |
Arthur Heymans | 17ad459 | 2018-08-06 15:35:28 +0200 | [diff] [blame] | 20 | u32 tomk, tolud, uma_sizek = 0, delta_cbmem; |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 21 | |
| 22 | /* Total Memory 2GB example: |
| 23 | * |
| 24 | * 00000000 0000MB-2014MB 2014MB RAM (writeback) |
| 25 | * 7de00000 2014MB-2016MB 2MB GFX GTT (uncached) |
| 26 | * 7e000000 2016MB-2048MB 32MB GFX UMA (uncached) |
| 27 | * 80000000 2048MB TOLUD |
| 28 | * 80000000 2048MB TOM |
| 29 | * |
| 30 | * Total Memory 4GB example: |
| 31 | * |
| 32 | * 00000000 0000MB-3038MB 3038MB RAM (writeback) |
| 33 | * bde00000 3038MB-3040MB 2MB GFX GTT (uncached) |
| 34 | * be000000 3040MB-3072MB 32MB GFX UMA (uncached) |
| 35 | * be000000 3072MB TOLUD |
| 36 | * 100000000 4096MB TOM |
| 37 | * 100000000 4096MB-5120MB 1024MB RAM (writeback) |
| 38 | * 140000000 5120MB TOUUD |
| 39 | */ |
| 40 | |
| 41 | pci_domain_read_resources(dev); |
| 42 | |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 43 | struct device *mch = pcidev_on_root(0, 0); |
Arthur Heymans | 8908931 | 2018-06-26 21:01:40 +0200 | [diff] [blame] | 44 | |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 45 | /* Top of Upper Usable DRAM, including remap */ |
Arthur Heymans | 8908931 | 2018-06-26 21:01:40 +0200 | [diff] [blame] | 46 | touud = pci_read_config16(mch, D0F0_TOUUD); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 47 | touud <<= 20; |
| 48 | |
| 49 | /* Top of Lower Usable DRAM */ |
Arthur Heymans | 8908931 | 2018-06-26 21:01:40 +0200 | [diff] [blame] | 50 | tolud = pci_read_config16(mch, D0F0_TOLUD) & 0xfff0; |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 51 | tolud <<= 16; |
| 52 | |
| 53 | /* Top of Memory - does not account for any UMA */ |
Arthur Heymans | 8908931 | 2018-06-26 21:01:40 +0200 | [diff] [blame] | 54 | tom = pci_read_config16(mch, D0F0_TOM) & 0x1ff; |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 55 | tom <<= 27; |
| 56 | |
| 57 | printk(BIOS_DEBUG, "TOUUD 0x%llx TOLUD 0x%08x TOM 0x%llx\n", |
| 58 | touud, tolud, tom); |
| 59 | |
| 60 | tomk = tolud >> 10; |
| 61 | |
| 62 | /* Graphics memory comes next */ |
Arthur Heymans | 8908931 | 2018-06-26 21:01:40 +0200 | [diff] [blame] | 63 | const u16 ggc = pci_read_config16(mch, D0F0_GGC); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 64 | if (!(ggc & 2)) { |
| 65 | printk(BIOS_DEBUG, "IGD decoded, subtracting "); |
| 66 | |
| 67 | /* Graphics memory */ |
| 68 | const u32 gms_sizek = decode_igd_memory_size((ggc >> 4) & 0xf); |
Arthur Heymans | 8b76605 | 2018-01-24 23:25:13 +0100 | [diff] [blame] | 69 | printk(BIOS_DEBUG, "%uM UMA, ", gms_sizek >> 10); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 70 | tomk -= gms_sizek; |
| 71 | |
| 72 | /* GTT Graphics Stolen Memory Size (GGMS) */ |
| 73 | const u32 gsm_sizek = decode_igd_gtt_size((ggc >> 8) & 0xf); |
Arthur Heymans | 8b76605 | 2018-01-24 23:25:13 +0100 | [diff] [blame] | 74 | printk(BIOS_DEBUG, "%uM GTT", gsm_sizek >> 10); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 75 | tomk -= gsm_sizek; |
| 76 | |
| 77 | uma_sizek = gms_sizek + gsm_sizek; |
| 78 | } |
Arthur Heymans | 8908931 | 2018-06-26 21:01:40 +0200 | [diff] [blame] | 79 | const u8 esmramc = pci_read_config8(mch, D0F0_ESMRAMC); |
Arthur Heymans | 8b76605 | 2018-01-24 23:25:13 +0100 | [diff] [blame] | 80 | const u32 tseg_sizek = decode_tseg_size(esmramc); |
| 81 | printk(BIOS_DEBUG, " and %uM TSEG\n", tseg_sizek >> 10); |
| 82 | tomk -= tseg_sizek; |
| 83 | uma_sizek += tseg_sizek; |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 84 | |
Arthur Heymans | 17ad459 | 2018-08-06 15:35:28 +0200 | [diff] [blame] | 85 | /* cbmem_top can be shifted downwards due to alignment. |
| 86 | Mark the region between cbmem_top and tomk as unusable */ |
| 87 | delta_cbmem = tomk - ((uint32_t)cbmem_top() >> 10); |
| 88 | tomk -= delta_cbmem; |
| 89 | uma_sizek += delta_cbmem; |
| 90 | |
| 91 | printk(BIOS_DEBUG, "Unused RAM between cbmem_top and TOM: 0x%xK\n", |
| 92 | delta_cbmem); |
| 93 | |
Nico Huber | ca3e121 | 2017-10-02 20:07:53 +0200 | [diff] [blame] | 94 | printk(BIOS_INFO, "Available memory below 4GB: %uM\n", tomk >> 10); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 95 | |
Nico Huber | 58ba83f | 2021-01-17 21:50:55 +0100 | [diff] [blame] | 96 | /* Report lowest memory region */ |
| 97 | ram_resource(dev, 3, 0, 0xa0000 / KiB); |
| 98 | |
| 99 | /* |
| 100 | * Reserve everything between A segment and 1MB: |
| 101 | * |
| 102 | * 0xa0000 - 0xbffff: Legacy VGA |
| 103 | * 0xc0000 - 0xfffff: RAM |
| 104 | */ |
| 105 | mmio_resource(dev, 4, 0xa0000 / KiB, (0xc0000 - 0xa0000) / KiB); |
| 106 | reserved_ram_resource(dev, 5, 0xc0000 / KiB, (1*MiB - 0xc0000) / KiB); |
| 107 | |
| 108 | /* Report < 4GB memory */ |
| 109 | ram_resource(dev, 6, 1*MiB / KiB, tomk - 1*MiB / KiB); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 110 | |
| 111 | /* |
| 112 | * If >= 4GB installed then memory from TOLUD to 4GB |
| 113 | * is remapped above TOM, TOUUD will account for both |
| 114 | */ |
| 115 | touud >>= 10; /* Convert to KB */ |
| 116 | if (touud > 4096 * 1024) { |
Nico Huber | 58ba83f | 2021-01-17 21:50:55 +0100 | [diff] [blame] | 117 | ram_resource(dev, 7, 4096 * 1024, touud - (4096 * 1024)); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 118 | printk(BIOS_INFO, "Available memory above 4GB: %lluM\n", |
| 119 | (touud >> 10) - 4096); |
| 120 | } |
| 121 | |
| 122 | printk(BIOS_DEBUG, "Adding UMA memory area base=0x%llx " |
| 123 | "size=0x%llx\n", ((u64)tomk) << 10, ((u64)uma_sizek) << 10); |
| 124 | /* Don't use uma_resource() as our UMA touches the PCI hole. */ |
Nico Huber | 58ba83f | 2021-01-17 21:50:55 +0100 | [diff] [blame] | 125 | fixed_mem_resource(dev, 8, tomk, uma_sizek, IORESOURCE_RESERVE); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 126 | |
Angel Pons | 1ac6f8b | 2021-01-20 13:13:26 +0100 | [diff] [blame^] | 127 | mmconf_resource(dev, 9); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 128 | } |
| 129 | |
Elyes HAOUAS | 6dcdaaf | 2018-02-09 07:44:31 +0100 | [diff] [blame] | 130 | static void mch_domain_set_resources(struct device *dev) |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 131 | { |
| 132 | struct resource *resource; |
| 133 | int i; |
| 134 | |
Nico Huber | 58ba83f | 2021-01-17 21:50:55 +0100 | [diff] [blame] | 135 | for (i = 3; i <= 9; ++i) { |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 136 | /* Report read resources. */ |
Vladimir Serbinenko | 40412c6 | 2014-11-12 00:09:20 +0100 | [diff] [blame] | 137 | resource = probe_resource(dev, i); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 138 | if (resource) |
| 139 | report_resource_stored(dev, resource, ""); |
| 140 | } |
| 141 | |
| 142 | assign_resources(dev->link_list); |
| 143 | } |
| 144 | |
Elyes HAOUAS | 6dcdaaf | 2018-02-09 07:44:31 +0100 | [diff] [blame] | 145 | static void mch_domain_init(struct device *dev) |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 146 | { |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 147 | struct device *mch = pcidev_on_root(0, 0); |
Arthur Heymans | 8908931 | 2018-06-26 21:01:40 +0200 | [diff] [blame] | 148 | |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 149 | /* Enable SERR */ |
Elyes HAOUAS | 5ac723e | 2020-04-29 09:09:12 +0200 | [diff] [blame] | 150 | pci_or_config16(mch, PCI_COMMAND, PCI_COMMAND_SERR); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 151 | } |
| 152 | |
Arthur Heymans | e798e6a | 2017-12-23 23:09:54 +0100 | [diff] [blame] | 153 | static const char *northbridge_acpi_name(const struct device *dev) |
| 154 | { |
| 155 | if (dev->path.type == DEVICE_PATH_DOMAIN) |
| 156 | return "PCI0"; |
| 157 | |
| 158 | if (dev->path.type != DEVICE_PATH_PCI || dev->bus->secondary != 0) |
| 159 | return NULL; |
| 160 | |
| 161 | switch (dev->path.pci.devfn) { |
| 162 | case PCI_DEVFN(0, 0): |
| 163 | return "MCHC"; |
| 164 | } |
| 165 | |
| 166 | return NULL; |
| 167 | } |
| 168 | |
Arthur Heymans | aade90e | 2018-01-25 00:33:45 +0100 | [diff] [blame] | 169 | void northbridge_write_smram(u8 smram) |
| 170 | { |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 171 | struct device *dev = pcidev_on_root(0, 0); |
Arthur Heymans | 48fa922 | 2018-11-19 13:08:01 +0100 | [diff] [blame] | 172 | |
| 173 | if (dev == NULL) |
| 174 | die("could not find pci 00:00.0!\n"); |
| 175 | |
| 176 | pci_write_config8(dev, D0F0_SMRAM, smram); |
Arthur Heymans | aade90e | 2018-01-25 00:33:45 +0100 | [diff] [blame] | 177 | } |
| 178 | |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 179 | static struct device_operations pci_domain_ops = { |
| 180 | .read_resources = mch_domain_read_resources, |
| 181 | .set_resources = mch_domain_set_resources, |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 182 | .init = mch_domain_init, |
| 183 | .scan_bus = pci_domain_scan_bus, |
Vladimir Serbinenko | 33769a5 | 2014-08-30 22:39:20 +0200 | [diff] [blame] | 184 | .write_acpi_tables = northbridge_write_acpi_tables, |
Nico Huber | 68680dd | 2020-03-31 17:34:52 +0200 | [diff] [blame] | 185 | .acpi_fill_ssdt = generate_cpu_entries, |
Arthur Heymans | e798e6a | 2017-12-23 23:09:54 +0100 | [diff] [blame] | 186 | .acpi_name = northbridge_acpi_name, |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 187 | }; |
| 188 | |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 189 | static struct device_operations cpu_bus_ops = { |
Nico Huber | 2f8ba69 | 2020-04-05 14:05:24 +0200 | [diff] [blame] | 190 | .read_resources = noop_read_resources, |
| 191 | .set_resources = noop_set_resources, |
Kyösti Mälkki | b3267e0 | 2019-08-13 16:44:04 +0300 | [diff] [blame] | 192 | .init = mp_cpu_bus_init, |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 193 | }; |
| 194 | |
Elyes HAOUAS | 6dcdaaf | 2018-02-09 07:44:31 +0100 | [diff] [blame] | 195 | static void enable_dev(struct device *dev) |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 196 | { |
| 197 | /* Set the operations if it is a special bus type */ |
Stefan Reinauer | 4aff445 | 2013-02-12 14:17:15 -0800 | [diff] [blame] | 198 | if (dev->path.type == DEVICE_PATH_DOMAIN) { |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 199 | dev->ops = &pci_domain_ops; |
Stefan Reinauer | 0aa37c4 | 2013-02-12 15:20:54 -0800 | [diff] [blame] | 200 | } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 201 | dev->ops = &cpu_bus_ops; |
| 202 | } |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 203 | } |
| 204 | |
| 205 | static void gm45_init(void *const chip_info) |
| 206 | { |
| 207 | int dev, fn, bit_base; |
| 208 | |
Kyösti Mälkki | 98a9174 | 2018-05-21 21:29:16 +0300 | [diff] [blame] | 209 | struct device *const d0f0 = pcidev_on_root(0x0, 0); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 210 | |
| 211 | /* Hide internal functions based on devicetree info. */ |
| 212 | for (dev = 3; dev > 0; --dev) { |
| 213 | switch (dev) { |
| 214 | case 3: /* ME */ |
| 215 | fn = 3; |
| 216 | bit_base = 6; |
| 217 | break; |
| 218 | case 2: /* IGD */ |
| 219 | fn = 1; |
| 220 | bit_base = 3; |
| 221 | break; |
| 222 | case 1: /* PEG */ |
| 223 | fn = 0; |
| 224 | bit_base = 1; |
| 225 | break; |
| 226 | } |
| 227 | for (; fn >= 0; --fn) { |
Angel Pons | b053583 | 2020-06-08 11:46:58 +0200 | [diff] [blame] | 228 | const struct device *const d = pcidev_on_root(dev, fn); |
| 229 | if (!d || d->enabled) |
| 230 | continue; |
| 231 | /* FIXME: Using bitwise ops changes the binary */ |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 232 | pci_write_config32(d0f0, D0F0_DEVEN, |
Angel Pons | b053583 | 2020-06-08 11:46:58 +0200 | [diff] [blame] | 233 | pci_read_config32(d0f0, D0F0_DEVEN) & ~(1 << (bit_base + fn))); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 234 | } |
| 235 | } |
| 236 | |
| 237 | const u32 deven = pci_read_config32(d0f0, D0F0_DEVEN); |
| 238 | if (!(deven & (0xf << 6))) |
| 239 | pci_write_config32(d0f0, D0F0_DEVEN, deven & ~(1 << 14)); |
| 240 | } |
| 241 | |
| 242 | struct chip_operations northbridge_intel_gm45_ops = { |
| 243 | CHIP_NAME("Intel GM45 Northbridge") |
| 244 | .enable_dev = enable_dev, |
| 245 | .init = gm45_init, |
| 246 | }; |