Johanna Schander | 431d008 | 2019-07-22 09:24:14 +0200 | [diff] [blame] | 1 | chip soc/intel/skylake |
Johanna Schander | 431d008 | 2019-07-22 09:24:14 +0200 | [diff] [blame] | 2 | register "deep_s3_enable_ac" = "0" |
| 3 | register "deep_s3_enable_dc" = "0" |
| 4 | register "deep_s5_enable_ac" = "0" |
| 5 | register "deep_s5_enable_dc" = "0" |
| 6 | register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" |
| 7 | |
| 8 | register "eist_enable" = "1" |
| 9 | |
| 10 | # GPE configuration |
| 11 | # Note that GPE events called out in ASL code rely on this |
| 12 | # route. i.e. If this route changes then the affected GPE |
| 13 | # offset bits also need to be changed. |
| 14 | register "gpe0_dw0" = "GPP_C" |
| 15 | register "gpe0_dw1" = "GPP_D" |
| 16 | register "gpe0_dw2" = "GPP_E" |
| 17 | |
Michael Niewöhner | c5f1dc9 | 2021-04-10 22:51:15 +0200 | [diff] [blame] | 18 | register "gen1_dec" = "0x000c0681" |
| 19 | register "gen2_dec" = "0x000c1641" |
Johanna Schander | 431d008 | 2019-07-22 09:24:14 +0200 | [diff] [blame] | 20 | |
Johanna Schander | 431d008 | 2019-07-22 09:24:14 +0200 | [diff] [blame] | 21 | # Disable DPTF |
| 22 | register "dptf_enable" = "0" |
| 23 | |
| 24 | # FSP Configuration |
Johanna Schander | 431d008 | 2019-07-22 09:24:14 +0200 | [diff] [blame] | 25 | register "SataSalpSupport" = "0" |
Felix Singer | 9a1b47e | 2023-10-23 17:37:21 +0200 | [diff] [blame] | 26 | register "SataPortsEnable" = "{ |
| 27 | [0] = 0, |
| 28 | [1] = 0, |
| 29 | [2] = 0, |
| 30 | }" |
Johanna Schander | 431d008 | 2019-07-22 09:24:14 +0200 | [diff] [blame] | 31 | register "DspEnable" = "0" |
| 32 | register "IoBufferOwnership" = "0" |
Johanna Schander | 431d008 | 2019-07-22 09:24:14 +0200 | [diff] [blame] | 33 | register "SsicPortEnable" = "0" |
Johanna Schander | 431d008 | 2019-07-22 09:24:14 +0200 | [diff] [blame] | 34 | register "ScsEmmcHs400Enabled" = "0" |
Johanna Schander | 431d008 | 2019-07-22 09:24:14 +0200 | [diff] [blame] | 35 | register "SkipExtGfxScan" = "1" |
Johanna Schander | 431d008 | 2019-07-22 09:24:14 +0200 | [diff] [blame] | 36 | register "SaGv" = "SaGv_Enabled" |
| 37 | register "PmConfigSlpS3MinAssert" = "2" # 50ms |
| 38 | register "PmConfigSlpS4MinAssert" = "1" # 1s |
| 39 | register "PmConfigSlpSusMinAssert" = "3" # 500ms |
| 40 | register "PmConfigSlpAMinAssert" = "3" # 2s |
Johanna Schander | 431d008 | 2019-07-22 09:24:14 +0200 | [diff] [blame] | 41 | |
| 42 | register "serirq_mode" = "SERIRQ_CONTINUOUS" |
| 43 | |
Johanna Schander | 431d008 | 2019-07-22 09:24:14 +0200 | [diff] [blame] | 44 | # VR Settings Configuration for 4 Domains |
| 45 | #+----------------+-----------+-----------+-------------+----------+ |
| 46 | #| Domain/Setting | SA | IA | GT Unsliced | GT | |
| 47 | #+----------------+-----------+-----------+-------------+----------+ |
| 48 | #| Psi1Threshold | 20A | 20A | 20A | 20A | |
| 49 | #| Psi2Threshold | 4A | 5A | 5A | 5A | |
| 50 | #| Psi3Threshold | 1A | 1A | 1A | 1A | |
| 51 | #| Psi3Enable | 1 | 1 | 1 | 1 | |
| 52 | #| Psi4Enable | 1 | 1 | 1 | 1 | |
| 53 | #| ImonSlope | 0 | 0 | 0 | 0 | |
| 54 | #| ImonOffset | 0 | 0 | 0 | 0 | |
| 55 | #| IccMax | 6A | 64A | 31A | 31A | |
| 56 | #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | |
| 57 | #+----------------+-----------+-----------+-------------+----------+ |
| 58 | register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ |
| 59 | .vr_config_enable = 1, |
| 60 | .psi1threshold = VR_CFG_AMP(20), |
| 61 | .psi2threshold = VR_CFG_AMP(4), |
| 62 | .psi3threshold = VR_CFG_AMP(1), |
| 63 | .psi3enable = 0, |
| 64 | .psi4enable = 0, |
| 65 | .imon_slope = 0x0, |
| 66 | .imon_offset = 0x0, |
| 67 | .icc_max = VR_CFG_AMP(6), |
| 68 | .voltage_limit = 1520, |
| 69 | .ac_loadline = 1030, |
| 70 | .dc_loadline = 1030, |
| 71 | }" |
| 72 | |
| 73 | register "domain_vr_config[VR_IA_CORE]" = "{ |
| 74 | .vr_config_enable = 1, |
| 75 | .psi1threshold = VR_CFG_AMP(20), |
| 76 | .psi2threshold = VR_CFG_AMP(5), |
| 77 | .psi3threshold = VR_CFG_AMP(1), |
| 78 | .psi3enable = 0, |
| 79 | .psi4enable = 0, |
| 80 | .imon_slope = 0x0, |
| 81 | .imon_offset = 0x0, |
| 82 | .icc_max = VR_CFG_AMP(64), |
| 83 | .voltage_limit = 1520, |
| 84 | .ac_loadline = 240, |
| 85 | .dc_loadline = 240, |
| 86 | }" |
| 87 | |
| 88 | register "domain_vr_config[VR_GT_UNSLICED]" = "{ |
| 89 | .vr_config_enable = 1, |
| 90 | .psi1threshold = VR_CFG_AMP(20), |
| 91 | .psi2threshold = VR_CFG_AMP(5), |
| 92 | .psi3threshold = VR_CFG_AMP(1), |
| 93 | .psi3enable = 0, |
| 94 | .psi4enable = 0, |
| 95 | .imon_slope = 0x0, |
| 96 | .imon_offset = 0x0, |
| 97 | .icc_max = VR_CFG_AMP(31), |
| 98 | .voltage_limit = 1520, |
| 99 | .ac_loadline = 310, |
| 100 | .dc_loadline = 310, |
| 101 | }" |
| 102 | |
| 103 | register "domain_vr_config[VR_GT_SLICED]" = "{ |
| 104 | .vr_config_enable = 1, |
| 105 | .psi1threshold = VR_CFG_AMP(20), |
| 106 | .psi2threshold = VR_CFG_AMP(5), |
| 107 | .psi3threshold = VR_CFG_AMP(1), |
| 108 | .psi3enable = 0, |
| 109 | .psi4enable = 0, |
| 110 | .imon_slope = 0x0, |
| 111 | .imon_offset = 0x0, |
| 112 | .icc_max = VR_CFG_AMP(31), |
| 113 | .voltage_limit = 1520, |
| 114 | .ac_loadline = 310, |
| 115 | .dc_loadline = 310, |
| 116 | }" |
| 117 | |
| 118 | # Enable Root Ports 3, 5 and 9 |
| 119 | register "PcieRpEnable[2]" = "1" |
| 120 | register "PcieRpEnable[4]" = "1" |
| 121 | register "PcieRpEnable[8]" = "1" |
| 122 | |
| 123 | register "PcieRpLtrEnable[2]" = "1" |
| 124 | register "PcieRpLtrEnable[4]" = "1" |
| 125 | register "PcieRpLtrEnable[8]" = "1" |
| 126 | |
| 127 | register "PcieRpHotPlug[4]" = "1" |
| 128 | |
Johanna Schander | 431d008 | 2019-07-22 09:24:14 +0200 | [diff] [blame] | 129 | # PL1 override 25W |
Johanna Schander | 431d008 | 2019-07-22 09:24:14 +0200 | [diff] [blame] | 130 | # PL2 override 44W |
Sumeet R Pawnikar | 97c5464 | 2020-05-10 01:24:11 +0530 | [diff] [blame] | 131 | register "power_limits_config" = "{ |
| 132 | .tdp_pl1_override = 25, |
| 133 | .tdp_pl2_override = 44, |
| 134 | }" |
Johanna Schander | 431d008 | 2019-07-22 09:24:14 +0200 | [diff] [blame] | 135 | |
| 136 | # Send an extra VR mailbox command for the PS4 exit issue |
| 137 | register "SendVrMbxCmd" = "2" |
| 138 | |
Felix Singer | 21b5a9a | 2023-10-23 07:26:28 +0200 | [diff] [blame] | 139 | register "SerialIoDevMode" = "{ |
| 140 | [PchSerialIoIndexI2C0] = PchSerialIoPci, |
| 141 | [PchSerialIoIndexI2C1] = PchSerialIoPci, |
| 142 | [PchSerialIoIndexI2C2] = PchSerialIoDisabled, |
| 143 | [PchSerialIoIndexI2C3] = PchSerialIoDisabled, |
| 144 | [PchSerialIoIndexI2C4] = PchSerialIoDisabled, |
| 145 | [PchSerialIoIndexI2C5] = PchSerialIoDisabled, |
| 146 | [PchSerialIoIndexSpi0] = PchSerialIoDisabled, |
| 147 | [PchSerialIoIndexSpi1] = PchSerialIoDisabled, |
| 148 | [PchSerialIoIndexUart0] = PchSerialIoDisabled, |
| 149 | [PchSerialIoIndexUart1] = PchSerialIoDisabled, |
| 150 | [PchSerialIoIndexUart2] = PchSerialIoDisabled, |
Johanna Schander | 431d008 | 2019-07-22 09:24:14 +0200 | [diff] [blame] | 151 | }" |
| 152 | |
Johanna Schander | 431d008 | 2019-07-22 09:24:14 +0200 | [diff] [blame] | 153 | device domain 0 on |
Reagan Bohan | 8979955 | 2024-05-15 08:54:15 +0000 | [diff] [blame] | 154 | device ref igpu on |
| 155 | register "gfx" = "GMA_STATIC_DISPLAYS(0)" |
| 156 | |
| 157 | register "panel_cfg" = "{ |
| 158 | .up_delay_ms = 200, |
| 159 | .down_delay_ms = 50, |
| 160 | .cycle_delay_ms = 500, |
| 161 | .backlight_on_delay_ms = 1, |
| 162 | .backlight_off_delay_ms = 200, |
| 163 | .backlight_pwm_hz = 200, |
| 164 | }" |
| 165 | end |
Felix Singer | 3d98710 | 2023-11-16 01:39:05 +0100 | [diff] [blame] | 166 | device ref sa_thermal on end |
| 167 | device ref south_xhci on end |
| 168 | device ref thermal on end |
| 169 | device ref i2c0 on end |
| 170 | device ref i2c1 on |
Johanna Schander | 431d008 | 2019-07-22 09:24:14 +0200 | [diff] [blame] | 171 | chip drivers/i2c/hid |
| 172 | register "generic.hid" = ""PNP0C50"" |
| 173 | register "generic.desc" = ""Synaptics Touchpad"" |
Karthikeyan Ramasubramanian | e49dfb6 | 2021-02-09 15:05:17 -0700 | [diff] [blame] | 174 | register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E7_IRQ)" |
Matt DeVillier | 2cf52d8 | 2022-09-01 15:09:24 -0500 | [diff] [blame] | 175 | register "generic.detect" = "1" |
Johanna Schander | 431d008 | 2019-07-22 09:24:14 +0200 | [diff] [blame] | 176 | register "hid_desc_reg_offset" = "0x20" |
| 177 | device i2c 0x2c on end |
| 178 | end |
Felix Singer | 3d98710 | 2023-11-16 01:39:05 +0100 | [diff] [blame] | 179 | end |
| 180 | device ref heci1 on end |
| 181 | device ref uart2 on end |
| 182 | device ref pcie_rp1 on end |
| 183 | device ref pcie_rp5 on end |
| 184 | device ref pcie_rp9 on end |
| 185 | device ref lpc_espi on |
Johanna Schander | 431d008 | 2019-07-22 09:24:14 +0200 | [diff] [blame] | 186 | chip superio/ite/it8528e |
| 187 | device pnp 6e.1 off end |
| 188 | device pnp 6e.2 off end |
| 189 | device pnp 6e.3 off end |
| 190 | device pnp 6e.4 off end |
| 191 | device pnp 6e.5 off end |
| 192 | device pnp 6e.6 off end |
| 193 | device pnp 6e.a off end |
| 194 | device pnp 6e.f off end |
| 195 | device pnp 6e.10 off end |
| 196 | device pnp 6e.11 off end |
| 197 | device pnp 6e.12 off end |
| 198 | device pnp 6e.13 off end |
| 199 | device pnp 6e.14 off end |
| 200 | device pnp 6e.17 off end |
| 201 | device pnp 6e.18 off end |
| 202 | device pnp 6e.19 off end |
| 203 | end #superio/ite/it8528e |
Felix Singer | 3d98710 | 2023-11-16 01:39:05 +0100 | [diff] [blame] | 204 | end |
| 205 | device ref hda on end |
| 206 | device ref smbus on end |
| 207 | device ref fast_spi on end |
Johanna Schander | 431d008 | 2019-07-22 09:24:14 +0200 | [diff] [blame] | 208 | end |
| 209 | end |