Johanna Schander | 431d008 | 2019-07-22 09:24:14 +0200 | [diff] [blame] | 1 | chip soc/intel/skylake |
Johanna Schander | 431d008 | 2019-07-22 09:24:14 +0200 | [diff] [blame] | 2 | register "deep_s3_enable_ac" = "0" |
| 3 | register "deep_s3_enable_dc" = "0" |
| 4 | register "deep_s5_enable_ac" = "0" |
| 5 | register "deep_s5_enable_dc" = "0" |
| 6 | register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" |
| 7 | |
| 8 | register "eist_enable" = "1" |
| 9 | |
| 10 | # GPE configuration |
| 11 | # Note that GPE events called out in ASL code rely on this |
| 12 | # route. i.e. If this route changes then the affected GPE |
| 13 | # offset bits also need to be changed. |
| 14 | register "gpe0_dw0" = "GPP_C" |
| 15 | register "gpe0_dw1" = "GPP_D" |
| 16 | register "gpe0_dw2" = "GPP_E" |
| 17 | |
Michael Niewöhner | c5f1dc9 | 2021-04-10 22:51:15 +0200 | [diff] [blame^] | 18 | register "gen1_dec" = "0x000c0681" |
| 19 | register "gen2_dec" = "0x000c1641" |
Johanna Schander | 431d008 | 2019-07-22 09:24:14 +0200 | [diff] [blame] | 20 | |
Johanna Schander | 431d008 | 2019-07-22 09:24:14 +0200 | [diff] [blame] | 21 | # Disable DPTF |
| 22 | register "dptf_enable" = "0" |
| 23 | |
| 24 | # FSP Configuration |
Johanna Schander | 431d008 | 2019-07-22 09:24:14 +0200 | [diff] [blame] | 25 | register "SataSalpSupport" = "0" |
| 26 | register "SataMode" = "0" |
| 27 | register "SataPortsEnable[0]" = "0" |
| 28 | register "SataPortsEnable[1]" = "0" |
| 29 | register "SataPortsEnable[2]" = "0" |
Johanna Schander | 431d008 | 2019-07-22 09:24:14 +0200 | [diff] [blame] | 30 | register "DspEnable" = "0" |
| 31 | register "IoBufferOwnership" = "0" |
Johanna Schander | 431d008 | 2019-07-22 09:24:14 +0200 | [diff] [blame] | 32 | register "SsicPortEnable" = "0" |
Johanna Schander | 431d008 | 2019-07-22 09:24:14 +0200 | [diff] [blame] | 33 | register "ScsEmmcHs400Enabled" = "0" |
Johanna Schander | 431d008 | 2019-07-22 09:24:14 +0200 | [diff] [blame] | 34 | register "SkipExtGfxScan" = "1" |
Johanna Schander | 431d008 | 2019-07-22 09:24:14 +0200 | [diff] [blame] | 35 | register "HeciEnabled" = "1" |
| 36 | register "SaGv" = "SaGv_Enabled" |
| 37 | register "PmConfigSlpS3MinAssert" = "2" # 50ms |
| 38 | register "PmConfigSlpS4MinAssert" = "1" # 1s |
| 39 | register "PmConfigSlpSusMinAssert" = "3" # 500ms |
| 40 | register "PmConfigSlpAMinAssert" = "3" # 2s |
Johanna Schander | 431d008 | 2019-07-22 09:24:14 +0200 | [diff] [blame] | 41 | |
| 42 | register "serirq_mode" = "SERIRQ_CONTINUOUS" |
| 43 | |
Johanna Schander | 431d008 | 2019-07-22 09:24:14 +0200 | [diff] [blame] | 44 | # VR Settings Configuration for 4 Domains |
| 45 | #+----------------+-----------+-----------+-------------+----------+ |
| 46 | #| Domain/Setting | SA | IA | GT Unsliced | GT | |
| 47 | #+----------------+-----------+-----------+-------------+----------+ |
| 48 | #| Psi1Threshold | 20A | 20A | 20A | 20A | |
| 49 | #| Psi2Threshold | 4A | 5A | 5A | 5A | |
| 50 | #| Psi3Threshold | 1A | 1A | 1A | 1A | |
| 51 | #| Psi3Enable | 1 | 1 | 1 | 1 | |
| 52 | #| Psi4Enable | 1 | 1 | 1 | 1 | |
| 53 | #| ImonSlope | 0 | 0 | 0 | 0 | |
| 54 | #| ImonOffset | 0 | 0 | 0 | 0 | |
| 55 | #| IccMax | 6A | 64A | 31A | 31A | |
| 56 | #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | |
| 57 | #+----------------+-----------+-----------+-------------+----------+ |
| 58 | register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ |
| 59 | .vr_config_enable = 1, |
| 60 | .psi1threshold = VR_CFG_AMP(20), |
| 61 | .psi2threshold = VR_CFG_AMP(4), |
| 62 | .psi3threshold = VR_CFG_AMP(1), |
| 63 | .psi3enable = 0, |
| 64 | .psi4enable = 0, |
| 65 | .imon_slope = 0x0, |
| 66 | .imon_offset = 0x0, |
| 67 | .icc_max = VR_CFG_AMP(6), |
| 68 | .voltage_limit = 1520, |
| 69 | .ac_loadline = 1030, |
| 70 | .dc_loadline = 1030, |
| 71 | }" |
| 72 | |
| 73 | register "domain_vr_config[VR_IA_CORE]" = "{ |
| 74 | .vr_config_enable = 1, |
| 75 | .psi1threshold = VR_CFG_AMP(20), |
| 76 | .psi2threshold = VR_CFG_AMP(5), |
| 77 | .psi3threshold = VR_CFG_AMP(1), |
| 78 | .psi3enable = 0, |
| 79 | .psi4enable = 0, |
| 80 | .imon_slope = 0x0, |
| 81 | .imon_offset = 0x0, |
| 82 | .icc_max = VR_CFG_AMP(64), |
| 83 | .voltage_limit = 1520, |
| 84 | .ac_loadline = 240, |
| 85 | .dc_loadline = 240, |
| 86 | }" |
| 87 | |
| 88 | register "domain_vr_config[VR_GT_UNSLICED]" = "{ |
| 89 | .vr_config_enable = 1, |
| 90 | .psi1threshold = VR_CFG_AMP(20), |
| 91 | .psi2threshold = VR_CFG_AMP(5), |
| 92 | .psi3threshold = VR_CFG_AMP(1), |
| 93 | .psi3enable = 0, |
| 94 | .psi4enable = 0, |
| 95 | .imon_slope = 0x0, |
| 96 | .imon_offset = 0x0, |
| 97 | .icc_max = VR_CFG_AMP(31), |
| 98 | .voltage_limit = 1520, |
| 99 | .ac_loadline = 310, |
| 100 | .dc_loadline = 310, |
| 101 | }" |
| 102 | |
| 103 | register "domain_vr_config[VR_GT_SLICED]" = "{ |
| 104 | .vr_config_enable = 1, |
| 105 | .psi1threshold = VR_CFG_AMP(20), |
| 106 | .psi2threshold = VR_CFG_AMP(5), |
| 107 | .psi3threshold = VR_CFG_AMP(1), |
| 108 | .psi3enable = 0, |
| 109 | .psi4enable = 0, |
| 110 | .imon_slope = 0x0, |
| 111 | .imon_offset = 0x0, |
| 112 | .icc_max = VR_CFG_AMP(31), |
| 113 | .voltage_limit = 1520, |
| 114 | .ac_loadline = 310, |
| 115 | .dc_loadline = 310, |
| 116 | }" |
| 117 | |
| 118 | # Enable Root Ports 3, 5 and 9 |
| 119 | register "PcieRpEnable[2]" = "1" |
| 120 | register "PcieRpEnable[4]" = "1" |
| 121 | register "PcieRpEnable[8]" = "1" |
| 122 | |
| 123 | register "PcieRpLtrEnable[2]" = "1" |
| 124 | register "PcieRpLtrEnable[4]" = "1" |
| 125 | register "PcieRpLtrEnable[8]" = "1" |
| 126 | |
| 127 | register "PcieRpHotPlug[4]" = "1" |
| 128 | |
| 129 | # USB |
| 130 | register "usb2_ports[0]" = "USB2_PORT_MID(OC1)" # Type-A Port (right) |
| 131 | register "usb2_ports[1]" = "USB2_PORT_MID(OC1)" # Type-A Port (left) |
| 132 | |
| 133 | register "usb2_ports[2]" = "USB2_PORT_MID(OC1)" # TODO Unknown. Maybe USBC? |
| 134 | register "usb2_ports[3]" = "USB2_PORT_MID(OC1)" # TODO Unknown. Maybe USBC? |
| 135 | register "usb2_ports[4]" = "USB2_PORT_MID(OC1)" # TODO Unknown. Maybe USBC? |
| 136 | register "usb2_ports[5]" = "USB2_PORT_MID(OC1)" # TODO Unknown. Maybe USBC? |
| 137 | |
| 138 | register "usb2_ports[6]" = "USB2_PORT_FLEX(OC2)" # Camera |
| 139 | register "usb2_ports[7]" = "USB2_PORT_FLEX(OC2)" # Keyboard |
| 140 | register "usb2_ports[8]" = "USB2_PORT_FLEX(OC2)" # Touchscreen |
| 141 | |
| 142 | register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (left) |
| 143 | register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (right) |
| 144 | |
| 145 | register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC1)" # TODO Unknown. Maybe USBC? |
| 146 | |
| 147 | # PL1 override 25W |
Johanna Schander | 431d008 | 2019-07-22 09:24:14 +0200 | [diff] [blame] | 148 | # PL2 override 44W |
Sumeet R Pawnikar | 97c5464 | 2020-05-10 01:24:11 +0530 | [diff] [blame] | 149 | register "power_limits_config" = "{ |
| 150 | .tdp_pl1_override = 25, |
| 151 | .tdp_pl2_override = 44, |
| 152 | }" |
Johanna Schander | 431d008 | 2019-07-22 09:24:14 +0200 | [diff] [blame] | 153 | |
| 154 | # Send an extra VR mailbox command for the PS4 exit issue |
| 155 | register "SendVrMbxCmd" = "2" |
| 156 | |
| 157 | # Lock Down |
| 158 | register "common_soc_config" = "{ |
| 159 | .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, |
| 160 | }" |
| 161 | |
| 162 | register "SerialIoDevMode" = "{ \ |
| 163 | [PchSerialIoIndexI2C0] = PchSerialIoPci, \ |
| 164 | [PchSerialIoIndexI2C1] = PchSerialIoPci, \ |
| 165 | [PchSerialIoIndexI2C2] = PchSerialIoDisabled, \ |
| 166 | [PchSerialIoIndexI2C3] = PchSerialIoDisabled, \ |
| 167 | [PchSerialIoIndexI2C4] = PchSerialIoDisabled, \ |
| 168 | [PchSerialIoIndexI2C5] = PchSerialIoDisabled, \ |
| 169 | [PchSerialIoIndexSpi0] = PchSerialIoDisabled, \ |
| 170 | [PchSerialIoIndexSpi1] = PchSerialIoDisabled, \ |
| 171 | [PchSerialIoIndexUart0] = PchSerialIoDisabled, \ |
| 172 | [PchSerialIoIndexUart1] = PchSerialIoDisabled, \ |
| 173 | [PchSerialIoIndexUart2] = PchSerialIoDisabled, \ |
| 174 | }" |
| 175 | |
| 176 | device cpu_cluster 0 on |
| 177 | device lapic 0 on end |
| 178 | end |
| 179 | device domain 0 on |
| 180 | device pci 00.0 on end # Host Bridge |
| 181 | device pci 02.0 on end # Integrated Graphics Device |
Felix Singer | 9c1c009 | 2020-07-29 20:48:08 +0200 | [diff] [blame] | 182 | device pci 04.0 on end # Thermal Subsystem |
Johanna Schander | 431d008 | 2019-07-22 09:24:14 +0200 | [diff] [blame] | 183 | device pci 08.0 off end # Gaussian Mixture Model |
| 184 | device pci 14.0 on end # USB xHCI |
| 185 | device pci 14.1 off end # USB xDCI (OTG) |
| 186 | device pci 14.2 on end # Thermal Subsystem |
Felix Singer | e218667 | 2020-07-29 23:20:52 +0200 | [diff] [blame] | 187 | device pci 14.3 off end # Camera |
Johanna Schander | 431d008 | 2019-07-22 09:24:14 +0200 | [diff] [blame] | 188 | device pci 15.0 on end # I2C Controller #0 |
| 189 | device pci 15.1 on |
| 190 | chip drivers/i2c/hid |
| 191 | register "generic.hid" = ""PNP0C50"" |
| 192 | register "generic.desc" = ""Synaptics Touchpad"" |
Karthikeyan Ramasubramanian | e49dfb6 | 2021-02-09 15:05:17 -0700 | [diff] [blame] | 193 | register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E7_IRQ)" |
Johanna Schander | 431d008 | 2019-07-22 09:24:14 +0200 | [diff] [blame] | 194 | register "generic.probed" = "1" |
| 195 | register "hid_desc_reg_offset" = "0x20" |
| 196 | device i2c 0x2c on end |
| 197 | end |
| 198 | end # I2C Controller #1 |
| 199 | device pci 15.2 off end # I2C Controller #2 |
| 200 | device pci 15.3 off end # I2C Controller #3 |
| 201 | device pci 16.0 on end # Management Engine Interface 1 |
| 202 | device pci 16.1 off end # Management Engine Interface 2 |
| 203 | device pci 16.2 off end # Management Engine IDE-R |
| 204 | device pci 16.3 off end # Management Engine KT Redirection |
| 205 | device pci 16.4 off end # Management Engine Interface 3 |
| 206 | device pci 17.0 off end # SATA |
| 207 | device pci 19.0 on end # I2C Controller #4 |
| 208 | device pci 19.1 off end # I2C Controller #5 |
| 209 | device pci 19.2 off end # UART #2 |
| 210 | device pci 1c.0 on end # PCI Express Port 1 |
| 211 | device pci 1c.1 off end # PCI Express Port 2 |
| 212 | device pci 1c.2 off end # PCI Express Port 3 |
| 213 | device pci 1c.3 off end # PCI Express Port 4 |
| 214 | device pci 1c.4 on end # PCI Express Port 5 |
| 215 | device pci 1c.5 off end # PCI Express Port 6 |
| 216 | device pci 1c.6 off end # PCI Express Port 7 |
| 217 | device pci 1c.7 off end # PCI Express Port 8 |
| 218 | device pci 1d.0 on end # PCI Express Port 9 |
| 219 | device pci 1d.1 off end # PCI Express Port 10 |
| 220 | device pci 1d.2 off end # PCI Express Port 11 |
| 221 | device pci 1d.3 off end # PCI Express Port 12 |
| 222 | device pci 1e.0 on end # Serial IO UART0 |
Felix Singer | 5291952 | 2020-07-29 21:44:36 +0200 | [diff] [blame] | 223 | device pci 1e.6 off end # SDXC |
Johanna Schander | 431d008 | 2019-07-22 09:24:14 +0200 | [diff] [blame] | 224 | device pci 1f.0 on # LPC |
| 225 | chip drivers/pc80/tpm |
| 226 | device pnp 0c31.0 on end |
| 227 | end |
| 228 | chip superio/ite/it8528e |
| 229 | device pnp 6e.1 off end |
| 230 | device pnp 6e.2 off end |
| 231 | device pnp 6e.3 off end |
| 232 | device pnp 6e.4 off end |
| 233 | device pnp 6e.5 off end |
| 234 | device pnp 6e.6 off end |
| 235 | device pnp 6e.a off end |
| 236 | device pnp 6e.f off end |
| 237 | device pnp 6e.10 off end |
| 238 | device pnp 6e.11 off end |
| 239 | device pnp 6e.12 off end |
| 240 | device pnp 6e.13 off end |
| 241 | device pnp 6e.14 off end |
| 242 | device pnp 6e.17 off end |
| 243 | device pnp 6e.18 off end |
| 244 | device pnp 6e.19 off end |
| 245 | end #superio/ite/it8528e |
| 246 | end # LPC Bridge |
| 247 | device pci 1f.1 on end # P2SB |
| 248 | device pci 1f.2 on end # Power Management Controller |
| 249 | device pci 1f.3 on end # Intel HDA |
| 250 | device pci 1f.4 on end # SMBus |
| 251 | device pci 1f.5 on end # PCH SPI |
| 252 | device pci 1f.6 off end # GbE |
| 253 | end |
| 254 | end |