Johanna Schander | 431d008 | 2019-07-22 09:24:14 +0200 | [diff] [blame] | 1 | chip soc/intel/skylake |
Johanna Schander | 431d008 | 2019-07-22 09:24:14 +0200 | [diff] [blame] | 2 | register "deep_s3_enable_ac" = "0" |
| 3 | register "deep_s3_enable_dc" = "0" |
| 4 | register "deep_s5_enable_ac" = "0" |
| 5 | register "deep_s5_enable_dc" = "0" |
| 6 | register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" |
| 7 | |
| 8 | register "eist_enable" = "1" |
| 9 | |
| 10 | # GPE configuration |
| 11 | # Note that GPE events called out in ASL code rely on this |
| 12 | # route. i.e. If this route changes then the affected GPE |
| 13 | # offset bits also need to be changed. |
| 14 | register "gpe0_dw0" = "GPP_C" |
| 15 | register "gpe0_dw1" = "GPP_D" |
| 16 | register "gpe0_dw2" = "GPP_E" |
| 17 | |
| 18 | register "gen1_dec" = "0x000c0081" |
| 19 | register "gen2_dec" = "0x000c0681" |
| 20 | register "gen3_dec" = "0x000c1641" |
| 21 | |
| 22 | # Enable "Intel Speed Shift Technology" |
| 23 | register "speed_shift_enable" = "1" |
| 24 | |
| 25 | # Disable DPTF |
| 26 | register "dptf_enable" = "0" |
| 27 | |
| 28 | # FSP Configuration |
| 29 | register "ProbelessTrace" = "0" |
| 30 | register "EnableLan" = "0" |
| 31 | register "EnableSata" = "0" |
| 32 | register "SataSalpSupport" = "0" |
| 33 | register "SataMode" = "0" |
| 34 | register "SataPortsEnable[0]" = "0" |
| 35 | register "SataPortsEnable[1]" = "0" |
| 36 | register "SataPortsEnable[2]" = "0" |
| 37 | register "EnableAzalia" = "1" |
| 38 | register "DspEnable" = "0" |
| 39 | register "IoBufferOwnership" = "0" |
| 40 | register "EnableTraceHub" = "0" |
| 41 | register "SsicPortEnable" = "0" |
| 42 | register "SmbusEnable" = "1" |
| 43 | register "Cio2Enable" = "0" |
| 44 | register "ScsEmmcEnabled" = "0" |
| 45 | register "ScsEmmcHs400Enabled" = "0" |
| 46 | register "ScsSdCardEnabled" = "0" |
| 47 | register "PttSwitch" = "0" |
| 48 | register "SkipExtGfxScan" = "1" |
| 49 | register "Device4Enable" = "1" |
| 50 | register "HeciEnabled" = "1" |
| 51 | register "SaGv" = "SaGv_Enabled" |
| 52 | register "PmConfigSlpS3MinAssert" = "2" # 50ms |
| 53 | register "PmConfigSlpS4MinAssert" = "1" # 1s |
| 54 | register "PmConfigSlpSusMinAssert" = "3" # 500ms |
| 55 | register "PmConfigSlpAMinAssert" = "3" # 2s |
| 56 | register "PmTimerDisabled" = "0" |
| 57 | |
| 58 | register "serirq_mode" = "SERIRQ_CONTINUOUS" |
| 59 | |
| 60 | register "pirqa_routing" = "PCH_IRQ11" |
| 61 | register "pirqb_routing" = "PCH_IRQ10" |
| 62 | register "pirqc_routing" = "PCH_IRQ11" |
| 63 | register "pirqd_routing" = "PCH_IRQ11" |
| 64 | register "pirqe_routing" = "PCH_IRQ11" |
| 65 | register "pirqf_routing" = "PCH_IRQ11" |
| 66 | register "pirqg_routing" = "PCH_IRQ11" |
| 67 | register "pirqh_routing" = "PCH_IRQ11" |
| 68 | |
| 69 | # VR Settings Configuration for 4 Domains |
| 70 | #+----------------+-----------+-----------+-------------+----------+ |
| 71 | #| Domain/Setting | SA | IA | GT Unsliced | GT | |
| 72 | #+----------------+-----------+-----------+-------------+----------+ |
| 73 | #| Psi1Threshold | 20A | 20A | 20A | 20A | |
| 74 | #| Psi2Threshold | 4A | 5A | 5A | 5A | |
| 75 | #| Psi3Threshold | 1A | 1A | 1A | 1A | |
| 76 | #| Psi3Enable | 1 | 1 | 1 | 1 | |
| 77 | #| Psi4Enable | 1 | 1 | 1 | 1 | |
| 78 | #| ImonSlope | 0 | 0 | 0 | 0 | |
| 79 | #| ImonOffset | 0 | 0 | 0 | 0 | |
| 80 | #| IccMax | 6A | 64A | 31A | 31A | |
| 81 | #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | |
| 82 | #+----------------+-----------+-----------+-------------+----------+ |
| 83 | register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ |
| 84 | .vr_config_enable = 1, |
| 85 | .psi1threshold = VR_CFG_AMP(20), |
| 86 | .psi2threshold = VR_CFG_AMP(4), |
| 87 | .psi3threshold = VR_CFG_AMP(1), |
| 88 | .psi3enable = 0, |
| 89 | .psi4enable = 0, |
| 90 | .imon_slope = 0x0, |
| 91 | .imon_offset = 0x0, |
| 92 | .icc_max = VR_CFG_AMP(6), |
| 93 | .voltage_limit = 1520, |
| 94 | .ac_loadline = 1030, |
| 95 | .dc_loadline = 1030, |
| 96 | }" |
| 97 | |
| 98 | register "domain_vr_config[VR_IA_CORE]" = "{ |
| 99 | .vr_config_enable = 1, |
| 100 | .psi1threshold = VR_CFG_AMP(20), |
| 101 | .psi2threshold = VR_CFG_AMP(5), |
| 102 | .psi3threshold = VR_CFG_AMP(1), |
| 103 | .psi3enable = 0, |
| 104 | .psi4enable = 0, |
| 105 | .imon_slope = 0x0, |
| 106 | .imon_offset = 0x0, |
| 107 | .icc_max = VR_CFG_AMP(64), |
| 108 | .voltage_limit = 1520, |
| 109 | .ac_loadline = 240, |
| 110 | .dc_loadline = 240, |
| 111 | }" |
| 112 | |
| 113 | register "domain_vr_config[VR_GT_UNSLICED]" = "{ |
| 114 | .vr_config_enable = 1, |
| 115 | .psi1threshold = VR_CFG_AMP(20), |
| 116 | .psi2threshold = VR_CFG_AMP(5), |
| 117 | .psi3threshold = VR_CFG_AMP(1), |
| 118 | .psi3enable = 0, |
| 119 | .psi4enable = 0, |
| 120 | .imon_slope = 0x0, |
| 121 | .imon_offset = 0x0, |
| 122 | .icc_max = VR_CFG_AMP(31), |
| 123 | .voltage_limit = 1520, |
| 124 | .ac_loadline = 310, |
| 125 | .dc_loadline = 310, |
| 126 | }" |
| 127 | |
| 128 | register "domain_vr_config[VR_GT_SLICED]" = "{ |
| 129 | .vr_config_enable = 1, |
| 130 | .psi1threshold = VR_CFG_AMP(20), |
| 131 | .psi2threshold = VR_CFG_AMP(5), |
| 132 | .psi3threshold = VR_CFG_AMP(1), |
| 133 | .psi3enable = 0, |
| 134 | .psi4enable = 0, |
| 135 | .imon_slope = 0x0, |
| 136 | .imon_offset = 0x0, |
| 137 | .icc_max = VR_CFG_AMP(31), |
| 138 | .voltage_limit = 1520, |
| 139 | .ac_loadline = 310, |
| 140 | .dc_loadline = 310, |
| 141 | }" |
| 142 | |
| 143 | # Enable Root Ports 3, 5 and 9 |
| 144 | register "PcieRpEnable[2]" = "1" |
| 145 | register "PcieRpEnable[4]" = "1" |
| 146 | register "PcieRpEnable[8]" = "1" |
| 147 | |
| 148 | register "PcieRpLtrEnable[2]" = "1" |
| 149 | register "PcieRpLtrEnable[4]" = "1" |
| 150 | register "PcieRpLtrEnable[8]" = "1" |
| 151 | |
| 152 | register "PcieRpHotPlug[4]" = "1" |
| 153 | |
| 154 | # USB |
| 155 | register "usb2_ports[0]" = "USB2_PORT_MID(OC1)" # Type-A Port (right) |
| 156 | register "usb2_ports[1]" = "USB2_PORT_MID(OC1)" # Type-A Port (left) |
| 157 | |
| 158 | register "usb2_ports[2]" = "USB2_PORT_MID(OC1)" # TODO Unknown. Maybe USBC? |
| 159 | register "usb2_ports[3]" = "USB2_PORT_MID(OC1)" # TODO Unknown. Maybe USBC? |
| 160 | register "usb2_ports[4]" = "USB2_PORT_MID(OC1)" # TODO Unknown. Maybe USBC? |
| 161 | register "usb2_ports[5]" = "USB2_PORT_MID(OC1)" # TODO Unknown. Maybe USBC? |
| 162 | |
| 163 | register "usb2_ports[6]" = "USB2_PORT_FLEX(OC2)" # Camera |
| 164 | register "usb2_ports[7]" = "USB2_PORT_FLEX(OC2)" # Keyboard |
| 165 | register "usb2_ports[8]" = "USB2_PORT_FLEX(OC2)" # Touchscreen |
| 166 | |
| 167 | register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (left) |
| 168 | register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (right) |
| 169 | |
| 170 | register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC1)" # TODO Unknown. Maybe USBC? |
| 171 | |
| 172 | # PL1 override 25W |
Johanna Schander | 431d008 | 2019-07-22 09:24:14 +0200 | [diff] [blame] | 173 | # PL2 override 44W |
Sumeet R Pawnikar | 97c5464 | 2020-05-10 01:24:11 +0530 | [diff] [blame^] | 174 | register "power_limits_config" = "{ |
| 175 | .tdp_pl1_override = 25, |
| 176 | .tdp_pl2_override = 44, |
| 177 | }" |
Johanna Schander | 431d008 | 2019-07-22 09:24:14 +0200 | [diff] [blame] | 178 | |
| 179 | # Send an extra VR mailbox command for the PS4 exit issue |
| 180 | register "SendVrMbxCmd" = "2" |
| 181 | |
| 182 | # Lock Down |
| 183 | register "common_soc_config" = "{ |
| 184 | .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, |
| 185 | }" |
| 186 | |
| 187 | register "SerialIoDevMode" = "{ \ |
| 188 | [PchSerialIoIndexI2C0] = PchSerialIoPci, \ |
| 189 | [PchSerialIoIndexI2C1] = PchSerialIoPci, \ |
| 190 | [PchSerialIoIndexI2C2] = PchSerialIoDisabled, \ |
| 191 | [PchSerialIoIndexI2C3] = PchSerialIoDisabled, \ |
| 192 | [PchSerialIoIndexI2C4] = PchSerialIoDisabled, \ |
| 193 | [PchSerialIoIndexI2C5] = PchSerialIoDisabled, \ |
| 194 | [PchSerialIoIndexSpi0] = PchSerialIoDisabled, \ |
| 195 | [PchSerialIoIndexSpi1] = PchSerialIoDisabled, \ |
| 196 | [PchSerialIoIndexUart0] = PchSerialIoDisabled, \ |
| 197 | [PchSerialIoIndexUart1] = PchSerialIoDisabled, \ |
| 198 | [PchSerialIoIndexUart2] = PchSerialIoDisabled, \ |
| 199 | }" |
| 200 | |
| 201 | device cpu_cluster 0 on |
| 202 | device lapic 0 on end |
| 203 | end |
| 204 | device domain 0 on |
| 205 | device pci 00.0 on end # Host Bridge |
| 206 | device pci 02.0 on end # Integrated Graphics Device |
| 207 | device pci 04.0 off end # Thermal Subsystem |
| 208 | device pci 08.0 off end # Gaussian Mixture Model |
| 209 | device pci 14.0 on end # USB xHCI |
| 210 | device pci 14.1 off end # USB xDCI (OTG) |
| 211 | device pci 14.2 on end # Thermal Subsystem |
| 212 | device pci 15.0 on end # I2C Controller #0 |
| 213 | device pci 15.1 on |
| 214 | chip drivers/i2c/hid |
| 215 | register "generic.hid" = ""PNP0C50"" |
| 216 | register "generic.desc" = ""Synaptics Touchpad"" |
| 217 | register "generic.irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_E7_IRQ)" |
| 218 | register "generic.probed" = "1" |
| 219 | register "hid_desc_reg_offset" = "0x20" |
| 220 | device i2c 0x2c on end |
| 221 | end |
| 222 | end # I2C Controller #1 |
| 223 | device pci 15.2 off end # I2C Controller #2 |
| 224 | device pci 15.3 off end # I2C Controller #3 |
| 225 | device pci 16.0 on end # Management Engine Interface 1 |
| 226 | device pci 16.1 off end # Management Engine Interface 2 |
| 227 | device pci 16.2 off end # Management Engine IDE-R |
| 228 | device pci 16.3 off end # Management Engine KT Redirection |
| 229 | device pci 16.4 off end # Management Engine Interface 3 |
| 230 | device pci 17.0 off end # SATA |
| 231 | device pci 19.0 on end # I2C Controller #4 |
| 232 | device pci 19.1 off end # I2C Controller #5 |
| 233 | device pci 19.2 off end # UART #2 |
| 234 | device pci 1c.0 on end # PCI Express Port 1 |
| 235 | device pci 1c.1 off end # PCI Express Port 2 |
| 236 | device pci 1c.2 off end # PCI Express Port 3 |
| 237 | device pci 1c.3 off end # PCI Express Port 4 |
| 238 | device pci 1c.4 on end # PCI Express Port 5 |
| 239 | device pci 1c.5 off end # PCI Express Port 6 |
| 240 | device pci 1c.6 off end # PCI Express Port 7 |
| 241 | device pci 1c.7 off end # PCI Express Port 8 |
| 242 | device pci 1d.0 on end # PCI Express Port 9 |
| 243 | device pci 1d.1 off end # PCI Express Port 10 |
| 244 | device pci 1d.2 off end # PCI Express Port 11 |
| 245 | device pci 1d.3 off end # PCI Express Port 12 |
| 246 | device pci 1e.0 on end # Serial IO UART0 |
| 247 | device pci 1f.0 on # LPC |
| 248 | chip drivers/pc80/tpm |
| 249 | device pnp 0c31.0 on end |
| 250 | end |
| 251 | chip superio/ite/it8528e |
| 252 | device pnp 6e.1 off end |
| 253 | device pnp 6e.2 off end |
| 254 | device pnp 6e.3 off end |
| 255 | device pnp 6e.4 off end |
| 256 | device pnp 6e.5 off end |
| 257 | device pnp 6e.6 off end |
| 258 | device pnp 6e.a off end |
| 259 | device pnp 6e.f off end |
| 260 | device pnp 6e.10 off end |
| 261 | device pnp 6e.11 off end |
| 262 | device pnp 6e.12 off end |
| 263 | device pnp 6e.13 off end |
| 264 | device pnp 6e.14 off end |
| 265 | device pnp 6e.17 off end |
| 266 | device pnp 6e.18 off end |
| 267 | device pnp 6e.19 off end |
| 268 | end #superio/ite/it8528e |
| 269 | end # LPC Bridge |
| 270 | device pci 1f.1 on end # P2SB |
| 271 | device pci 1f.2 on end # Power Management Controller |
| 272 | device pci 1f.3 on end # Intel HDA |
| 273 | device pci 1f.4 on end # SMBus |
| 274 | device pci 1f.5 on end # PCH SPI |
| 275 | device pci 1f.6 off end # GbE |
| 276 | end |
| 277 | end |