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Angel Pons182dbde2020-04-02 23:49:05 +02001/* SPDX-License-Identifier: GPL-2.0-only */
zbao246e84b2012-07-13 18:47:03 +08002
Elyes HAOUAS65fa5982014-07-22 23:12:38 +02003#ifndef _HUDSON_EARLY_SETUP_C_
4#define _HUDSON_EARLY_SETUP_C_
zbao246e84b2012-07-13 18:47:03 +08005
6#include <stdint.h>
Michał Żygowski287ce5f2019-12-01 17:41:23 +01007#include <amdblocks/acpimmio.h>
Kyösti Mälkkif1b58b72019-03-01 13:43:02 +02008#include <device/pci_ops.h>
Elyes HAOUASeb789f02018-10-27 16:40:25 +02009
zbao246e84b2012-07-13 18:47:03 +080010#include "hudson.h"
11
Idwer Volleringc18e5212014-01-06 21:57:56 +000012void hudson_pci_port80(void)
13{
14 u8 byte;
Antonello Dettori8d7181d2016-09-01 16:50:42 +020015 pci_devfn_t dev;
Idwer Volleringc18e5212014-01-06 21:57:56 +000016
17 /* P2P Bridge */
18 dev = PCI_DEV(0, 0x14, 4);
19
20 /* Chip Control: Enable subtractive decoding */
21 byte = pci_read_config8(dev, 0x40);
22 byte |= 1 << 5;
23 pci_write_config8(dev, 0x40, byte);
24
25 /* Misc Control: Enable subtractive decoding if 0x40 bit 5 is set */
26 byte = pci_read_config8(dev, 0x4B);
27 byte |= 1 << 7;
28 pci_write_config8(dev, 0x4B, byte);
29
30 /* The same IO Base and IO Limit here is meaningful because we set the
31 * bridge to be subtractive. During early setup stage, we have to make
32 * sure that data can go through port 0x80.
33 */
34 /* IO Base: 0xf000 */
35 byte = pci_read_config8(dev, 0x1C);
36 byte |= 0xF << 4;
37 pci_write_config8(dev, 0x1C, byte);
38
39 /* IO Limit: 0xf000 */
40 byte = pci_read_config8(dev, 0x1D);
41 byte |= 0xF << 4;
42 pci_write_config8(dev, 0x1D, byte);
43
44 /* PCI Command: Enable IO response */
45 byte = pci_read_config8(dev, 0x04);
46 byte |= 1 << 0;
47 pci_write_config8(dev, 0x04, byte);
48
49 /* LPC controller */
50 dev = PCI_DEV(0, 0x14, 3);
51
52 byte = pci_read_config8(dev, 0x4A);
53 byte &= ~(1 << 5); /* disable lpc port 80 */
54 pci_write_config8(dev, 0x4A, byte);
55}
56
zbao246e84b2012-07-13 18:47:03 +080057void hudson_lpc_port80(void)
58{
59 u8 byte;
zbao246e84b2012-07-13 18:47:03 +080060
zbao246e84b2012-07-13 18:47:03 +080061 /* Enable port 80 LPC decode in pci function 3 configuration space. */
Elyes HAOUAS49f63e02020-04-22 16:14:26 +020062 const pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
zbao246e84b2012-07-13 18:47:03 +080063 byte = pci_read_config8(dev, 0x4a);
Idwer Volleringc18e5212014-01-06 21:57:56 +000064 byte |= 1 << 5; /* enable port 80 */
zbao246e84b2012-07-13 18:47:03 +080065 pci_write_config8(dev, 0x4a, byte);
66}
67
Michał Żygowski8cee45c2019-11-23 18:03:46 +010068void hudson_lpc_decode(void)
69{
Michał Żygowski8cee45c2019-11-23 18:03:46 +010070 u32 tmp;
71
Kyösti Mälkkia244d5e2019-12-09 08:08:58 +020072 /* Enable LPC controller */
73 pm_write8(0xec, pm_read8(0xec) | 0x01);
74
Elyes HAOUAS49f63e02020-04-22 16:14:26 +020075 const pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
Elyes HAOUAS4436ebe2020-01-08 13:04:59 +010076 /* Serial port enumeration on Hudson:
Michał Żygowski8cee45c2019-11-23 18:03:46 +010077 * PORT0 - 0x3f8
78 * PORT1 - 0x2f8
79 * PORT5 - 0x2e8
80 * PORT7 - 0x3e8
81 */
82 tmp = DECODE_ENABLE_SERIAL_PORT0 | DECODE_ENABLE_SERIAL_PORT1
83 | DECODE_ENABLE_SERIAL_PORT5 | DECODE_ENABLE_SERIAL_PORT7;
84
85 pci_write_config32(dev, LPC_IO_PORT_DECODE_ENABLE, tmp);
86}
87
Edward O'Callaghan893a55e2014-12-02 17:44:47 +110088#endif /* _HUDSON_EARLY_SETUP_C_ */