zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2010 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 14 | */ |
| 15 | |
Elyes HAOUAS | 65fa598 | 2014-07-22 23:12:38 +0200 | [diff] [blame] | 16 | #ifndef _HUDSON_EARLY_SETUP_C_ |
| 17 | #define _HUDSON_EARLY_SETUP_C_ |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 18 | |
| 19 | #include <stdint.h> |
Stefan Reinauer | 24d1d4b | 2013-03-21 11:51:41 -0700 | [diff] [blame] | 20 | #include <arch/io.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 21 | #include <device/pci_ops.h> |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 22 | #include <console/console.h> |
Elyes HAOUAS | eb789f0 | 2018-10-27 16:40:25 +0200 | [diff] [blame^] | 23 | |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 24 | #include "hudson.h" |
| 25 | |
Idwer Vollering | c18e521 | 2014-01-06 21:57:56 +0000 | [diff] [blame] | 26 | void hudson_pci_port80(void) |
| 27 | { |
| 28 | u8 byte; |
Antonello Dettori | 8d7181d | 2016-09-01 16:50:42 +0200 | [diff] [blame] | 29 | pci_devfn_t dev; |
Idwer Vollering | c18e521 | 2014-01-06 21:57:56 +0000 | [diff] [blame] | 30 | |
| 31 | /* P2P Bridge */ |
| 32 | dev = PCI_DEV(0, 0x14, 4); |
| 33 | |
| 34 | /* Chip Control: Enable subtractive decoding */ |
| 35 | byte = pci_read_config8(dev, 0x40); |
| 36 | byte |= 1 << 5; |
| 37 | pci_write_config8(dev, 0x40, byte); |
| 38 | |
| 39 | /* Misc Control: Enable subtractive decoding if 0x40 bit 5 is set */ |
| 40 | byte = pci_read_config8(dev, 0x4B); |
| 41 | byte |= 1 << 7; |
| 42 | pci_write_config8(dev, 0x4B, byte); |
| 43 | |
| 44 | /* The same IO Base and IO Limit here is meaningful because we set the |
| 45 | * bridge to be subtractive. During early setup stage, we have to make |
| 46 | * sure that data can go through port 0x80. |
| 47 | */ |
| 48 | /* IO Base: 0xf000 */ |
| 49 | byte = pci_read_config8(dev, 0x1C); |
| 50 | byte |= 0xF << 4; |
| 51 | pci_write_config8(dev, 0x1C, byte); |
| 52 | |
| 53 | /* IO Limit: 0xf000 */ |
| 54 | byte = pci_read_config8(dev, 0x1D); |
| 55 | byte |= 0xF << 4; |
| 56 | pci_write_config8(dev, 0x1D, byte); |
| 57 | |
| 58 | /* PCI Command: Enable IO response */ |
| 59 | byte = pci_read_config8(dev, 0x04); |
| 60 | byte |= 1 << 0; |
| 61 | pci_write_config8(dev, 0x04, byte); |
| 62 | |
| 63 | /* LPC controller */ |
| 64 | dev = PCI_DEV(0, 0x14, 3); |
| 65 | |
| 66 | byte = pci_read_config8(dev, 0x4A); |
| 67 | byte &= ~(1 << 5); /* disable lpc port 80 */ |
| 68 | pci_write_config8(dev, 0x4A, byte); |
| 69 | } |
| 70 | |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 71 | void hudson_lpc_port80(void) |
| 72 | { |
| 73 | u8 byte; |
Antonello Dettori | 8d7181d | 2016-09-01 16:50:42 +0200 | [diff] [blame] | 74 | pci_devfn_t dev; |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 75 | |
| 76 | /* Enable LPC controller */ |
| 77 | outb(0xEC, 0xCD6); |
| 78 | byte = inb(0xCD7); |
| 79 | byte |= 1; |
| 80 | outb(0xEC, 0xCD6); |
| 81 | outb(byte, 0xCD7); |
| 82 | |
| 83 | /* Enable port 80 LPC decode in pci function 3 configuration space. */ |
Idwer Vollering | c18e521 | 2014-01-06 21:57:56 +0000 | [diff] [blame] | 84 | dev = PCI_DEV(0, 0x14, 3); |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 85 | byte = pci_read_config8(dev, 0x4a); |
Idwer Vollering | c18e521 | 2014-01-06 21:57:56 +0000 | [diff] [blame] | 86 | byte |= 1 << 5; /* enable port 80 */ |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 87 | pci_write_config8(dev, 0x4a, byte); |
| 88 | } |
| 89 | |
| 90 | int s3_save_nvram_early(u32 dword, int size, int nvram_pos) |
| 91 | { |
| 92 | int i; |
| 93 | printk(BIOS_DEBUG, "Writing %x of size %d to nvram pos: %d\n", dword, size, nvram_pos); |
| 94 | |
Elyes HAOUAS | c021ffe | 2016-09-18 19:18:56 +0200 | [diff] [blame] | 95 | for (i = 0; i < size; i++) { |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 96 | outb(nvram_pos, BIOSRAM_INDEX); |
Elyes HAOUAS | a342f39 | 2018-10-17 10:56:26 +0200 | [diff] [blame] | 97 | outb((dword >> (8 * i)) & 0xff, BIOSRAM_DATA); |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 98 | nvram_pos++; |
| 99 | } |
| 100 | |
| 101 | return nvram_pos; |
| 102 | } |
| 103 | |
| 104 | int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos) |
| 105 | { |
| 106 | u32 data = *old_dword; |
| 107 | int i; |
Elyes HAOUAS | c021ffe | 2016-09-18 19:18:56 +0200 | [diff] [blame] | 108 | for (i = 0; i < size; i++) { |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 109 | outb(nvram_pos, BIOSRAM_INDEX); |
| 110 | data &= ~(0xff << (i * 8)); |
| 111 | data |= inb(BIOSRAM_DATA) << (i *8); |
| 112 | nvram_pos++; |
| 113 | } |
| 114 | *old_dword = data; |
| 115 | printk(BIOS_DEBUG, "Loading %x of size %d to nvram pos:%d\n", *old_dword, size, |
| 116 | nvram_pos-size); |
| 117 | return nvram_pos; |
| 118 | } |
| 119 | |
Edward O'Callaghan | 893a55e | 2014-12-02 17:44:47 +1100 | [diff] [blame] | 120 | #endif /* _HUDSON_EARLY_SETUP_C_ */ |