Angel Pons | 182dbde | 2020-04-02 23:49:05 +0200 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | /* This file is part of the coreboot project. */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 3 | |
Kyösti Mälkki | de64078 | 2019-12-03 07:30:26 +0200 | [diff] [blame] | 4 | #include <arch/bootblock.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 5 | #include <device/pci_ops.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 6 | #include "pch.h" |
| 7 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 8 | /* |
| 9 | * Enable Prefetching and Caching. |
| 10 | */ |
| 11 | static void enable_spi_prefetch(void) |
| 12 | { |
| 13 | u8 reg8; |
Edward O'Callaghan | 9a817ef | 2014-10-26 10:12:15 +1100 | [diff] [blame] | 14 | pci_devfn_t dev; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 15 | |
| 16 | dev = PCI_DEV(0, 0x1f, 0); |
| 17 | |
| 18 | reg8 = pci_read_config8(dev, 0xdc); |
| 19 | reg8 &= ~(3 << 2); |
| 20 | reg8 |= (2 << 2); /* Prefetching and Caching Enabled */ |
| 21 | pci_write_config8(dev, 0xdc, reg8); |
| 22 | } |
| 23 | |
| 24 | |
| 25 | static void map_rcba(void) |
| 26 | { |
Edward O'Callaghan | 9a817ef | 2014-10-26 10:12:15 +1100 | [diff] [blame] | 27 | pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 28 | |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 29 | pci_write_config32(dev, RCBA, (uintptr_t)DEFAULT_RCBA | 1); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 30 | } |
| 31 | |
| 32 | static void enable_port80_on_lpc(void) |
| 33 | { |
Kyösti Mälkki | b544c00 | 2019-01-06 10:41:41 +0200 | [diff] [blame] | 34 | /* Enable port 80 POST on LPC. The chipset does this by default, |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 35 | * but it doesn't appear to hurt anything. */ |
| 36 | u32 gcs = RCBA32(GCS); |
| 37 | gcs = gcs & ~0x4; |
| 38 | RCBA32(GCS) = gcs; |
| 39 | } |
| 40 | |
| 41 | static void set_spi_speed(void) |
| 42 | { |
| 43 | u32 fdod; |
| 44 | u8 ssfc; |
| 45 | |
| 46 | /* Observe SPI Descriptor Component Section 0 */ |
| 47 | SPIBAR32(FDOC) = 0x1000; |
| 48 | |
| 49 | /* Extract the Write/Erase SPI Frequency from descriptor */ |
| 50 | fdod = SPIBAR32(FDOD); |
| 51 | fdod >>= 24; |
| 52 | fdod &= 7; |
| 53 | |
| 54 | /* Set Software Sequence frequency to match */ |
| 55 | ssfc = SPIBAR8(SSFC + 2); |
| 56 | ssfc &= ~7; |
| 57 | ssfc |= fdod; |
| 58 | SPIBAR8(SSFC + 2) = ssfc; |
| 59 | } |
| 60 | |
Arthur Heymans | 8e646e7 | 2018-06-05 11:19:22 +0200 | [diff] [blame] | 61 | void bootblock_early_southbridge_init(void) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 62 | { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 63 | map_rcba(); |
| 64 | enable_spi_prefetch(); |
| 65 | enable_port80_on_lpc(); |
| 66 | set_spi_speed(); |
| 67 | |
| 68 | /* Enable upper 128bytes of CMOS */ |
| 69 | RCBA32(RC) = (1 << 2); |
Arthur Heymans | d893a26 | 2018-12-19 16:54:06 +0100 | [diff] [blame] | 70 | |
| 71 | pch_enable_lpc(); |
| 72 | mainboard_config_superio(); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 73 | } |