| commit | b544c000565f928813299d0ea19dcae88ac7961e | [log] [tgz] |
|---|---|---|
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | Sun Jan 06 10:41:41 2019 +0200 |
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | Mon Jan 07 10:39:58 2019 +0000 |
| tree | 47576651cc111dc0996392d6f9d510e98dd68415 | |
| parent | 438f86166325e4f8089be5c65b40075d77a0406c [diff] [blame] |
intel/lynxpoint: Fix spelling Change-Id: I684e1962a9d4312ee9fad4ada70323b02ca3ae48 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30687 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
diff --git a/src/southbridge/intel/lynxpoint/bootblock.c b/src/southbridge/intel/lynxpoint/bootblock.c index 20d0ee3..1a9e7bb 100644 --- a/src/southbridge/intel/lynxpoint/bootblock.c +++ b/src/southbridge/intel/lynxpoint/bootblock.c
@@ -54,7 +54,7 @@ static void enable_port80_on_lpc(void) { - /* Enable port 80 POST on LPC. The chipset does this by deafult, + /* Enable port 80 POST on LPC. The chipset does this by default, * but it doesn't appear to hurt anything. */ u32 gcs = RCBA32(GCS); gcs = gcs & ~0x4;