Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 Google Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | #include <arch/io.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 17 | #include <cpu/x86/tsc.h> |
| 18 | #include "pch.h" |
| 19 | |
| 20 | static void store_initial_timestamp(void) |
| 21 | { |
| 22 | /* On Cougar Point we have two 32bit scratchpad registers available: |
| 23 | * D0:F0 0xdc (SKPAD) |
| 24 | * D31:F2 0xd0 (SATA SP) |
| 25 | */ |
| 26 | tsc_t tsc = rdtsc(); |
| 27 | pci_write_config32(PCI_DEV(0, 0x00, 0), 0xdc, tsc.lo); |
| 28 | pci_write_config32(PCI_DEV(0, 0x1f, 2), 0xd0, tsc.hi); |
| 29 | } |
| 30 | |
| 31 | /* |
| 32 | * Enable Prefetching and Caching. |
| 33 | */ |
| 34 | static void enable_spi_prefetch(void) |
| 35 | { |
| 36 | u8 reg8; |
Edward O'Callaghan | 9a817ef | 2014-10-26 10:12:15 +1100 | [diff] [blame] | 37 | pci_devfn_t dev; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 38 | |
| 39 | dev = PCI_DEV(0, 0x1f, 0); |
| 40 | |
| 41 | reg8 = pci_read_config8(dev, 0xdc); |
| 42 | reg8 &= ~(3 << 2); |
| 43 | reg8 |= (2 << 2); /* Prefetching and Caching Enabled */ |
| 44 | pci_write_config8(dev, 0xdc, reg8); |
| 45 | } |
| 46 | |
| 47 | |
| 48 | static void map_rcba(void) |
| 49 | { |
Edward O'Callaghan | 9a817ef | 2014-10-26 10:12:15 +1100 | [diff] [blame] | 50 | pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 51 | |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 52 | pci_write_config32(dev, RCBA, (uintptr_t)DEFAULT_RCBA | 1); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 53 | } |
| 54 | |
| 55 | static void enable_port80_on_lpc(void) |
| 56 | { |
Kyösti Mälkki | b544c00 | 2019-01-06 10:41:41 +0200 | [diff] [blame^] | 57 | /* Enable port 80 POST on LPC. The chipset does this by default, |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 58 | * but it doesn't appear to hurt anything. */ |
| 59 | u32 gcs = RCBA32(GCS); |
| 60 | gcs = gcs & ~0x4; |
| 61 | RCBA32(GCS) = gcs; |
| 62 | } |
| 63 | |
| 64 | static void set_spi_speed(void) |
| 65 | { |
| 66 | u32 fdod; |
| 67 | u8 ssfc; |
| 68 | |
| 69 | /* Observe SPI Descriptor Component Section 0 */ |
| 70 | SPIBAR32(FDOC) = 0x1000; |
| 71 | |
| 72 | /* Extract the Write/Erase SPI Frequency from descriptor */ |
| 73 | fdod = SPIBAR32(FDOD); |
| 74 | fdod >>= 24; |
| 75 | fdod &= 7; |
| 76 | |
| 77 | /* Set Software Sequence frequency to match */ |
| 78 | ssfc = SPIBAR8(SSFC + 2); |
| 79 | ssfc &= ~7; |
| 80 | ssfc |= fdod; |
| 81 | SPIBAR8(SSFC + 2) = ssfc; |
| 82 | } |
| 83 | |
| 84 | static void bootblock_southbridge_init(void) |
| 85 | { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 86 | store_initial_timestamp(); |
Aaron Durbin | 06f1f8f | 2014-11-06 09:58:07 -0600 | [diff] [blame] | 87 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 88 | map_rcba(); |
| 89 | enable_spi_prefetch(); |
| 90 | enable_port80_on_lpc(); |
| 91 | set_spi_speed(); |
| 92 | |
| 93 | /* Enable upper 128bytes of CMOS */ |
| 94 | RCBA32(RC) = (1 << 2); |
| 95 | } |